dingusppc/cpu/ppc/test/ppcdisasmtest.csv

1	# Test data for PowerPC disassembler supplied as comma-separated values
2	# Data format:
3	# instruction address (hex), instruction code (hex), expected disassembly: opcode, [operands...]
4	# unconditional branches
5	0xFFF03008,0x48000355,bl,0xFFF0335C
6	0xFFF03000,0x4280035C,b,0xFFF0335C
7	# bcctr variants with simplified mnemonics
8	0xFFF03000,0x4E800420,bctr
9	0xFFF03000,0x4E800421,bctrl
10	0xFFF03000,0x4C820420,bnectr
11	0xFFF03000,0x4C820421,bnectrl
12	0xFFF03000,0x4C960420,bnectr,cr5
13	0xFFF03000,0x4C920421,bnectrl,cr4
14	0xFFF03000,0x4D980420,bltctr,cr6
15	0xFFF03000,0x4C9D0420,blectr,cr7
16	0xFFF03000,0x4D820420,beqctr
17	0xFFF03000,0x4D960420,beqctr,cr5
18	0xFFF03000,0x4CA80420,bgectr+,cr2
19	0xFFF03000,0x4C980421,bgectrl,cr6
20	0xFFF03000,0x4D810420,bgtctr
21	0xFFF03000,0x4D850420,bgtctr,cr1
22	0xFFF03000,0x4D8B0421,bsoctrl,cr2
23	0xFFF03000,0x4C830420,bnsctr
24	0xFFF03000,0x4C930420,bnsctr,cr4
25	# bclr variants with simplified mnemonics
26	0xFFF03000,0x4E800020,blr
27	0xFFF03000,0x4E800021,blrl
28	0xFFF03000,0x4D800020,bltlr
29	0xFFF03000,0x4D840020,bltlr,cr1
30	0xFFF03000,0x4C810021,blelrl
31	0xFFF03000,0x4C8D0020,blelr,cr3
32	0xFFF03000,0x4DA20020,beqlr+
33	0xFFF03000,0x4DBE0021,beqlrl+,cr7
34	0xFFF03000,0x4CA80020,bgelr+,cr2
35	0xFFF03000,0x4DB90020,bgtlr+,cr6
36	0xFFF03000,0x4C8A0021,bnelrl,cr2
37	0xFFF03000,0x4D930020,bsolr,cr4
38	0xFFF03000,0x4C8F0021,bnslrl,cr3
39	0xFFF03000,0x4E000020,bdnzlr
40	0xFFF03000,0x4E200020,bdnzlr+
41	0xFFF03000,0x4E400020,bdzlr
42	0xFFF03000,0x4E400021,bdzlrl
43	0xFFF03000,0x4E600020,bdzlr+
44	0xFFF03000,0x4C000020,bdnzflr,lt
45	0xFFF03000,0x4C040020,bdnzflr,4*cr1+lt
46	0xFFF03000,0x4C5D0021,bdzflrl,4*cr7+gt
47	0xFFF03000,0x4D020020,bdnztlr,eq
48	0xFFF03000,0x4D530021,bdztlrl,4*cr4+so
49	# conditional branches with simplified mnemonics, primary opcode 0x10
50	0xFFF0011C,0x409E2EE4,bne,cr7,0xFFF03000
51	0xFFF00100,0x40A60098,bne+,cr1,0xFFF00198
52	0xFFF00100,0x41820018,beq,0xFFF00118
53	0xFFF03004,0x41200054,bdnzt+,lt,0xFFF03058
54	0xFFF03004,0x40000054,bdnzf,lt,0xFFF03058
55	0xFFF03000,0x4106FFF4,bdnzt,4*cr1+eq,0xFFF02FF4
56	0xFFF03000,0x4001558F,bdnzfla,gt,0x0000558C
57	# indexed load/store instructions, primary opcode 0x1F
58	0xFFF00100,0x7D49F02E,lwzx,r10,r9,r30
59	0xFFF00100,0x7FAB806E,lwzux,r29,r11,r16
60	0xFFF00100,0x7C0820AE,lbzx,r0,r8,r4
61	0xFFF00100,0x7F47E8EE,lbzux,r26,r7,r29
62	0xFFF00100,0x7C01612E,stwx,r0,r1,r12
63	0xFFF00100,0x7FC3996E,stwux,r30,r3,r19
64	0xFFF00100,0x7D2C09AE,stbx,r9,r12,r1
65	0xFFF00100,0x7C8531EE,stbux,r4,r5,r6
66	0xFFF00100,0x7C94DA2E,lhzx,r4,r20,r27
67	0xFFF00100,0x7C833A6E,lhzux,r4,r3,r7
68	0xFFF00100,0x7D8F62AE,lhax,r12,r15,r12
69	0xFFF00100,0x7C98DAEE,lhaux,r4,r24,r27
70	0xFFF00100,0x7C0C0B2E,sthx,r0,r12,r1
71	0xFFF00100,0x7C032B6E,sthux,r0,r3,r5
72	0xFFF00100,0x7C43242E,lfsx,fp2,r3,r4
73	0xFFF00100,0x7C43246E,lfsux,fp2,r3,r4
74	0xFFF00100,0x7D491CAE,lfdx,fp10,r9,r3
75	0xFFF00100,0x7C4324EE,lfdux,fp2,r3,r4
76	0xFFF00100,0x7C43252E,stfsx,fp2,r3,r4
77	0xFFF00100,0x7C43256E,stfsux,fp2,r3,r4
78	0xFFF00100,0x7C4325AE,stfdx,fp2,r3,r4
79	0xFFF00100,0x7C4325EE,stfdux,fp2,r3,r4
80	# arithmetic instructions with immediate operand
81	0xFFF00100,0x1F00A81A,mulli,r24,r0,-0x57E6
82	0xFFF00100,0x1D8A4CCC,mulli,r12,r10,0x4CCC
83	0xFFF00100,0x207CFEE0,subfic,r3,r28,-0x120
84	0xFFF00100,0x20894E75,subfic,r4,r9,0x4E75
85	0xFFF00100,0x38BE0000,addi,r5,r30,0x0
86	0xFFF00100,0x3A2EFFF0,addi,r17,r14,-0x10
87	0xFFF00100,0x307F005E,addic,r3,r31,0x5E
88	0xFFF00100,0x30C4FFFF,addic,r6,r4,-0x1
89	0xFFF00100,0x34803012,addic.,r4,r0,0x3012
90	0xFFF00100,0x3E1F4A47,addis,r16,r31,0x4A47
91	0xFFF00100,0x3F3CFFF6,addis,r25,r28,-0xA
92	# subtracts and friends, primary opcode 0x1F
93	0xFFF00100,0x7C03E810,subfc,r0,r3,r29
94	0xFFF00100,0x7CE03011,subfc.,r7,r0,r6
95	0xFFF00100,0x7CC47C10,subfco,r6,r4,r15
96	0xFFF00100,0x7CC46C11,subfco.,r6,r4,r13
97	0xFFF00100,0x7D800850,subf,r12,r0,r1
98	0xFFF00100,0x7C966851,subf.,r4,r22,r13
99	0xFFF00100,0x7C7B8C50,subfo,r3,r27,r17
100	0xFFF00100,0x7D283C51,subfo.,r9,r8,r7
101	0xFFF00100,0x7CE400D0,neg,r7,r4
102	0xFFF00100,0x7CC900D1,neg.,r6,r9
103	0xFFF00100,0x7C6B04D0,nego,r3,r11
104	0xFFF00100,0x7FC004D1,nego.,r30,r0
105	0xFFF00100,0x7D266110,subfe,r9,r6,r12
106	0xFFF00100,0x7C693111,subfe.,r3,r9,r6
107	0xFFF00100,0x7C642D10,subfeo,r3,r4,r5
108	0xFFF00100,0x7C843511,subfeo.,r4,r4,r6
109	0xFFF00100,0x7D6B0190,subfze,r11,r11
110	0xFFF00100,0x7C430191,subfze.,r2,r3
111	0xFFF00100,0x7C640590,subfzeo,r3,r4
112	0xFFF00100,0x7C850591,subfzeo.,r4,r5
113	0xFFF00100,0x7C4301D0,subfme,r2,r3
114	0xFFF00100,0x7C4301D1,subfme.,r2,r3
115	0xFFF00100,0x7D2A1A10,doz,r9,r10,r3
116	0xFFF00100,0x7C642A11,doz.,r3,r4,r5
117	0xFFF00100,0x7C851E10,dozo,r4,r5,r3
118	0xFFF00100,0x7CA41E11,dozo.,r5,r4,r3
119	0xFFF00100,0x7C1E02D0,abs,r0,r30
120	0xFFF00100,0x7C3E02D1,abs.,r1,r30
121	0xFFF00100,0x7FC306D0,abso,r30,r3
122	0xFFF00100,0x7FC706D1,abso.,r30,r7
123	0xFFF00100,0x7CE703D0,nabs,r7,r7
124	0xFFF00100,0x7D0703D1,nabs.,r8,r7
125	0xFFF00100,0x7D0907D0,nabso,r8,r9
126	0xFFF00100,0x7D0A07D1,nabso.,r8,r10
127	# additions, primary opcode 0x1F
128	0xFFF00100,0x7C830014,addc,r4,r3,r0
129	0xFFF00100,0x7FB8F015,addc.,r29,r24,r30
130	0xFFF00100,0x7CDB0414,addco,r6,r27,r0
131	0xFFF00100,0x7C880415,addco.,r4,r8,r0
132	0xFFF00100,0x7D6BC914,adde,r11,r11,r25
133	0xFFF00100,0x7D296115,adde.,r9,r9,r12
134	0xFFF00100,0x7C842514,addeo,r4,r4,r4
135	0xFFF00100,0x7C843515,addeo.,r4,r4,r6
136	0xFFF00100,0x7CE80194,addze,r7,r8
137	0xFFF00100,0x7C800195,addze.,r4,r0
138	# FIXME addzeo
139	# FIXME addzeo.
140	# FIXME addme
141	# FIXME addme.
142	# FIXME addmeo
143	# FIXME addmeo.
144	0xFFF00100,0x7F03EA14,add,r24,r3,r29
145	0xFFF00100,0x7ED6E215,add.,r22,r22,r28
146	0xFFF00100,0x7D040614,addo,r8,r4,r0
147	0xFFF00100,0x7DE40615,addo.,r15,r4,r0
148	# integer multiplications & divisions, primary opcode 0x1F
149	0xFFF00100,0x7C8C5016,mulhwu,r4,r12,r10
150	0xFFF00100,0x7CA72017,mulhwu.,r5,r7,r4
151	0xFFF00100,0x7CA72096,mulhw,r5,r7,r4
152	0xFFF00100,0x7CA72097,mulhw.,r5,r7,r4
153	0xFFF00100,0x7C9000D6,mul,r4,r16,r0
154	0xFFF00100,0x7CA428D7,mul.,r5,r4,r5
155	# FIXME mulo
156	# FIXME mulo.
157	0xFFF00100,0x7D0039D6,mullw,r8,r0,r7
158	0xFFF00100,0x7C1DF1D7,mullw.,r0,r29,r30
159	0xFFF00100,0x7CE725D6,mullwo,r7,r7,r4
160	0xFFF00100,0x7CE725D7,mullwo.,r7,r7,r4
161	0xFFF00100,0x7FEB2296,div,r31,r11,r4
162	0xFFF00100,0x7C064297,div.,r0,r6,r8
163	# FIXME divo
164	# FIXME divo.
165	0xFFF00100,0x7CA03AD6,divs,r5,r0,r7
166	0xFFF00100,0x7C642AD7,divs.,r3,r4,r5
167	# FIXME divso
168	# FIXME divso.
169	0xFFF00100,0x7F7C1B96,divwu,r27,r28,r3
170	0xFFF00100,0x7C7B1B97,divwu.,r3,r27,r3
171	0xFFF00100,0x7CE62796,divwuo,r7,r6,r4
172	0xFFF00100,0x7CE62797,divwuo.,r7,r6,r4
173	0xFFF00100,0x7C042BD6,divw,r0,r4,r5
174	0xFFF00100,0x7C042BD7,divw.,r0,r4,r5
175	0xFFF00100,0x7CA627D6,divwo,r5,r6,r4
176	0xFFF00100,0x7CA627D7,divwo.,r5,r6,r4
177	# move to condition register, primary opcode 0x1F
178	0xFFF00100,0x7D818120,mtcrf,0x18,r12
179	0xFFF00100,0x7D838120,mtcrf,0x38,r12
180	0xFFF00100,0x7D080120,mtcrf,0x80,r8
181	0xFFF00100,0x7E007120,mtcrf,0x07,r16
182	# logical instructions, primary opcode 0x1F
183	0xFFF00100,0x7FC32838,and,r3,r30,r5
184	0xFFF00100,0x7C672039,and.,r7,r3,r4
185	0xFFF00100,0x7D281878,andc,r8,r9,r3
186	0xFFF00100,0x7DCE0079,andc.,r14,r14,r0
187	0xFFF00100,0x7C8328F8,nor,r3,r4,r5
188	0xFFF00100,0x7D4948F9,nor.,r9,r10,r9
189	0xFFF00100,0x7ED53A38,eqv,r21,r22,r7
190	0xFFF00100,0x7C622239,eqv.,r2,r3,r4
191	0xFFF00100,0x7D645278,xor,r4,r11,r10
192	0xFFF00100,0x7C600279,xor.,r0,r3,r0
193	0xFFF00100,0x7C841B38,orc,r4,r4,r3
194	0xFFF00100,0x7C841B39,orc.,r4,r4,r3
195	0xFFF00100,0x7DE42378,or,r4,r15,r4
196	0xFFF00100,0x7C632379,or.,r3,r3,r4
197	0xFFF00100,0x7C6023B8,nand,r0,r3,r4
198	0xFFF00100,0x7F8B63B9,nand.,r11,r28,r12
199	# trap instructions
200	0xFFF00100,0x7F800008,tw,28,r0,r0
201	# integer load and stores
202	0xFFF00100,0x80BF0808,lwz,r5,0x808(r31)
203	0xFFF00100,0x80A2FFB8,lwz,r5,-0x48(r2)
204	0xFFF00100,0x80002F3C,lwz,r0,0x2F3C
205	0xFFF00100,0x8506003C,lwzu,r8,0x3C(r6)
206	0xFFF00100,0x8403FFF8,lwzu,r0,-0x8(r3)
207	0xFFF00100,0x88FD00FA,lbz,r7,0xFA(r29)
208	0xFFF00100,0x889EFFF4,lbz,r4,-0xC(r30)
209	0xFFF00100,0x8D480001,lbzu,r10,0x1(r8)
210	0xFFF00100,0x8FC3FFFF,lbzu,r30,-0x1(r3)
211	0xFFF00100,0x90600AFC,stw,r3,0xAFC
212	0xFFF00100,0x9000F620,stw,r0,-0x9E0
213	0xFFF00100,0x9146696E,stw,r10,0x696E(r6)
214	0xFFF00100,0x9317FFF0,stw,r24,-0x10(r23)
215	0xFFF00100,0x94050020,stwu,r0,0x20(r5)
216	0xFFF00100,0x9421FFA0,stwu,r1,-0x60(r1)
217	0xFFF00100,0x981F00FA,stb,r0,0xFA(r31)
218	0xFFF00100,0x98829882,stb,r4,-0x677E(r2)
219	0xFFF00100,0x9EFC000A,stbu,r23,0xA(r28)
220	0xFFF00100,0x9FAEFFFC,stbu,r29,-0x4(r14)
221	0xFFF00100,0xA22E6010,lhz,r17,0x6010(r14)
222	0xFFF00100,0xA0C6FFF8,lhz,r6,-0x8(r6)
223	0xFFF00100,0xA43C6010,lhzu,r1,0x6010(r28)
224	0xFFF00100,0xA7BFFFFE,lhzu,r29,-0x2(r31)
225	0xFFF00100,0xA820265F,lha,r1,0x265F
226	0xFFF00100,0xA8B5201F,lha,r5,0x201F(r21)
227	0xFFF00100,0xAAFEFE82,lha,r23,-0x17E(r30)
228	0xFFF00100,0xAC08003C,lhau,r0,0x3C(r8)
229	0xFFF00100,0xAC90FFFE,lhau,r4,-0x2(r16)
230	0xFFF00100,0xB3E40012,sth,r31,0x12(r4)
231	0xFFF00100,0xB02EFFFB,sth,r1,-0x5(r14)
232	0xFFF00100,0xB4B81EF4,sthu,r5,0x1EF4(r24)
233	0xFFF00100,0xB774FFFE,sthu,r27,-0x2(r20)
234	0xFFF00100,0xBB61006C,lmw,r27,0x6C(r1)
235	0xFFF00100,0xBB41FFE8,lmw,r26,-0x18(r1)
236	0xFFF00100,0xBC410008,stmw,r2,0x8(r1)
237	0xFFF00100,0xBFC1FFF8,stmw,r30,-0x8(r1)
238	# various simplified (extended) mnemonics
239	0xFFF00100,0x60000000,nop
240	0xFFF00100,0x7C7C1B78,mr,r28,r3
241	0xFFF00100,0x7C7C1B78,mr,r28,r3
242	0xFFF00100,0x7DAA6B79,mr.,r10,r13
243	0xFFF00100,0x38000000,li,r0,0x0
244	0xFFF00100,0x3860FFCE,li,r3,-0x32
245	# invalid opcodes/instruction forms
246	0xFFF00100,0x7D49F02F,dc.l,0x7D49F02F
247	0xFFF00100,0x7F800009,dc.l,0x7F800009
248	0xFFF00100,0x7C6B0CD0,dc.l,0x7C6B0CD0
249	0xFFF00100,0x7C642D90,dc.l,0x7C642D90
250	# POWER/PPC601 specific instructions
251	#0xFFF00100,0x7E3EE43A,maskir,r30,r17,r28