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mpc106: Document flash ROM related registers.

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joevt
2024-02-16 23:28:33 -08:00
committed by dingusdev
parent e43bb02d9a
commit 392f6cdcd3
1 changed files with 93 additions and 1 deletions
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devices/memctrl/mpc106.h
+93 -1
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@@ -65,9 +65,101 @@ enum GrackleReg : uint32_t {
MCCR4 = 0xFC // memory control configuration 4
};
/* PICR1 bit definitions. */
enum {
CF_L2_MP_SHIFT = 0,
CF_L2_MP_MASK = 3 << CF_L2_MP_SHIFT,
SPECULATIVE_PCI_READS = 1 << 2,
CF_APARK = 1 << 3,
CF_LOOP_SNOOP = 1 << 4,
LE_MODE = 1 << 5,
ST_GATH_EN = 1 << 6,
NO_PORT_REGS = 1 << 7,
CF_EXTERNAL_L2 = 1 << 8,
CF_DPARK = 1 << 9,
TEA_EN = 1 << 10, // enabled during ROM flashing
MCP_EN = 1 << 11,
FLASH_WR_EN = 1 << 12, // enabled during ROM flashing, disabled after ROM flashing
CF_LBA_EN = 1 << 13,
CF_MP_ID_SHIFT = 14,
CF_MP_ID_MASK = 3 << CF_MP_ID_SHIFT,
ADDRESS_MAP = 1 << 16,
PROC_TYPE_SHIFT = 17,
PROC_TYPE_MASK = 3 << PROC_TYPE_SHIFT,
XIO_MODE = 1 << 19,
RCS0 = 1 << 20,
CF_CACHE_1G = 1 << 21,
CF_BREAD_WS_SHIFT = 22,
CF_BREAD_WS_MASK = 3 << CF_BREAD_WS_SHIFT,
CF_CBA_MASK_SHIFT = 24,
CF_CBA_MASK_MASK = 0xff << CF_CBA_MASK_SHIFT,
};
/* PICR2 bit definitions. */
enum {
CF_WDATA = 0,
CF_DOE = 1,
CF_APHASE_WS_SHIFT = 2,
CF_APHASE_WS_MASK = 3 << CF_APHASE_WS_SHIFT,
CF_L2_SIZE_SHIFT = 4,
CF_L2_SIZE_MASK = 3 << CF_L2_SIZE_SHIFT,
CF_TOE_WIDTH = 6,
CF_FAST_CASTOUT = 7,
CF_TWO_BANKS = 8,
CF_L2_HIT_DELAY_SHIFT = 9,
CF_L2_HIT_DELAY_MASK = 3 << CF_L2_HIT_DELAY_SHIFT,
CF_RWITM_FILL = 11,
CF_INV_MODE = 12,
CF_HOLD = 13,
CF_ADDR_ONLY_DISABLE = 14,
// RESERVED = 15,
CF_HIT_HIGH = 16,
CF_MOD_HIGH = 17,
CF_SNOOP_WS_SHIFT = 18,
CF_SNOOP_WS_MASK = 3 << CF_SNOOP_WS_SHIFT,
CF_WMODE_SHIFT = 20,
CF_WMODE_MASK = 3 << CF_WMODE_SHIFT,
CF_DATA_RAM_TYPE_SHIFT = 22,
CF_DATA_RAM_TYPE_MASK = 3 << CF_DATA_RAM_TYPE_SHIFT,
CF_FAST_L2_MODE = 24,
FLASH_WR_LOCKOUT = 25, // Programmer Mode changes this to 0 which allows flash writing.
CF_FF0_LOCAL = 26,
NO_SNOOP_EN = 27,
CF_FLUSH_L2 = 28,
NO_SERIAL_CFG = 29,
L2_EN = 30,
L2_UPDATE_EN = 31,
};
/* MCCR1 bit definitions. */
enum {
MEMGO = 1 << 19,
BANK_0_ROW_SHIFT = 0,
BANK_0_ROW_MASK = 3 << BANK_0_ROW_SHIFT,
BANK_1_ROW_SHIFT = 2,
BANK_1_ROW_MASK = 3 << BANK_1_ROW_SHIFT,
BANK_2_ROW_SHIFT = 4,
BANK_2_ROW_MASK = 3 << BANK_2_ROW_SHIFT,
BANK_3_ROW_SHIFT = 6,
BANK_3_ROW_MASK = 3 << BANK_3_ROW_SHIFT,
BANK_4_ROW_SHIFT = 8,
BANK_4_ROW_MASK = 3 << BANK_4_ROW_SHIFT,
BANK_5_ROW_SHIFT = 10,
BANK_5_ROW_MASK = 3 << BANK_5_ROW_SHIFT,
BANK_6_ROW_SHIFT = 12,
BANK_6_ROW_MASK = 3 << BANK_6_ROW_SHIFT,
BANK_7_ROW_SHIFT = 14,
BANK_7_ROW_MASK = 3 << BANK_7_ROW_SHIFT,
PCKEN = 1 << 16,
RAM_TYPE = 1 << 17,
SREN = 1 << 18,
MEMGO = 1 << 19,
BURST = 1 << 20,
_8N64 = 1 << 21, // 1 = the MPC106 is configured for an 8-bit data path for ROM bank 0 rather than 64-bit
_501_MODE = 1 << 22,
ROMFAL_SHIFT = 23,
ROMFAL_MASK = 31 << ROMFAL_SHIFT,
ROMNAL_SHIFT = 28,
ROMNAL_MASK = 15 << ROMNAL_SHIFT,
};
class MPC106 : public MemCtrlBase, public PCIDevice, public PCIHost {