Fix read/write argument names

base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.

devices/common/machineid.h

@@ -55,12 +55,12 @@ public:
     };
     ~NubusMacID() = default;
 
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size) {
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size) {
         return (offset < 4 ? this->id[offset] : 0);
     };
 
     /* not writable */
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {};
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {};
 
 private:
     uint8_t id[4];
@@ -80,12 +80,12 @@ public:
     };
     ~GossamerID() = default;
 
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size) {
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size) {
         return ((!offset && size == 2) ? this->id : 0);
     };
 
     /* not writable */
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {};
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {};
 
 private:
     uint16_t id;

devices/common/mmiodevice.h

@@ -31,8 +31,8 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 class MMIODevice : public HWComponent {
 public:
     MMIODevice()                                                                      = default;
-    virtual uint32_t read(uint32_t reg_start, uint32_t offset, int size)              = 0;
-    virtual void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) = 0;
+    virtual uint32_t read(uint32_t rgn_start, uint32_t offset, int size)              = 0;
+    virtual void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) = 0;
     virtual ~MMIODevice()                                                             = default;
 };
 

devices/common/pci/bandit.cpp

@@ -111,7 +111,7 @@ void Bandit::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size)
     }
 }
 
-uint32_t Bandit::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t Bandit::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     int      bus_num, dev_num, fun_num;
     uint8_t  reg_offs;
@@ -178,7 +178,7 @@ uint32_t Bandit::read(uint32_t reg_start, uint32_t offset, int size)
     return result;
 }
 
-void Bandit::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
+void Bandit::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
 {
     int      bus_num, dev_num, fun_num;
     uint8_t  reg_offs;
@@ -284,7 +284,7 @@ Chaos::Chaos(std::string name) : PCIHost()
     this->name = name;
 }
 
-uint32_t Chaos::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t Chaos::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     int      bus_num, dev_num, fun_num;
     uint8_t  reg_offs;
@@ -340,7 +340,7 @@ uint32_t Chaos::read(uint32_t reg_start, uint32_t offset, int size)
     return result;
 }
 
-void Chaos::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
+void Chaos::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
 {
     int      bus_num, dev_num, fun_num;
     uint8_t  reg_offs;

devices/common/pci/bandit.h

@@ -63,8 +63,8 @@ public:
     void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size);
 
     // MMIODevice methods
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
 protected:
     void verbose_address_space();
@@ -90,8 +90,8 @@ public:
     };
 
     // MMIODevice methods
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
 private:
     std::string name;

devices/ioctrl/amic.cpp

@@ -101,7 +101,7 @@ int AMIC::device_postinit()
     return 0;
 }
 
-uint32_t AMIC::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t AMIC::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     uint32_t  phase_val;
 
@@ -180,7 +180,7 @@ uint32_t AMIC::read(uint32_t reg_start, uint32_t offset, int size)
     return 0;
 }
 
-void AMIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
+void AMIC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
 {
     uint32_t mask;
 

devices/ioctrl/amic.h

@@ -192,8 +192,8 @@ public:
     int device_postinit();
 
     /* MMIODevice methods */
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     // InterruptCtrl methods
     uint32_t register_dev_int(IntSrc src_id);

devices/ioctrl/grandcentral.cpp

@@ -94,7 +94,7 @@ void GrandCentral::notify_bar_change(int bar_num)
     }
 }
 
-uint32_t GrandCentral::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t GrandCentral::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     if (offset & 0x10000) { // Device register space
         unsigned subdev_num = (offset >> 12) & 0xF;
@@ -160,7 +160,7 @@ uint32_t GrandCentral::read(uint32_t reg_start, uint32_t offset, int size)
     return 0;
 }
 
-void GrandCentral::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
+void GrandCentral::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
 {
     if (offset & 0x10000) { // Device register space
         unsigned subdev_num = (offset >> 12) & 0xF;

devices/ioctrl/heathrow.cpp

@@ -128,7 +128,7 @@ void HeathrowIC::dma_write(uint32_t offset, uint32_t value, int size) {
 }
 
 
-uint32_t HeathrowIC::read(uint32_t reg_start, uint32_t offset, int size) {
+uint32_t HeathrowIC::read(uint32_t rgn_start, uint32_t offset, int size) {
     uint32_t res = 0;
 
     LOG_F(9, "%s: reading from offset %x", this->name.c_str(), offset);
@@ -172,7 +172,7 @@ uint32_t HeathrowIC::read(uint32_t reg_start, uint32_t offset, int size) {
     return res;
 }
 
-void HeathrowIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {
+void HeathrowIC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
     LOG_F(9, "%s: writing to offset %x", this->name.c_str(), offset);
 
     unsigned sub_addr = (offset >> 12) & 0x7F;

devices/ioctrl/macio.h

@@ -100,8 +100,8 @@ public:
     }
 
     // MMIO device methods
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     // InterruptCtrl methods
     uint32_t register_dev_int(IntSrc src_id);
@@ -182,8 +182,8 @@ public:
     }
 
     // MMIO device methods
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     // InterruptCtrl methods
     uint32_t register_dev_int(IntSrc src_id);

devices/memctrl/hammerhead.cpp

@@ -40,7 +40,7 @@ HammerheadCtrl::HammerheadCtrl() : MemCtrlBase()
     add_mmio_region(0xF8000000, 0x500, this);
 }
 
-uint32_t HammerheadCtrl::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t HammerheadCtrl::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     uint32_t result;
 

devices/memctrl/hammerhead.h

@@ -97,7 +97,7 @@ public:
     }
 
     // MMIODevice methods
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
     void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     void insert_ram_dimm(int slot_num, uint32_t capacity);

devices/memctrl/hmc.cpp

@@ -41,7 +41,7 @@ HMC::HMC() : MemCtrlBase()
     this->bit_pos = 0;
 }
 
-uint32_t HMC::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t HMC::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     if (!offset)
         return !!(this->ctrl_reg & (1ULL << this->bit_pos++));
@@ -49,7 +49,7 @@ uint32_t HMC::read(uint32_t reg_start, uint32_t offset, int size)
         return 0; /* FIXME: what should be returned for invalid offsets? */
 }
 
-void HMC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
+void HMC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
 {
     uint64_t bit;
 

devices/memctrl/hmc.h

@@ -51,8 +51,8 @@ public:
     }
 
     /* MMIODevice methods */
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     uint64_t get_control_reg(void) {
         return this->ctrl_reg;

devices/memctrl/mpc106.cpp

@@ -74,10 +74,10 @@ int MPC106::device_postinit()
     return 0;
 }
 
-uint32_t MPC106::read(uint32_t reg_start, uint32_t offset, int size) {
+uint32_t MPC106::read(uint32_t rgn_start, uint32_t offset, int size) {
     uint32_t result;
 
-    if (reg_start == 0xFE000000) {
+    if (rgn_start == 0xFE000000) {
         // broadcast I/O request to devices that support I/O space
         // until a device returns true that means "request accepted"
         for (auto& dev : this->io_space_devs) {
@@ -98,8 +98,8 @@ uint32_t MPC106::read(uint32_t reg_start, uint32_t offset, int size) {
     return 0;
 }
 
-void MPC106::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size) {
-    if (reg_start == 0xFE000000) {
+void MPC106::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
+    if (rgn_start == 0xFE000000) {
         // broadcast I/O request to devices that support I/O space
         // until a device returns true that means "request accepted"
         for (auto& dev : this->io_space_devs) {

devices/memctrl/mpc106.h

@@ -52,8 +52,8 @@ public:
         return std::unique_ptr<MPC106>(new MPC106());
     }
 
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     int device_postinit();
 

devices/memctrl/platinum.cpp

@@ -53,7 +53,7 @@ PlatinumCtrl::PlatinumCtrl() : MemCtrlBase()
     this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
 }
 
-uint32_t PlatinumCtrl::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     if (size != 4) {
         LOG_F(WARNING, "Platinum: unsupported register access size %d!", size);

devices/memctrl/platinum.h

@@ -155,7 +155,7 @@ public:
     }
 
     /* MMIODevice methods */
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
     void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     void insert_ram_dimm(int slot_num, uint32_t capacity);

devices/video/atirage.cpp

@@ -378,11 +378,11 @@ bool ATIRage::pci_io_write(uint32_t offset, uint32_t value, uint32_t size) {
 }
 
 
-uint32_t ATIRage::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t ATIRage::read(uint32_t rgn_start, uint32_t offset, int size)
 {
-    LOG_F(8, "Reading ATI Rage PCI memory: region=%X, offset=%X, size %d", reg_start, offset, size);
+    LOG_F(8, "Reading ATI Rage PCI memory: region=%X, offset=%X, size %d", rgn_start, offset, size);
 
-    if (reg_start < this->aperture_base || offset > APERTURE_SIZE) {
+    if (rgn_start < this->aperture_base || offset > APERTURE_SIZE) {
         LOG_F(WARNING, "ATI Rage: attempt to read outside the aperture!");
         return 0;
     }
@@ -410,11 +410,11 @@ uint32_t ATIRage::read(uint32_t reg_start, uint32_t offset, int size)
     return 0;
 }
 
-void ATIRage::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
+void ATIRage::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
 {
-    LOG_F(8, "Writing reg=%X, offset=%X, value=%X, size %d", reg_start, offset, value, size);
+    LOG_F(8, "Writing reg=%X, offset=%X, value=%X, size %d", rgn_start, offset, value, size);
 
-    if (reg_start < this->aperture_base || offset > APERTURE_SIZE) {
+    if (rgn_start < this->aperture_base || offset > APERTURE_SIZE) {
         LOG_F(WARNING, "ATI Rage: attempt to write outside the aperture!");
         return;
     }

devices/video/atirage.h

@@ -56,8 +56,8 @@ public:
     }
 
     /* MMIODevice methods */
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
     /* PCI device methods */
     bool supports_io_space(void) {

devices/video/control.cpp

@@ -103,11 +103,11 @@ void ControlVideo::notify_bar_change(int bar_num)
     }
 }
 
-uint32_t ControlVideo::read(uint32_t reg_start, uint32_t offset, int size)
+uint32_t ControlVideo::read(uint32_t rgn_start, uint32_t offset, int size)
 {
     uint32_t result = 0;
 
-    if (reg_start == this->vram_base) {
+    if (rgn_start == this->vram_base) {
         if (offset >= 0x800000) {
             return read_mem_rev(&this->vram_ptr[offset - 0x800000], size);
         } else {
@@ -124,15 +124,15 @@ uint32_t ControlVideo::read(uint32_t reg_start, uint32_t offset, int size)
         result = this->cur_mon_id << 6;
         break;
     default:
-        LOG_F(INFO, "read from 0x%08X:0x%08X", reg_start, offset);
+        LOG_F(INFO, "read from 0x%08X:0x%08X", rgn_start, offset);
     }
 
     return BYTESWAP_32(result);
 }
 
-void ControlVideo::write(uint32_t reg_start, uint32_t offset, uint32_t value, int size)
+void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
 {
-    if (reg_start == this->vram_base) {
+    if (rgn_start == this->vram_base) {
         if (offset >= 0x800000) {
             write_mem_rev(&this->vram_ptr[offset - 0x800000], value, size);
         } else {
@@ -209,7 +209,7 @@ void ControlVideo::write(uint32_t reg_start, uint32_t offset, uint32_t value, in
         this->int_enable = value;
         break;
     default:
-        LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, reg_start, offset);
+        LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, rgn_start, offset);
     }
 }
 

devices/video/control.h

@@ -97,8 +97,8 @@ public:
     }
 
     // MMIODevice methods
-    uint32_t read(uint32_t reg_start, uint32_t offset, int size);
-    void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
+    uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
+    void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
 
 protected:
     void notify_bar_change(int bar_num);