mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-11-12 12:07:04 +00:00
bigmac: support more registers.
This commit is contained in:
Maxim Poliakovski
parent
9db3076a48
commit
5f48a3ab5b
@ -30,6 +30,13 @@ BigMac::BigMac(uint8_t id) {
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supports_types(HWCompType::MMIO_DEV | HWCompType::ETHER_MAC);
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this->chip_id = id;
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this->chip_reset();
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}
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void BigMac::chip_reset() {
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this->event_mask = 0xFFFFU; // disable HW events causing on-chip interrupts
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this->stat = 0;
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this->phy_reset();
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this->mii_reset();
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this->srom_reset();
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@ -37,12 +44,38 @@ BigMac::BigMac(uint8_t id) {
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uint16_t BigMac::read(uint16_t reg_offset) {
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switch (reg_offset) {
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case BigMacReg::XIFC:
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return this->tx_if_ctrl;
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case BigMacReg::CHIP_ID:
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return this->chip_id;
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case BigMacReg::MIF_CSR:
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return (this->mif_csr_old & ~Mif_Data_In) | (this->mii_in_bit << 3);
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case BigMacReg::GLOB_STAT: {
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uint16_t old_stat = this->stat;
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this->stat = 0; // clear-on-read
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return old_stat;
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}
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case BigMacReg::EVENT_MASK:
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return this->event_mask;
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case BigMacReg::SROM_CSR:
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return (this->srom_csr_old & ~Srom_Data_In) | (this->srom_in_bit << 2);
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case BigMacReg::TX_SW_RST:
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return this->tx_reset;
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case BigMacReg::TX_CONFIG:
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return this->tx_config;
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case BigMacReg::PEAK_ATT: {
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uint8_t old_val = this->peak_attempts;
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this->peak_attempts = 0; // clear-on-read
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return old_val;
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}
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case BigMacReg::NC_CNT:
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return this->norm_coll_cnt;
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case BigMacReg::EX_CNT:
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return this->excs_coll_cnt;
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case BigMacReg::LT_CNT:
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return this->late_coll_cnt;
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case BigMacReg::RX_CONFIG:
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return this->rx_config;
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default:
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LOG_F(WARNING, "%s: unimplemented register at 0x%X", this->name.c_str(),
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reg_offset);
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@ -53,6 +86,20 @@ uint16_t BigMac::read(uint16_t reg_offset) {
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void BigMac::write(uint16_t reg_offset, uint16_t value) {
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switch (reg_offset) {
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case BigMacReg::XIFC:
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this->tx_if_ctrl = value;
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break;
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case BigMacReg::TX_FIFO_CSR:
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this->tx_fifo_enable = !!(value & 1);
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this->tx_fifo_size = (((value >> 1) & 0xFF) + 1) << 7;
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break;
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case BigMacReg::TX_FIFO_TH:
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this->tx_fifo_tresh = value;
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break;
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case BigMacReg::RX_FIFO_CSR:
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this->rx_fifo_enable = !!(value & 1);
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this->rx_fifo_size = (((value >> 1) & 0xFF) + 1) << 7;
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break;
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case BigMacReg::MIF_CSR:
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if (value & Mif_Data_Out_En) {
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// send bits one by one on each low-to-high transition of Mif_Clock
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@ -64,6 +111,9 @@ void BigMac::write(uint16_t reg_offset, uint16_t value) {
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}
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this->mif_csr_old = value;
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break;
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case BigMacReg::EVENT_MASK:
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this->event_mask = value;
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break;
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case BigMacReg::SROM_CSR:
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if (value & Srom_Chip_Select) {
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// exchange data on each low-to-high transition of Srom_Clock
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@ -80,11 +130,58 @@ void BigMac::write(uint16_t reg_offset, uint16_t value) {
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this->tx_reset = 0; // acknowledge SW reset
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}
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break;
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case BigMacReg::TX_CONFIG:
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this->tx_config = value;
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break;
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case BigMacReg::NC_CNT:
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this->norm_coll_cnt = value;
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break;
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case BigMacReg::NT_CNT:
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this->net_coll_cnt = value;
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break;
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case BigMacReg::EX_CNT:
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this->excs_coll_cnt = value;
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break;
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case BigMacReg::LT_CNT:
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this->late_coll_cnt = value;
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break;
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case BigMacReg::RNG_SEED:
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this->rng_seed = value;
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break;
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case BigMacReg::RX_SW_RST:
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if (!value) {
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LOG_F(INFO, "%s: receiver soft reset asserted", this->name.c_str());
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}
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break;
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case BigMacReg::RX_CONFIG:
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this->rx_config = value;
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break;
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case BigMacReg::MAC_ADDR_0:
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case BigMacReg::MAC_ADDR_1:
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case BigMacReg::MAC_ADDR_2:
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this->mac_addr_flt[8 - ((reg_offset >> 4) & 0xF)] = value;
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break;
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case BigMacReg::RX_FRM_CNT:
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this->rcv_frame_cnt = value;
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break;
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case BigMacReg::RX_LE_CNT:
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this->len_err_cnt = value;
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break;
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case BigMacReg::RX_AE_CNT:
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this->align_err_cnt = value;
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break;
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case BigMacReg::RX_FE_CNT:
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this->fcs_err_cnt = value;
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break;
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case BigMacReg::RX_CVE_CNT:
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this->cv_err_cnt = value;
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break;
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case BigMacReg::HASH_TAB_0:
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case BigMacReg::HASH_TAB_1:
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case BigMacReg::HASH_TAB_2:
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case BigMacReg::HASH_TAB_3:
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this->hash_table[(reg_offset >> 4) & 3] = value;
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break;
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default:
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LOG_F(WARNING, "%s: unimplemented register at 0x%X is written with 0x%X",
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this->name.c_str(), reg_offset, value);
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@ -37,11 +37,37 @@ enum EthernetCellId : uint8_t {
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/* BigMac HW registers. */
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enum BigMacReg : uint16_t {
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XIFC = 0x000, // transceiver interface control
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TX_FIFO_CSR = 0x100,
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TX_FIFO_TH = 0x110,
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RX_FIFO_CSR = 0x120,
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CHIP_ID = 0x170,
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MIF_CSR = 0x180,
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GLOB_STAT = 0x200, // Apple: kSTAT, Sun: Global Status Register
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EVENT_MASK = 0x210, // ambiguously called INT_DISABLE in the Apple source
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SROM_CSR = 0x190,
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TX_SW_RST = 0x420,
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TX_CONFIG = 0x430,
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PEAK_ATT = 0x4E0, // Apple: kPAREG, Sun: PeakAttempts Register
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NC_CNT = 0x500, // Normal Collision Counter
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NT_CNT = 0x510, // Apple: Network Collision Counter
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EX_CNT = 0x520, // Excessive Collision Counter
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LT_CNT = 0x530, // Late Collision Counter
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RNG_SEED = 0x540,
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RX_SW_RST = 0x620,
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RX_CONFIG = 0x630,
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MAC_ADDR_2 = 0x660,
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MAC_ADDR_1 = 0x670,
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MAC_ADDR_0 = 0x680,
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RX_FRM_CNT = 0x690, // Receive Frame Counter
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RX_LE_CNT = 0x6A0, // Length Error Counter
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RX_AE_CNT = 0x6B0, // Alignment Error Counter
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RX_FE_CNT = 0x6C0, // FCS Error Counter
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RX_CVE_CNT = 0x6E0, // Code Violation Error Counter
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HASH_TAB_3 = 0x700,
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HASH_TAB_2 = 0x710,
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HASH_TAB_1 = 0x720,
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HASH_TAB_0 = 0x730,
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};
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/* MIF_CSR bit definitions. */
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@ -107,6 +133,9 @@ public:
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uint16_t read(uint16_t reg_offset);
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void write(uint16_t reg_offset, uint16_t value);
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protected:
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void chip_reset();
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// MII methods
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bool mii_rcv_value(uint16_t& var, uint8_t num_bits, uint8_t next_bit);
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void mii_rcv_bit();
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@ -127,7 +156,32 @@ private:
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uint8_t chip_id; // BigMac Chip ID
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// BigMac state
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uint16_t tx_reset = 0;
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uint16_t tx_reset = 0; // self-clearing one-bit register
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uint16_t tx_if_ctrl = 0;
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uint16_t rng_seed;
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uint16_t norm_coll_cnt = 0;
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uint16_t net_coll_cnt = 0;
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uint16_t excs_coll_cnt = 0;
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uint16_t late_coll_cnt = 0;
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uint16_t rcv_frame_cnt = 0;
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uint8_t len_err_cnt = 0;
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uint8_t align_err_cnt = 0;
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uint8_t fcs_err_cnt = 0;
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uint8_t cv_err_cnt = 0;
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uint8_t peak_attempts = 0;
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uint8_t tx_fifo_tresh = 0;
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bool tx_fifo_enable = false;
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bool rx_fifo_enable = false;
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uint16_t tx_fifo_size = 0;
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uint16_t rx_fifo_size = 0;
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uint16_t hash_table[4] = {};
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uint16_t mac_addr_flt[3] = {};
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uint16_t tx_config = 0;
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uint16_t rx_config = 0;
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// Interrupt state
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uint16_t event_mask = 0xFFFFU; // inverted mask: 0 - enabled, 1 - disabled
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uint16_t stat = 0;
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// MII state
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uint8_t mif_csr_old = 0;
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