Macintosh-Tools/dingusppc
1
0
Fork 0
mirror of https://github.com/dingusdev/dingusppc.git synced 2026-04-21 09:16:48 +00:00
Code Issues Projects Releases Wiki Activity

Fill out MACE stub further

Browse Source 
Last commit of 2025. This will be further expanded next year.
This commit is contained in:
dingusdev
2025-12-31 21:29:49 -07:00
parent 7429a4111e
commit 8105defb0b
2 changed files with 51 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
devices/ethernet/mace.cpp
+31 -4
View File
@@ -31,9 +31,19 @@ using namespace MaceEnet;
uint8_t MaceController::read(uint8_t reg_offset)
{
switch(reg_offset) {
switch (reg_offset) {
case MaceReg::Rcv_FIFO:
return 0; //No FIFO yet
case MaceReg::Rcv_Frame_Ctrl:
return this->rcv_fc;
case MaceReg::Xmit_Frame_Stat:
return this->xmt_fs;
case MaceReg::Xmit_Retry_Cnt:
return this->xmt_retry;
case MaceReg::Rcv_Frame_Stat:
return this->rcv_fs;
case MaceReg::FIFO_Frame_Cnt:
return this->fifo_fc;
case MaceReg::Interrupt: {
uint8_t ret_val = this->int_stat;
this->int_stat = 0;
@@ -42,12 +52,26 @@ uint8_t MaceController::read(uint8_t reg_offset)
}
case MaceReg::Interrupt_Mask:
return this->int_mask;
case MaceReg::Poll:
return this->poll_reg;
case MaceReg::BIU_Config_Ctrl:
return this->biu_ctrl;
case MaceReg::FIFO_Config:
return this->fifo_ctrl;
case MaceReg::MAC_Config_Ctrl:
return this->mac_cc;
case MaceReg::PLS_Config_Ctrl:
return this->pls_cc;
case MaceReg::PHY_Config_Ctrl:
return this->phy_cc;
case MaceReg::Chip_ID_Lo:
return this->chip_id & 0xFFU;
case MaceReg::Chip_ID_Hi:
return (this->chip_id >> 8) & 0xFFU;
case MaceReg::Int_Addr_Config:
return this->addr_cfg;
case MaceReg::Missed_Pkt_Cnt:
return this->missed_pkts;
default:
LOG_F(INFO, "%s: reading from register %d", this->name.c_str(), reg_offset);
}
@@ -64,9 +88,6 @@ void MaceController::write(uint8_t reg_offset, uint8_t value)
case MaceReg::Interrupt_Mask:
this->int_mask = value;
break;
case MaceReg::MAC_Config_Ctrl:
this->mac_cfg = value;
break;
case MaceReg::BIU_Config_Ctrl:
if (value & BIU_SWRST) {
LOG_F(INFO, "%s: soft reset asserted", this->name.c_str());
@@ -74,6 +95,12 @@ void MaceController::write(uint8_t reg_offset, uint8_t value)
}
this->biu_ctrl = value;
break;
case MaceReg::FIFO_Config:
this->fifo_ctrl = value;
break;
case MaceReg::MAC_Config_Ctrl:
this->mac_cfg = value;
break;
case MaceReg::PLS_Config_Ctrl:
if (value != 7)
LOG_F(WARNING, "%s: unsupported transceiver interface 0x%X in PLSCC",
devices/ethernet/mace.h
+20 -8
View File
@@ -99,14 +99,26 @@ public:
void write(uint8_t reg_offset, uint8_t value);
private:
uint16_t chip_id; // per-instance MACE Chip ID
uint8_t addr_cfg = 0;
uint8_t addr_ptr = 0;
uint8_t rcv_fc = 1;
uint8_t biu_ctrl = 0;
uint8_t mac_cfg = 0;
uint64_t phys_addr = 0;
uint64_t log_addr = 0;
uint16_t chip_id; // per-instance MACE Chip ID
uint8_t addr_cfg = 0;
uint8_t addr_ptr = 0;
uint8_t xmt_fs = 0;
uint8_t xmt_retry = 0;
uint8_t rcv_fc = 1;
uint8_t rcv_fs = 0;
uint8_t biu_ctrl = 0;
uint8_t fifo_ctrl = 0;
uint8_t poll_reg = 0;
uint8_t mac_cfg = 0;
uint8_t mac_cc = 0;
uint8_t pls_cc = 0;
uint8_t phy_cc = 0;
uint8_t fifo_fc = 0;
uint8_t missed_pkts = 0;
uint64_t phys_addr = 0;
uint64_t log_addr = 0;
// interrupt stuff
uint8_t int_stat = 0;