mpc106: rewrite control registers handling.
This commit is contained in:
Maxim Poliakovski
parent
ec97a671d8
commit
99e92a5679
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -173,80 +173,120 @@ void MPC106::pci_write(uint32_t offset, uint32_t value, uint32_t size) {
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}
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uint32_t MPC106::pci_cfg_read(uint32_t reg_offs, AccessDetails &details) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "read from Grackle register %08X", reg_offs);
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#endif
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if (reg_offs < 64) {
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return PCIDevice::pci_cfg_read(reg_offs, details);
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}
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uint32_t value = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[reg_offs]);
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if ((reg_offs >= 0x80 && reg_offs <= 0xA0) || reg_offs == 0xF0) {
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return value;
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switch (reg_offs) {
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case GrackleReg::CFG10:
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return 0;
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case GrackleReg::PMCR1:
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return (this->odcr << 24) | (this->pmcr2 << 16) | this->pmcr1;
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case GrackleReg::MBER:
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return this->mem_bank_en;
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case GrackleReg::PICR1:
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return this->picr1;
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case GrackleReg::PICR2:
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return this->picr2;
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case GrackleReg::MCCR1:
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return this->mccr1;
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default:
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LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER_WITH_VALUE();
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return value;
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return 0; // PCI Spec §6.1
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}
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void MPC106::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "write %08X to Grackle register %08X", value, reg_offs);
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#endif
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if (reg_offs < 64) {
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PCIDevice::pci_cfg_write(reg_offs, value, details);
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return;
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}
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// FIXME: implement write-protection for read-only registers
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uint32_t *addr = (uint32_t *)&this->my_pci_cfg_hdr[reg_offs];
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WRITE_DWORD_LE_A(addr, value);
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if ((reg_offs >= 0x80 && reg_offs <= 0xA0) || reg_offs == 0xF0) {
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if (this->my_pci_cfg_hdr[0xF2] & 8) {
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#ifdef MPC106_DEBUG
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LOG_F(9, "MPC106: MCCR1[MEMGO] was set!");
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#endif
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setup_ram();
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switch (reg_offs) {
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case GrackleReg::CFG10:
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// Open Firmware writes 0 to subordinate bus # - we don't care
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break;
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case GrackleReg::PMCR1:
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this->pmcr1 = value & 0xFFFFU;
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this->pmcr2 = (value >> 16) & 0xFF;
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this->odcr = value >> 24;
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break;
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case GrackleReg::MSAR1:
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case GrackleReg::MSAR2:
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this->mem_start[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::EMSAR1:
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case GrackleReg::EMSAR2:
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this->ext_mem_start[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::MEAR1:
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case GrackleReg::MEAR2:
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this->mem_end[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::EMEAR1:
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case GrackleReg::EMEAR2:
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this->ext_mem_end[(reg_offs >> 2) & 1] = value;
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break;
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case GrackleReg::MBER:
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this->mem_bank_en = value & 0xFFU;
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break;
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case GrackleReg::PICR1:
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this->picr1 = value;
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break;
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case GrackleReg::PICR2:
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this->picr2 = value;
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break;
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case GrackleReg::MCCR1:
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if ((value ^ this->mccr1) & MEMGO) {
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if (value & MEMGO)
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setup_ram();
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}
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return;
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this->mccr1 = value;
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break;
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case GrackleReg::MCCR2:
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this->mccr2 = value;
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break;
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case GrackleReg::MCCR3:
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this->mccr3 = value;
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break;
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case GrackleReg::MCCR4:
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this->mccr4 = value;
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break;
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default:
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LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER();
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}
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void MPC106::setup_ram() {
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uint32_t mem_start, mem_end, ext_mem_start, ext_mem_end, bank_start, bank_end;
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uint32_t ram_size = 0;
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uint8_t bank_en = this->my_pci_cfg_hdr[0xA0];
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for (int bank = 0; bank < 8; bank++) {
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if (bank_en & (1 << bank)) {
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if (this->mem_bank_en & (1 << bank)) {
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if (bank < 4) {
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x80]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x88]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x90]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x98]);
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mem_start = this->mem_start[0];
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ext_mem_start = this->ext_mem_start[0];
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mem_end = this->mem_end[0];
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ext_mem_end = this->ext_mem_end[0];
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} else {
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x84]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x8C]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x94]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x9C]);
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mem_start = this->mem_start[1];
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ext_mem_start = this->ext_mem_start[1];
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mem_end = this->mem_end[1];
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ext_mem_end = this->ext_mem_end[1];
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}
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bank_start = (((ext_mem_start >> bank * 8) & 3) << 30) |
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(((mem_start >> bank * 8) & 0xFF) << 20);
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bank_end = (((ext_mem_end >> bank * 8) & 3) << 30) |
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(((mem_end >> bank * 8) & 0xFF) << 20) | 0xFFFFFUL;
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if (bank && bank_start != ram_size)
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LOG_F(WARNING, "MPC106: RAM not contiguous!");
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LOG_F(WARNING, "Grackle: RAM not contiguous!");
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ram_size += bank_end - bank_start + 1;
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}
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}
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if (!this->add_ram_region(0, ram_size)) {
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LOG_F(WARNING, "MPC106 RAM allocation 0x%X..0x%X failed (maybe already exists?)",
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LOG_F(WARNING, "Grackle: RAM allocation 0x%X..0x%X failed (maybe already exists?)",
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0, ram_size - 1);
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}
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}
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -19,7 +19,7 @@ You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** MPC106 (Grackle) emulation
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/** MPC106 (Grackle) definitions.
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Grackle IC is a combined memory and PCI controller manufactured by Motorola.
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It's the central device in the Gossamer architecture.
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@ -31,8 +31,8 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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- our virtual device reports revision 4.0 as expected by machine firmware
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*/
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#ifndef MPC106_H_
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#define MPC106_H_
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#ifndef MPC106_H
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#define MPC106_H
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#include <devices/common/mmiodevice.h>
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#include <devices/common/pci/pcidevice.h>
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@ -43,6 +43,32 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <memory>
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#include <unordered_map>
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/** Grackle configuration space registers. */
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enum GrackleReg : uint32_t {
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CFG10 = 0x40, // bus # + subordinate bus # + disconnect counter
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PMCR1 = 0x70, // power management config 1
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MSAR1 = 0x80, // memory starting address 1
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MSAR2 = 0x84, // memory starting address 2
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EMSAR1 = 0x88, // extended memory starting address 1
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EMSAR2 = 0x8C, // extended memory starting address 2
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MEAR1 = 0x90, // memory ending address 1
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MEAR2 = 0x94, // memory ending address 2
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EMEAR1 = 0x98, // extended memory ending address 1
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EMEAR2 = 0x9C, // extended memory ending address 2
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MBER = 0xA0, // memory bank enable
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PICR1 = 0xA8, // processor interface configuration 1
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PICR2 = 0xAC, // processor interface configuration 2
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MCCR1 = 0xF0, // memory control configuration 1
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MCCR2 = 0xF4, // memory control configuration 2
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MCCR3 = 0xF8, // memory control configuration 3
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MCCR4 = 0xFC // memory control configuration 4
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};
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/* MCCR1 bit definitions. */
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enum {
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MEMGO = 1 << 19,
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};
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class MPC106 : public MemCtrlBase, public PCIDevice, public PCIHost {
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public:
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MPC106();
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@ -74,92 +100,23 @@ protected:
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void setup_ram(void);
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private:
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uint8_t my_pci_cfg_hdr[256] = {
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0x57, 0x10, // vendor ID: Motorola
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0x02, 0x00, // device ID: MPC106
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0x06, 0x00, // PCI command
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0x80, 0x00, // PCI status
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0x40, // revision ID: 4.0
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0x00, // standard programming
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0x00, // subclass code: host bridge
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0x06, // class code: bridge device
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0x08, // cache line size
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0x00, // latency timer
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0x00, // header type
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0x00, // BIST Control
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0x00, // Interrupt line
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0x00, // Interrupt pin
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0x00, // MIN GNT
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0x00, // MAX LAT
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0x00, // Bus number
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0x00, // Subordinate bus number
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0x00, // Discount counter
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, // Performance monitor command
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0x00, 0x00, // Performance monitor mode control
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0xFF, 0xFF,
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 0
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 1
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 2
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0x00, 0x00, 0x00, 0x00, // Performance monitor counter 3
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF,
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0x00, 0x00, // Power mgt config 1
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0x00, // Power mgt config 2
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0xCD, // default value for ODCR
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, // Memory Starting Address
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Extended Memory Starting Address
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Memory Ending Address
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Extended Memory Ending Address
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0x00, // Memory bank enable
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0xFF, 0xFF,
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0x00, // Memory page mode
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0xFF, 0xFF, 0xFF, 0xFF,
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0x10, 0x00, 0x00, 0xFF, // PICR1
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0x0C, 0x06, 0x0C, 0x00, // PICR2
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0x00, // ECC single-bit error counter
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0x00, // ECC single-bit error trigger
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0x04, // Alternate OS visible paramaters 1
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0x01, // Alternate OS visible paramaters 2
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0xFF, 0xFF, 0xFF, 0xFF,
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0x01, // Error enabling 1
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0x00, // Error detection 1
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0xFF,
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0x00, // 60x bus error status
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0x00, // Error enabling 2
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0x00, // Error detection 2
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0xFF,
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0x00, // PCI bus error status
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0x00, 0x00, 0x00, 0x00, // 60x/PCI ERROR address
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF,
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0x42, 0x00, 0xFF, 0x0F, // Emulation support config 1
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0x00, 0x00, 0x00, 0x00, // Modified memory status (no clear)
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0x20, 0x00, 0x00, 0x00, // Emulation support config 2
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0x00, 0x00, 0x00, 0x00, // Modified memory status (clear)
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0x00, 0x00, 0x02, 0xFF, // Memory ctrl config 1
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0x03, 0x00, 0x00, 0x00, // Memory ctrl config 2
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0x00, 0x00, 0x00, 0x00, // Memory ctrl config 3
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0x00, 0x00, 0x10, 0x00 // Memory ctrl config 4
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};
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uint32_t config_addr;
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uint16_t pmcr1 = 0; // power management config 1
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uint8_t pmcr2 = 0; // power management config 2
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uint8_t odcr = 0xCD; // output driver control
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uint32_t picr1 = 0xFF100010; // ROM on CPU bus, address map B, CPU type = MPC601
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uint32_t picr2 = 0x000C060C;
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uint32_t mccr1 = 0xFF820000; // 64bit ROM bus
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uint32_t mccr2 = 3;
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uint32_t mccr3 = 0;
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uint32_t mccr4 = 0x00100000;
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uint32_t mem_start[2] = {};
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uint32_t ext_mem_start[2] = {};
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uint32_t mem_end[2] = {};
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uint32_t ext_mem_end[2] = {};
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uint8_t mem_bank_en = 0;
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};
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#endif
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#endif // MPC106_H
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