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The MPC106, codenamed "Grackle", is a memory controller and PCI host bridge. Its predecessor was the MPC105, codenamed "Bandit".
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Unlike the CPU, the Grackle runs in little-endian mode in compliance with the PCI standard. This usually means that to get the result in the correct endian, the PowerPC must load and store byte-reversed inputs and results.
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Unlike the CPU, which generally runs in big-endian mode, the Grackle runs in little-endian mode in compliance with the PCI standard. This usually means that to get the result in the correct endian, the PowerPC must load and store byte-reversed inputs and results.
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By default, Grackle operates on Address Map B.
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CONFIG_ADDR can be found at any address in the range 0xFEC00000–0xFEDFFFFF, while CONFIG_DAT can be found at any address in the range 0xFEE00000–0xFEEFFFFF
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CONFIG_ADDR can be found at any address in the range 0xFEC00000–0xFEDFFFFF, while CONFIG_DAT can be found at any address in the range 0xFEE00000–0xFEEFFFFF. The device trees also establish 0xFEF00000 as the 8259 interrupt acknowledgement register.
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PCI Config addresses work as follows:
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bus << 16 | device << 11 | function << 8 | offset
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#Revisions
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# Revisions
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Revisions under 4.0 could allow up to 75 MHz, whereas 4.0 and newer can allow up to 83 MHz.
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# General Data
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Vendor ID: 0x1057 (Motorola)
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Device ID: 0x0002 (MPC106)
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Within the Mac's own device tree, this is usually device 0.
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It also spans for 0x7F000000 bytes starting from 0x80000000.
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# VIRTUAL MEMORY MAP
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| Address | Area |
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|:-------------:|:--------------------------------------:|
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| 0x5FFFE000 | InfoRecord |
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| 0x5FFFEFF0 | NKSystemInfo |
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| 0x68000000 | Motorola 68K Emulator (0x100000 bytes) |
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| 0x68060000 | Emulator Code |
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| 0x68080000 | Opcode Dispatch Table |
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| 0x68FFE000 | KernelData |
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| 0x68FFF000 | EmulatorData |
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| 0xFF800000 | OpenFirmware |
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| 0xFFF0C000 | HardwarePriv |
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# PHYSICAL MEMORY MAP
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## NuBus Power Macs
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(Sourced Heavily from: http://mess.redump.net/mess/driver_info/mac_technical_notes)
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|Starting Address|Ending Address| Area |
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|:--------------:|:------------:|:----------------------------:|
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| 0x00000000 | 0x3FFFFFFF | Main Memory |
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| 0x40000000 | 0x4FFFFFFF | ROM Mirrors |
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| 0x50000000 | 0x5FFFFFFF | IO Devices |
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| 0x5FFFFFFC | | "cpuid", really a Machine ID |
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| 0x60000000 | 0xEFFFFFFF | NuBus "super slot" space |
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| 0xF1000000 | 0xFFBFFFFF | NuBus "standard slot" space |
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| 0xFFC00000 | 0xFFFFFFFF | ROM |
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## PCI Power Macs
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### Main Memory
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* 0x00000000 - 0x7FFFFFFF
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Mac OS
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* 0x00400000 - OpenFirmware
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### PCI/Device Memory Area 0x80000000 - 0xFF000000
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* 0x81000000 - Video Display Device (normally)
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* 0xF3000000 -
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Mac OS I/O Device area
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* 0xF3008000 - 0xF3008FFF - DMA Channels
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* 0xF3008000 - SCSI DMA
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* 0xF3008100 - Floppy DMA
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* 0xF3008200 - Ethernet transmit DMA
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* 0xF3008300 - Ethernet receive DMA
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* 0xF3008400 - SCC channel A transmit DMA
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* 0xF3008500 - SCC channel A receive DMA
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* 0xF3008600 - SCC channel B transmit DMA
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* 0xF3008700 - SCC channel B receive DMA
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* 0xF3008800 - Audio out DMA
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* 0xF3008900 - Audio in DMA
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* 0xF3009000 - ATI Mach 64 video card
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* 0xF3010000 - SCSI device registers (0x100 bytes)
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* 0xF3011000 - MACE (serial) device registers (0x100 bytes)
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* 0xF3012000 - SCC compatibility port (?) (0x100 bytes)
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* 0xF3013000 - SCC MacRISC port (Serial for 0x20, then Modem for 0x20, with remaining 0xC0 unknown)
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* 0xF3014000 - AWAC (Audio) chip device registers
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* 0xF3015000 - SWIM3 (floppy controller) device registers
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* 0xF3016000 - pseudo VIA1 device registers
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* 0xF3017000 - pseudo VIA2 device registers
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* 0xF3020000 - Heathrow ATA
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* 0xF8000000 - Hammerhead memory controller registers (0x1000000 bytes)
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* 0xFE010000 - 53C875 Hard Drive Controller
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* 0xFE000000 - Grackle Low/Base
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* 0xFEC00000 - Grackle CONFIG_ADDR (0x4 bytes, all redirected to 0xXXXXXCF8)
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* 0xFEE00000 - Grackle CONFIG_DATA (0x4 bytes, all redirected to 0xXXXXXCFF)
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### ROM / Misc Area (0xFF000000 - 0xFFFFFFFF)
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* 0xFF000000 - ?
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* 0xFF000004 - "cpuid", really a machine ID
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* 0xFFC00000 - 0xFFFFFFFF
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Mac OS ROM Area
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* 0xFFC00000 - 0xFFEFFFFF - 68k Code Area
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(below addresses apply to Old World ROMs)
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* 0xFFF00100 - Reset Area (where the ROM begins executing)
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* 0xFFF10000 - Nanokernel Code
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* 0xFFF20000 - HW Init
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@ -2,6 +2,16 @@
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The Old World ROM is always 4 megabytes (MB). The first three MB are reserved for the 68k code, while the last MB is for the PowerPC boot-up code.
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# BMac
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The BMac is an ethernet controller.
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The max frame size is 0x5EE bytes.
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It resides on 0xF3011000, with Writing DMA on 0xF3008200 and Reading DMA on 0xF3008300.
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Swim3 is located at 0xF3015000.
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# Serial
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For serial, it replicates the functionality of a Zilog ESCC. There are two different ports - one located at 0xF3013000 for the printer, and the other at 0xF3013020 for the modem.
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@ -2,6 +2,29 @@ Using a combination of a 6522 along with some integrated circuits, the VIA Cuda
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The usual offset for a VIA Cuda is IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x16000. The registers are spaced out by 0x200 bytes on the Heathrow.
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# Registers
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Within the emulated CUDA, these registers are spaced apart by 0x200 bytes. Apple themselves recommended avoiding the usage of Handshake Data A.
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| Register Name |Abbreviation| Offset |
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|:-------------------------:|:----------:|:------:|
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| Data B | ORB | 0x0 |
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| Handshake Data A | ORA(H) | 0x1 |
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| Data Direction B | DIRB | 0x2 |
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| Data Direction A | DIRA | 0x3 |
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| Timer 1 Counter Low | T1C | 0x4 |
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| Timer 1 Counter High | T1CH | 0x5 |
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| Timer 1 Latch Low | T1L | 0x6 |
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| Timer 1 Latch High | T1LH | 0x7 |
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| Timer 2 Counter Low | T2C | 0x8 |
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| Timer 2 Counter High | T2CH | 0x9 |
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| Shift | SR | 0xA |
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| Auxiliary Control | ACR | 0xB |
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| Peripheral Control | PCR | 0xC |
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| Interrupt Flag | IFE | 0xD |
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| Interrupt Enable | IER | 0xE |
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| Data A | ORA | 0xF |
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# Usage
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The VIA Cuda is emulated in all Power Macs through an interrupt controller. Early Power Macs also used the Parameter RAM.
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