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Improve zdoc/bmac documentation.
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@ -30,15 +30,15 @@ BMac registers are located at offset 0x11000 starting from the I/O controller ba
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| XIFC | 0x000 | Transceiver interface configuration register |
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| TXFIFOCSR | 0x100 | Transceiver FIFO control & status register |
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| TXTH | 0x110 |
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| TXTH | 0x110 | Transceiver FIFO treshold |
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| RXFIFOCSR | 0x120 | Receiver FIFO control & status register |
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| MEMADD | 0x130 |
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| XCVRIF | 0x160 |
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| CHIPID | 0x170 | Chip aka Ethernet cell identification register |
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| MIFCSR | 0x180 | Media interface control & status register |
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| SROMCSR | 0x190 | Serial EEPROM control & status register |
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| TXPNTR | 0x1A0 |
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| RXPNTR | 0x1B0 |
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| TXPNTR | 0x1A0 | Transceiver pointer |
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| RXPNTR | 0x1B0 | Receiver pointer |
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| STATUS | 0x200 | Global status register |
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| INTDISABLE | 0x210 | Global interrupt disable register |
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| TXRST | 0x420 | Transceiver software reset |
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@ -54,11 +54,11 @@ BMac registers are located at offset 0x11000 starting from the I/O controller ba
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| TXMAX | 0x4C0 | Transceiver maximum frame size register |
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| TXMIN | 0x4D0 | Transceiver minimum frame size register |
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| PAREG | 0x4E0 | Transceiver peak attempts register |
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| DCNT | 0x4F0 |
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| NCCNT | 0x500 |
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| NTCNT | 0x510 |
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| EXCNT | 0x520 |
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| LTCNT | 0x530 |
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| DCNT | 0x4F0 | Defer timer (counter ?) |
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| NCCNT | 0x500 | Normal collision counter |
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| NTCNT | 0x510 | Network collision counter |
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| EXCNT | 0x520 | Excessive collision counter |
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| LTCNT | 0x530 | Late collision counter |
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| RSEED | 0x540 | Transceiver random number seed register |
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| TXSM | 0x550 | Transceiver state machine register |
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| RXRST | 0x620 | Receiver software reset register |
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