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https://github.com/dingusdev/dingusppc.git
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Merge pull request #6 from maximumspatium/master
Map->Array replacements.
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dingusdev
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commit
c11bddc47f
2
main.cpp
2
main.cpp
@ -145,7 +145,7 @@ void ppc_tbr_update()
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}
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}
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void ppc_expection_handler(uint32_t exception_type, uint32_t handle_args){
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void ppc_exception_handler(uint32_t exception_type, uint32_t handle_args){
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ppc_next_instruction_address = 0x0; //used to construct a new address
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grab_exception = true;
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29
ppcemumain.h
29
ppcemumain.h
@ -217,7 +217,7 @@ void ppc_setsoov(uint32_t a, uint32_t b);
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void ppc_changecrf0(uint32_t set_result);
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void ppc_tbr_update();
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void ppc_expection_handler(uint32_t exception_type, uint32_t handle_args);
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void ppc_exception_handler(uint32_t exception_type, uint32_t handle_args);
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//MEMORY DECLARATIONS
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extern unsigned char * machine_sysram_mem;
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@ -605,26 +605,6 @@ extern void ppc_psq_stu();
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extern void ppc_main_opcode();
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//A listing of all of the available opcodes on the PPC.
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static std::map<uint8_t, PPCOpcode> OpcodeGrabber =
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{{0, &ppc_illegalop}, {1, &ppc_illegalop}, {2, &ppc_illegalop}, {3, &ppc_twi},
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{4, &ppc_opcode4}, {5, &ppc_illegalop}, {6, &ppc_illegalop}, {7, &ppc_mulli},
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{8, &ppc_subfic}, {9, &power_dozi}, {10, &ppc_cmpli}, {11, &ppc_cmpi},
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{12, &ppc_addic}, {13, &ppc_addicdot}, {14, &ppc_addi}, {15, &ppc_addis},
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{16, &ppc_opcode16}, {17, &ppc_sc}, {18, &ppc_opcode18}, {19, &ppc_opcode19},
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{20, &ppc_rlwimi}, {21, &ppc_rlwinm}, {22, &power_rlmi}, {23, &ppc_rlwnm},
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{24, &ppc_ori}, {25, &ppc_oris}, {26, &ppc_xori}, {27, &ppc_xoris},
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{28, &ppc_andidot}, {29, &ppc_andisdot}, {30, &ppc_illegalop}, {31, &ppc_opcode31},
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{32, &ppc_lwz}, {33, &ppc_lwzu}, {34, &ppc_lbz}, {35, &ppc_lbzu},
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{36, &ppc_stw}, {37, &ppc_stwu}, {38, &ppc_stb}, {39, &ppc_stbu},
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{40, &ppc_lhz}, {41, &ppc_lhzu}, {42, &ppc_lha}, {43, &ppc_lhau},
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{44, &ppc_sth}, {45, &ppc_sthu}, {46, &ppc_lmw}, {47, &ppc_stmw},
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{48, &ppc_lfs}, {49, &ppc_lfsu}, {50, &ppc_lfd}, {51, &ppc_lfdu},
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{52, &ppc_stfs}, {53, &ppc_stfsu}, {54, &ppc_stfd}, {55, &ppc_stfdu},
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{56, &ppc_psq_l}, {57, &ppc_psq_lu}, {58, &ppc_illegalop}, {59, &ppc_opcode59},
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{60, &ppc_psq_st}, {61, &ppc_psq_stu}, {62, &ppc_illegalop}, {63, &ppc_opcode63}};
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//All of the opcodes possible are generated from the first 6 bits
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//of each instruction given by the processor.
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@ -644,13 +624,6 @@ static std::map<uint8_t, PPCOpcode> OpcodeGrabber =
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table, partially due to instructions that use either 6 or 11 bits
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for the instruction.
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**/
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static std::map<uint8_t, PPCOpcode> SubOpcode16Grabber=
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{{0, &ppc_bc}, {1, &ppc_bcl}, {2, &ppc_bca}, {3, &ppc_bcla}
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};
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static std::map<uint8_t, PPCOpcode> SubOpcode18Grabber=
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{{0, &ppc_b}, {1, &ppc_bl}, {2, &ppc_ba}, {3, &ppc_bla}
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};
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static std::map<uint16_t, PPCOpcode> SubOpcode19Grabber=
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{{32, &ppc_bclr}, {33, &ppc_bclrl}, {66, &ppc_crnor}, {100, &ppc_rfi},
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@ -545,7 +545,7 @@ void address_quickinsert_translate(uint32_t value_insert, uint32_t address_grab,
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final_grab |= (address_grab & 0x1FFFF);
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//Check the PP Tags in the batl
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//if (!(ppc_state.ppc_spr[grab_batl] == 0x2)){
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// ppc_expection_handler(0x0300, 0x0);
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// ppc_exception_handler(0x0300, 0x0);
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// }
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address_grab = final_grab;
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}
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@ -769,7 +769,7 @@ void address_quickgrab_translate(uint32_t address_grab, uint8_t bit_num){
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final_grab |= (address_grab & 0x1FFFF);
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//Check the PP Tags in the batl
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//if ((ppc_state.ppc_spr[grab_batl] & 0x3) == 0x0){
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// ppc_expection_handler(0x0300, 0x0);
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// ppc_exception_handler(0x0300, 0x0);
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//}
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address_grab = final_grab;
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}
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@ -974,7 +974,7 @@ void quickinstruction_translate(uint32_t address_grab){
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final_grab |= (((address_grab & 0x0FFE0000) & blocklen) | (ppc_state.ppc_spr[grab_batl] & 0xFFFE0000));
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final_grab |= (address_grab & 0x1FFFF);
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//if ((ppc_state.ppc_spr[grab_batl] & 0x3) == 0x0){
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// ppc_expection_handler(0x0400, 0x0);
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// ppc_exception_handler(0x0400, 0x0);
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//}
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address_grab = final_grab;
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}
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@ -58,6 +58,34 @@
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uint32_t strwrd_replace_value;
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/** Lookup tables. */
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/** Primary opcode (bits 0...5) lookup table. */
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static PPCOpcode OpcodeGrabber[] = {
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ppc_illegalop, ppc_illegalop, ppc_illegalop, ppc_twi, ppc_opcode4,
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ppc_illegalop, ppc_illegalop, ppc_mulli, ppc_subfic, power_dozi,
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ppc_cmpli, ppc_cmpi, ppc_addic, ppc_addicdot, ppc_addi,
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ppc_addis, ppc_opcode16, ppc_sc, ppc_opcode18, ppc_opcode19,
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ppc_rlwimi, ppc_rlwinm, power_rlmi, ppc_rlwnm, ppc_ori,
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ppc_oris, ppc_xori, ppc_xoris, ppc_andidot, ppc_andisdot,
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ppc_illegalop, ppc_opcode31, ppc_lwz, ppc_lwzu, ppc_lbz,
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ppc_lbzu, ppc_stw, ppc_stwu, ppc_stb, ppc_stbu,
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ppc_lhz, ppc_lhzu, ppc_lha, ppc_lhau, ppc_sth,
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ppc_sthu, ppc_lmw, ppc_stmw, ppc_lfs, ppc_lfsu,
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ppc_lfd, ppc_lfdu, ppc_stfs, ppc_stfsu, ppc_stfd,
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ppc_stfdu, ppc_psq_l, ppc_psq_lu, ppc_illegalop, ppc_illegalop,
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ppc_psq_st, ppc_psq_stu, ppc_illegalop, ppc_opcode63
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};
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/** Lookup tables for branch instructions. */
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static PPCOpcode SubOpcode16Grabber[] = {
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ppc_bc, ppc_bcl, ppc_bca, ppc_bcla
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};
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static PPCOpcode SubOpcode18Grabber[] = {
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ppc_b, ppc_bl, ppc_ba, ppc_bla
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};
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/**
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Extract the registers desired and the values of the registers
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This also takes the MSR into account, mainly to determine
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@ -206,7 +234,7 @@ void ppc_illegalop(){
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uint32_t grab_it = (uint32_t) illegal_code;
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printf("Illegal opcode reported: %d Report this! \n", grab_it);
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exit(-1);
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//ppc_expection_handler(0x0700, 0x80000);
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//ppc_exception_handler(0x0700, 0x80000);
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}
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void ppc_illegalsubop31(){
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@ -224,23 +252,11 @@ void ppc_opcode4(){
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}
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void ppc_opcode16(){
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uint8_t subop_grab = ppc_cur_instruction & 3;
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#ifdef EXHAUSTIVE_DEBUG
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uint32_t regrab = (uint32_t)subop_grab;
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printf("Executing Opcode 16 table subopcode entry %d \n", regrab);
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SubOpcode16Grabber[subop_grab]();
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#else
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SubOpcode16Grabber[subop_grab]();
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#endif // EXHAUSTIVE_DEBUG
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SubOpcode16Grabber[ppc_cur_instruction & 3]();
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}
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void ppc_opcode18(){
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uint8_t subop_grab = ppc_cur_instruction & 3;
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//printf("Reading from Opcode 18 table \n");
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//uint32_t regrab = (uint32_t)subop_grab;
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//printf("Executing subopcode entry %d \n", regrab);
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SubOpcode18Grabber[subop_grab]();
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SubOpcode18Grabber[ppc_cur_instruction & 3]();
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}
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void ppc_opcode19(){
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@ -253,7 +269,7 @@ void ppc_opcode19(){
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}
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else{
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std::cout << "ILLEGAL SUBOPCODE: " << subop_grab << std::endl;
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ppc_expection_handler(0x0700, 0x80000);
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ppc_exception_handler(0x0700, 0x80000);
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}
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#else
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SubOpcode19Grabber[subop_grab]();
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@ -270,7 +286,7 @@ void ppc_opcode31(){
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}
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else{
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std::cout << "ILLEGAL SUBOPCODE: " << subop_grab << std::endl;
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ppc_expection_handler(0x0700, 0x80000);
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ppc_exception_handler(0x0700, 0x80000);
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}
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#else
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SubOpcode31Grabber[subop_grab]();
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@ -287,7 +303,7 @@ void ppc_opcode59(){
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}
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else{
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std::cout << "ILLEGAL SUBOPCODE: " << subop_grab << std::endl;
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ppc_expection_handler(0x0700, 0x80000);
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ppc_exception_handler(0x0700, 0x80000);
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}
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#else
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SubOpcode59Grabber[subop_grab]();
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@ -304,7 +320,7 @@ void ppc_opcode63(){
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}
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else{
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std::cout << "ILLEGAL SUBOPCODE: " << subop_grab << std::endl;
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ppc_expection_handler(0x0700, 0x80000);
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ppc_exception_handler(0x0700, 0x80000);
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}
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#else
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SubOpcode63Grabber[subop_grab]();
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@ -1841,7 +1857,7 @@ void ppc_rfi(){
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}
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void ppc_sc(){
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ppc_expection_handler(0x0C00, 0x20000);
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ppc_exception_handler(0x0C00, 0x20000);
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}
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void ppc_tw(){
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@ -1853,7 +1869,7 @@ void ppc_tw(){
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(((int32_t)ppc_state.ppc_gpr[reg_a] == (int32_t)ppc_state.ppc_gpr[reg_b]) & (ppc_to & 0x04)) || \
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((ppc_state.ppc_gpr[reg_a] < ppc_state.ppc_gpr[reg_b]) & (ppc_to & 0x02)) || \
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((ppc_state.ppc_gpr[reg_a] > ppc_state.ppc_gpr[reg_b]) & (ppc_to & 0x01))){
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ppc_expection_handler(0x0700, 0x20000);
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ppc_exception_handler(0x0700, 0x20000);
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}
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}
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@ -1866,7 +1882,7 @@ void ppc_twi(){
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(((int32_t)ppc_state.ppc_gpr[reg_a] == simm) & (ppc_to & 0x04)) || \
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((ppc_state.ppc_gpr[reg_a] < (uint32_t)simm) & (ppc_to & 0x02)) || \
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((ppc_state.ppc_gpr[reg_a] > (uint32_t)simm) & (ppc_to & 0x01))){
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ppc_expection_handler(0x0700, 0x20000);
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ppc_exception_handler(0x0700, 0x20000);
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}
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}
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@ -1924,7 +1940,7 @@ void ppc_dcbz(){
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address_quickinsert_translate(0, (ppc_effective_address + 28), 4);
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}
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else{
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ppc_expection_handler(0x0600, 0x00000);
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ppc_exception_handler(0x0600, 0x00000);
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}
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}
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@ -1962,7 +1978,7 @@ void ppc_stbux(){
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address_quickinsert_translate(ppc_result_d, ppc_effective_address, 1);
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}
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else{
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ppc_expection_handler(0x07000, 0x20000);
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ppc_exception_handler(0x07000, 0x20000);
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}
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ppc_result_a = ppc_effective_address;
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ppc_store_result_rega();
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@ -2087,7 +2103,7 @@ void ppc_lbzu(){
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ppc_effective_address = ppc_result_a + grab_d;
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}
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else{
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ppc_expection_handler(0x0700, 0x20000);
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ppc_exception_handler(0x0700, 0x20000);
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}
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address_quickgrab_translate(ppc_effective_address, 1);
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ppc_result_d = return_value;
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@ -2112,7 +2128,7 @@ void ppc_lbzux(){
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ppc_effective_address = ppc_result_a + ppc_result_b;
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}
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else{
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ppc_expection_handler(0x0700, 0x20000);
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ppc_exception_handler(0x0700, 0x20000);
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}
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address_quickgrab_translate(ppc_effective_address, 1);
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ppc_result_d = return_value;
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@ -2271,7 +2287,7 @@ void ppc_lwzu(){
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ppc_effective_address = ppc_result_a + grab_d;
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}
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else{
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ppc_expection_handler(0x0700, 0x20000);
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ppc_exception_handler(0x0700, 0x20000);
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}
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address_quickgrab_translate(ppc_effective_address, 4);
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ppc_result_d = return_value;
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@ -2296,7 +2312,7 @@ void ppc_lwzux(){
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ppc_effective_address = ppc_result_a + ppc_result_b;
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}
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else{
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ppc_expection_handler(0x0700, 0x20000);
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ppc_exception_handler(0x0700, 0x20000);
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}
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address_quickgrab_translate(ppc_effective_address, 4);
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ppc_result_d = return_value;
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@ -2385,10 +2401,10 @@ void ppc_lswx(){
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ppc_grab_regsdab();
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//Invalid instruction forms
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if ((ppc_result_d == 0) && (ppc_result_a == 0)){
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ppc_expection_handler(0x0700, 0x100000);
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ppc_exception_handler(0x0700, 0x100000);
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}
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if ((ppc_result_d == ppc_result_a) || (ppc_result_a == ppc_result_b)){
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ppc_expection_handler(0x0700, 0x100000);
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ppc_exception_handler(0x0700, 0x100000);
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}
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ppc_effective_address = (reg_a == 0)?ppc_result_b:(ppc_result_a + ppc_result_b);
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grab_inb = ppc_state.ppc_spr[1] & 127;
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