mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-06-09 07:29:36 +00:00
Implemented most remaining opcodes
This commit is contained in:
dingusdev
parent
cee51b643e
commit
d277ab693e
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@ -85,6 +85,13 @@ const char* opc_int_ldst[16] = { /* integer load and store instructions */
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"lha", "lhau", "sth", "sthu", "lmw", "stmw"
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};
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const char* proc_mgmt_str[32] = { /* processor managment + byte reversed load and store*/
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"", "dcbst", "dcbf", "", "stwcx.", "", "", "dcbtst",
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"dcbt", "eciwx", "", "", "", "ecowx", "dcbi", "",
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"lwbrx", "tlbsync", "sync", "", "stwbrx", "", "", "dcba",
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"lhbrx", "", "eieio", "", "sthbrx", "", "icbi", "dcbz"
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};
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const char* opc_flt_ldst[8] = { /* integer load and store instructions */
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"lfs", "lfsu", "lfd", "lfdu", "stfs", "stfsu", "sftd", "sftdu"
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};
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@ -213,16 +220,36 @@ void opc_ar_im(PPCDisasmContext* ctx)
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auto rd = (ctx->instr_code >> 21) & 0x1F;
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int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
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if ((ctx->instr_code >> 26) == 0xE && !ra && ctx->simplified) {
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fmt_twoop_simm(ctx->instr_str, "li", rd, imm);
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}
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else if ((ctx->instr_code >> 26) == 0xF && !ra && ctx->simplified) {
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fmt_twoop_simm(ctx->instr_str, "lis", rd, imm);
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}
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else {
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fmt_threeop_simm(ctx->instr_str, arith_im_mnem[(ctx->instr_code >> 26) - 7],
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rd, ra, imm);
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if (ctx->simplified) {
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if (((ctx->instr_code >> 26) == 0xE) & !ra) {
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fmt_twoop_simm(ctx->instr_str, "li", rd, imm);
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return;
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}
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else if (((ctx->instr_code >> 26) == 0xF) & !ra) {
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fmt_twoop_simm(ctx->instr_str, "lis", rd, imm);
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return;
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}
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if (imm > 0x7FFF) {
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switch ((ctx->instr_code >> 26)) {
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case 0xC:
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fmt_threeop_simm(ctx->instr_str, "subic", rd, ra, imm);
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return;
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case 0xD:
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fmt_threeop_simm(ctx->instr_str, "subic.", rd, ra, imm);
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return;
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case 0xE:
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fmt_threeop_simm(ctx->instr_str, "subi", rd, ra, imm);
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return;
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case 0xF:
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fmt_threeop_simm(ctx->instr_str, "subis", rd, ra, imm);
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return;
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}
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}
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}
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fmt_threeop_simm(ctx->instr_str, arith_im_mnem[(ctx->instr_code >> 26) - 7],
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rd, ra, imm);
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}
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void power_dozi(PPCDisasmContext* ctx)
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@ -270,6 +297,18 @@ void opc_rlwnm(PPCDisasmContext* ctx)
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auto mb = (ctx->instr_code >> 6) & 0x1F;
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auto me = (ctx->instr_code >> 1) & 0x1F;
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if (ctx->simplified) {
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if ((me == 31) & (mb == 0)) {
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if (ctx->instr_code & 1) {
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fmt_rotateop(ctx->instr_str, "rotlw.", rs, ra, rb, mb, me, false);
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return;
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}
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else {
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fmt_rotateop(ctx->instr_str, "rotlw", rs, ra, rb, mb, me, false);
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return;
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}
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}
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}
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if (ctx->instr_code & 1)
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fmt_rotateop(ctx->instr_str, "rlwnm.", rs, ra, rb, mb, me, false);
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else
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@ -462,7 +501,7 @@ void opc_bclrx(PPCDisasmContext* ctx)
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strcat(opcode, "d");
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strcat(opcode, (bo & 2) ? "z" : "nz");
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if (!(bo & 0x10)) {
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strcat(opcode, (bo & 8) ? "t" : "f");
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strcat(opcode, (bo & 8) ? "tlr" : "flr");
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if (cr) {
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strcat(operands, "4*cr0+");
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operands[4] = cr + '0';
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@ -592,7 +631,12 @@ void opc_group19(PPCDisasmContext* ctx)
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ctx->instr_str = my_sprintf("%-8sr%d", "isync");
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return;
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case 193:
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fmt_threeop_crb(ctx->instr_str, "crxor", rs, ra, rb);
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if (ctx->simplified && (rs == ra) && (rs == rb)) {
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ctx->instr_str = my_sprintf("%-8scrb%d", "crclr", rs);
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}
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else {
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fmt_threeop_crb(ctx->instr_str, "crxor", rs, ra, rb);
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}
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return;
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case 225:
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fmt_threeop_crb(ctx->instr_str, "crnand", rs, ra, rb);
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@ -688,10 +732,31 @@ void opc_group31(PPCDisasmContext* ctx)
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if ((!index || index == 2) && (ext_opc & 0x200))
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opc_illegal(ctx);
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else
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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fmt_threeop_simm(ctx->instr_str, opcode, rs, ra, rb);
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}
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return;
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case 0x12: /* tlb instructions */
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if (index == 11) {
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ctx->instr_str = my_sprintf("%-8s", "tlbia");
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}
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else if (index == 18) {
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ctx->instr_str = my_sprintf("%-8sr%s", "tlbie", rb);
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}
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return;
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case 0x18: /* Shifting instructions */
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if (index == 0)
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fmt_threeop(ctx->instr_str, "slw", rs, ra, rb);
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else if (index == 16)
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fmt_threeop(ctx->instr_str, "srw", rs, ra, rb);
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else if (index == 24)
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fmt_threeop(ctx->instr_str, "sraw", rs, ra, rb);
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else if (index == 25)
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fmt_threeop_uimm(ctx->instr_str, "srawi", rs, ra, rb);
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return;
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case 0x1A: /* Byte sign extend instructions */
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if (index == 28)
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fmt_twoop(ctx->instr_str, "extsh", rs, ra);
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@ -716,6 +781,7 @@ void opc_group31(PPCDisasmContext* ctx)
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}
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return;
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case 0x17: /* indexed load/store instructions */
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if (index > 23 || rc_set || strlen(opc_idx_ldst[index]) == 0) {
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opc_illegal(ctx);
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@ -727,6 +793,25 @@ void opc_group31(PPCDisasmContext* ctx)
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ctx->instr_str = my_sprintf("%-8sfp%d, r%d, r%d",
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opc_idx_ldst[index], rs, ra, rb);
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return;
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case 0x16: /* processor mgmt + byte reversed load and store instructions */
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strcpy(opcode, proc_mgmt_str[index]);
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if ((index == 4) | (index == 9) | (index == 13) | (index == 16) \
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| (index == 20) | (index == 24) | (index == 28)) {
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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return;
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break;
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}
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else if ((index == 18)) {
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ctx->instr_str = my_sprintf("%-8s", opcode);
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return;
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}
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else {
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fmt_twoop(ctx->instr_str, opcode, ra, rb);
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}
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return;
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break;
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}
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@ -764,7 +849,7 @@ void opc_group31(PPCDisasmContext* ctx)
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, r%d", "cmpl", rs, ra, rb);
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break;
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case 83: /* mfmsr */
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ctx->instr_str = my_sprintf("%-8s0x%02X, r%d", "mfmsr",
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ctx->instr_str = my_sprintf("%-8sr%d", "mfmsr",
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(ctx->instr_code >> 21) & 0x1F);
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break;
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case 144: /* mtcrf */
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@ -779,16 +864,45 @@ void opc_group31(PPCDisasmContext* ctx)
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fmt_oneop(ctx->instr_str, "mtmsr", rs);
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break;
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case 339: /* mfspr */
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if (ctx->simplified) {
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switch (ref_spr) {
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case 1:
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ctx->instr_str = my_sprintf("%-8sr%d", "mfxer", rs);
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return;
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case 8:
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ctx->instr_str = my_sprintf("%-8sr%d", "mflr", rs);
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return;
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case 9:
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ctx->instr_str = my_sprintf("%-8sr%d", "mfctr", rs);
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return;
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}
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}
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fmt_twoop_fromspr(ctx->instr_str, "mfspr", rs, ref_spr);
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break;
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case 371: /* mftb */
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fmt_twoop_tospr(ctx->instr_str, "mftb", ref_spr, rs);
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break;
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case 467: /* mtspr */
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if (ctx->simplified) {
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switch (ref_spr) {
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case 1:
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ctx->instr_str = my_sprintf("%-8sr%d", "mtxer", rs);
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return;
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case 8:
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ctx->instr_str = my_sprintf("%-8sr%d", "mtlr", rs);
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return;
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case 9:
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ctx->instr_str = my_sprintf("%-8sr%d", "mtctr", rs);
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return;
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}
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}
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fmt_twoop_tospr(ctx->instr_str, "mtspr", ref_spr, rs);
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break;
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case 598: /* sync */
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ctx->instr_str = my_sprintf("%-8s", "sync");
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case 533: /* lswx */
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fmt_threeop_simm(ctx->instr_str, "lswx", rs, ra, rb);
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break;
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case 597: /* lswi */
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fmt_threeop_simm(ctx->instr_str, "lswi", rs, ra, rb);
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break;
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default:
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opc_illegal(ctx);
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@ -1004,6 +1118,19 @@ void opc_group63(PPCDisasmContext* ctx)
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return;
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case 23: /* fsel */
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strcpy(opcode, "fsel");
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if (rc_set)
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strcat_s(opcode, ".");
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if ((rc != 0) | (ra != 0))
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opc_illegal(ctx);
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else
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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case 25: /* fmul */
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strcpy(opcode, opc_flt_ext_arith[25]);
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@ -1079,7 +1206,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rs & 3)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, crf%d, r%d, r%d", "fcmpu", (rs >> 2), ra, rb);
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ctx->instr_str = my_sprintf("%-8scrf%d, r%d, r%d,", "fcmpu", (rs >> 2), ra, rb);
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break;
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case 12: /* frsp */
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if (ra != 0)
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@ -1103,7 +1230,15 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rs & 3)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, crf%d, r%d, r%d", "fcmpu", (rs >> 2), ra, rb);
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ctx->instr_str = my_sprintf("%-8scrf%d, r%d, r%d,", "fcmpo", (rs >> 2), ra, rb);
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break;
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case 38: /* mtfsb1 */
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strcpy(opcode, "mtfsb1");
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if (rc_set)
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strcat(opcode, ".");
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ctx->instr_str = my_sprintf("%-8scrb%d", opcode, rs);
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break;
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case 40: /* fneg */
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strcpy(opcode, "fneg");
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@ -1116,6 +1251,14 @@ void opc_group63(PPCDisasmContext* ctx)
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else
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ctx->instr_str = my_sprintf("%-8sr%d, r%d", opcode, rs, rb);
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break;
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case 70: /* mtfsb0 */
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strcpy(opcode, "mtfsb0");
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if (rc_set)
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strcat(opcode, ".");
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ctx->instr_str = my_sprintf("%-8scrb%d", opcode, rs);
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break;
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case 72: /* fmr */
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if (ra != 0)
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opc_illegal(ctx);
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