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ppcopcodes: Cleanup ppc_rfi.
Reduce the number of operations by 1 and make more clear what is happening.
This commit is contained in:
+12
-8
@@ -1416,12 +1416,16 @@ void dppc_interpreter::ppc_rfi(uint32_t opcode) {
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return;
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}
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uint32_t old_msr_val = ppc_state.msr;
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uint32_t new_srr1_val = (ppc_state.spr[SPR::SRR1] & 0x87C0FF73UL);
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uint32_t new_msr_val = (ppc_state.msr & ~0x87C0FF73UL);
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// keep 0, 5-9, 16-23, 25-27, 30-31 bits; exclude POW, ILE, and Reserved bits.
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const uint32_t msr_bits_to_replace = 0x87C0FF73UL;
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const uint32_t msr_bits_to_clear = MSR::POW;
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new_msr_val = (new_msr_val | new_srr1_val) & 0xFFFBFFFFUL;
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ppc_msr_did_change(old_msr_val, new_msr_val);
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uint32_t bits_from_srr1 = ppc_state.spr[SPR::SRR1] &
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(msr_bits_to_replace & ~msr_bits_to_clear);
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uint32_t new_msr_val = (ppc_state.msr & ~(msr_bits_to_replace | msr_bits_to_clear)) |
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bits_from_srr1;
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ppc_msr_did_change(ppc_state.msr, new_msr_val);
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// generate External Interrupt Exception
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// if CPU interrupt line is still asserted
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@@ -1584,10 +1588,10 @@ void dppc_interpreter::ppc_stu(uint32_t opcode) {
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ea += ppc_result_a;
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mmu_write_vmem<T>(opcode, ea, ppc_result_d);
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ppc_state.gpr[reg_a] = ea;
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}
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}
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else {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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}
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}
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@@ -1609,7 +1613,7 @@ void dppc_interpreter::ppc_stux(uint32_t opcode) {
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}
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else {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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}
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}
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template void dppc_interpreter::ppc_stux<uint8_t>(uint32_t opcode);
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