sc53c94: Add registers and comments.
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joevt
dingusdev
parent
faf066f2b9
commit
f07de5401d
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -43,63 +43,103 @@ class InterruptCtrl;
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/** 53C94 read registers */
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namespace Read {
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enum Reg53C94 : uint8_t {
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Xfer_Cnt_LSB = 0,
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Xfer_Cnt_MSB = 1,
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FIFO = 2,
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Command = 3,
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Status = 4,
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Int_Status = 5,
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Seq_Step = 6,
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FIFO_Flags = 7,
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Config_1 = 8,
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Config_2 = 0xB,
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Config_3 = 0xC,
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Config_4 = 0xD, // Am53CF94 extension
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Xfer_Cnt_Hi = 0xE, // Am53CF94 extension
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Xfer_Cnt_LSB = 0, // Current Transfer Count Register LSB
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Xfer_Cnt_MSB = 1, // Current Transfer Count Register MSB
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FIFO = 2, // FIFO Register
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Command = 3, // Command Register
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Status = 4, // Status Register
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Int_Status = 5, // Interrupt Status Register
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Seq_Step = 6, // Internal State Register
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FIFO_Flags = 7, // Current FIFO/Internal State Register
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Config_1 = 8, // Control Register 1
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//
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//
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Config_2 = 0xB, // Control Register 2
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Config_3 = 0xC, // Control Register 3
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Config_4 = 0xD, // Control Register 4
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Xfer_Cnt_Hi = 0xE, // Current Transfer Count Register High ; Am53CF94 extension
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//
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};
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};
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/** 53C94 write registers */
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namespace Write {
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enum Reg53C94 : uint8_t {
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Xfer_Cnt_LSB = 0,
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Xfer_Cnt_MSB = 1,
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FIFO = 2,
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Command = 3,
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Dest_Bus_ID = 4,
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Sel_Timeout = 5,
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Sync_Period = 6,
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Sync_Offset = 7,
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Config_1 = 8,
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Clock_Factor = 9,
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Test_Mode = 0xA,
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Config_2 = 0xB,
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Config_3 = 0xC,
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Config_4 = 0xD, // Am53CF94 extension
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Xfer_Cnt_Hi = 0xE, // Am53CF94 extension
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Data_Align = 0xF
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Xfer_Cnt_LSB = 0, // Start Transfer Count Register LSB
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Xfer_Cnt_MSB = 1, // Start Transfer Count Register MSB
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FIFO = 2, // FIFO Register
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Command = 3, // Command Register
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Dest_Bus_ID = 4, // SCSI Destination ID Register (DID)
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Sel_Timeout = 5, // SCSI Timeout Register
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Sync_Period = 6, // Synchronous Transfer Period Register
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Sync_Offset = 7, // Synchronous Offset Register
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Config_1 = 8, // Control Register 1
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Clock_Factor = 9, // Clock Factor Register
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Test_Mode = 0xA, // Forced Test Mode Register
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Config_2 = 0xB, // Control Register 2
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Config_3 = 0xC, // Control Register 3
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Config_4 = 0xD, // Control Register 4 ; Am53CF94 extension
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Xfer_Cnt_Hi = 0xE, // Start Transfer Count Register High ; Am53CF94 extension
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Data_Align = 0xF, // Data Alignment Register
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};
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};
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/** NCR53C94/Am53CF94 commands. */
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enum {
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CMD_NOP = 0,
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CMD_CLEAR_FIFO = 1,
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CMD_RESET_DEVICE = 2,
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CMD_RESET_BUS = 3,
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CMD_DMA_STOP = 4,
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CMD_XFER = 0x10,
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CMD_COMPLETE_STEPS = 0x11,
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CMD_MSG_ACCEPTED = 0x12,
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CMD_SELECT_NO_ATN = 0x41,
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CMD_SELECT_WITH_ATN = 0x42,
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CMD_ENA_SEL_RESEL = 0x44,
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// General Commands
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CMD_NOP = 0x00, // no interrupt
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CMD_CLEAR_FIFO = 0x01, // no interrupt
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CMD_RESET_DEVICE = 0x02, // no interrupt
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CMD_RESET_BUS = 0x03,
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// Initiator commands
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CMD_XFER = 0x10,
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CMD_COMPLETE_STEPS = 0x11,
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CMD_MSG_ACCEPTED = 0x12,
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//CMD_TRANSFER_PAD_BYTES = 0x18,
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CMD_SET_ATN = 0x1A, // no interrupt
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//CMD_RESET_ATN = 0x1B, // no interrupt
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// Target commands
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//CMD_SEND_MESSAGE = 0x20,
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//CMD_SEND_STATUS = 0x21,
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//CMD_SEND_DATA = 0x22,
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//CMD_DISCONNECT_STEPS = 0x23,
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//CMD_TERMINATE_STEPS = 0x24,
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//CMD_TARGET_COMMAND_COMPLETE_STEPS = 0x25,
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//CMD_DISCONNECT = 0x27, // no interrupt
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//CMD_RECEIVE_MESSAGE_STEPS = 0x28,
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//CMD_RECEIVE_COMMAND = 0x29,
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//CMD_RECEIVE_DATA = 0x2A,
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//CMD_RECEIVE_COMMAND_STEPS = 0x2B,
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CMD_DMA_STOP = 0x04, // no interrupt
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CMD_ACCESS_FIFO_COMMAND = 0x05,
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// Idle Commands
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//CMD_RESELECT_STEPS = 0x40,
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CMD_SELECT_NO_ATN = 0x41,
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CMD_SELECT_WITH_ATN = 0x42,
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//CMD_SELECT_WITH_ATN_AND_STOP = 0x43,
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CMD_ENA_SEL_RESEL = 0x44, // no interrupt
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//CMD_DISABLE_SEL_RESEL = 0x45,
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//CMD_SELECT_WITH_ATN3_STEPS = 0x46,
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//CMD_RESELECT_WITH_ATN3_STEPS = 0x47,
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// Flags
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CMD_OPCODE = 0x7F,
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CMD_ISDMA = 0x80,
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};
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/** Status register bits. **/
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enum {
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STAT_TC = 1 << 4, // Terminal count (NCR) / count to zero (AMD)
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STAT_GE = 1 << 6, // Gross Error (NCR) / Illegal Operation Error (AMD)
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//SCSI_CTRL_IO = 0x01, // Input/Output
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//SCSI_CTRL_CD = 0x02, // Command/Data
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//SCSI_CTRL_MSG = 0x04, // Message
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//STAT_GCV = 0x08, // Group Code Valid
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STAT_TC = 0x10, // Terminal count (NCR) / count to zero (AMD)
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//STAT_PE = 0x20, // Parity Error
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STAT_GE = 0x40, // Gross Error (NCR) / Illegal Operation Error (AMD)
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STAT_INT = 0x80, // Interrupt
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};
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/** Interrupt status register bits. */
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