mirror of
https://github.com/dingusdev/dingusppc.git
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Support for floating-point loads and stores
This commit is contained in:
dingusdev
parent
96e9351190
commit
f3befe9c16
@ -1,3 +1,7 @@
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/** @file Logic for the disassembler.
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@author maximumspatium
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*/
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#include <iostream>
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#include <string>
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#include <functional> //Mandated by Visual Studio
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@ -82,6 +86,13 @@ const char* opc_flt_ldst[8] = { /* integer load and store instructions */
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"lfs", "lfsu", "lfd", "lfdu", "stfs", "stfsu", "sftd", "sftdu"
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};
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const char* opc_flt_ext_arith[32] = { /* integer load and store instructions */
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "fsel",
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"", "fmul", "", "", "fmsub", "fmadd", "fnmsub", "fnmadd",
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};
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/** various formatting helpers. */
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void fmt_oneop(string& buf, const char* opc, int src)
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{
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@ -108,6 +119,11 @@ void fmt_twoop_tospr(string& buf, const char* opc, int dst, int src)
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buf = my_sprintf("%-8sr%d, spr%d", opc, dst, src);
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}
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void fmt_twoop_flt(string& buf, const char* opc, int dst, int src1)
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{
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buf = my_sprintf("%-8sfr%d, fr%d", opc, dst, src1);
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}
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void fmt_threeop(string& buf, const char* opc, int dst, int src1, int src2)
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{
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buf = my_sprintf("%-8sr%d, r%d, r%d", opc, dst, src1, src2);
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@ -129,6 +145,16 @@ void fmt_threeop_simm(string& buf, const char* opc, int dst, int src1, int imm)
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(imm < 0) ? "-" : "", abs(imm));
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}
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void fmt_threeop_flt(string& buf, const char* opc, int dst, int src1, int src2)
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{
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buf = my_sprintf("%-8sfr%d, fr%d, fr%d", opc, dst, src1, src2);
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}
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void fmt_fourop_flt(string& buf, const char* opc, int dst, int src1, int src2, int src3)
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{
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buf = my_sprintf("%-8sfr%d, fr%d, fr%d, fr%d", opc, dst, src1, src2, src3);
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}
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void fmt_rotateop(string& buf, const char* opc, int dst, int src1, int sh, int mb, int me, bool imm)
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{
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if (imm)
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@ -145,7 +171,32 @@ void opc_illegal(PPCDisasmContext* ctx)
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void opc_twi(PPCDisasmContext* ctx)
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{
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//return "DEADBEEF";
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auto to = (ctx->instr_code >> 21) & 0x1F;
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
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if (ctx->simplified) {
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switch (to) {
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case 1:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twlgti", ra, imm);
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break;
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case 6:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twllei", ra, imm);
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break;
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case 8:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twgti", ra, imm);
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break;
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case 16:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twlti", ra, imm);
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break;
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case 20:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twlei", ra, imm);
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break;
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}
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}
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else {
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ctx->instr_str = my_sprintf("%-8s%d, r%d, 0x%08X", "twi", to, ra, imm);
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}
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}
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void opc_group4(PPCDisasmContext* ctx)
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@ -162,6 +213,9 @@ void opc_ar_im(PPCDisasmContext* ctx)
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if ((ctx->instr_code >> 26) == 0xE && !ra && ctx->simplified) {
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fmt_twoop_simm(ctx->instr_str, "li", rd, imm);
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}
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else if ((ctx->instr_code >> 26) == 0xF && !ra && ctx->simplified) {
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fmt_twoop_simm(ctx->instr_str, "lis", rd, imm);
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}
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else {
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fmt_threeop_simm(ctx->instr_str, arith_im_mnem[(ctx->instr_code >> 26) - 7],
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rd, ra, imm);
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@ -392,12 +446,12 @@ void opc_bclrx(PPCDisasmContext* ctx)
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if (!ctx->simplified || ((bo & 0x10) && bi) ||
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(((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
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generic_bcctrx(ctx, bo, bi);
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generic_bclrx(ctx, bo, bi);
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return;
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}
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if ((bo & 0x14) == 0x14) {
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ctx->instr_str = my_sprintf("%-8s0x%08X", bcctrx_mnem[0]);
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ctx->instr_str = my_sprintf("%-8s0x%08X", bclrx_mnem[0]);
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return;
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}
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@ -664,20 +718,46 @@ void opc_group31(PPCDisasmContext* ctx)
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opc_idx_ldst[index], rs, ra, rb);
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return;
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break;
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case 0x1A: /* Byte sign extend instructions */
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if (index == 28)
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fmt_twoop(ctx->instr_str, "extsb", rs, ra);
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else if (index == 29)
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fmt_twoop(ctx->instr_str, "extsh", rs, ra);
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}
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auto ref_spr = (((ctx->instr_code >> 11) & 31) << 5) | ((ctx->instr_code >> 16) & 31);
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switch (ext_opc) {
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case 0: /* cmp */
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if (rc_set)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, r%d", "cmp", rs, ra, rb);
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break;
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case 4:
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if (rc_set)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "tw", rs, ra, rb);
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, r%d", "tw", rs, ra, rb);
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break;
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case 19: /* mfcr */
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fmt_oneop(ctx->instr_str, "mfcr", rs);
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break;
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case 26: /* cntlzw */
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strcpy_s(opcode, "cntlzw");
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_twoop(ctx->instr_str, opcode, rs, ra);
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break;
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case 64: /* cmpl */
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if (rc_set)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, r%d", "cmpl", rs, ra, rb);
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break;
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case 83: /* mfmsr */
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ctx->instr_str = my_sprintf("%-8s0x%02X, r%d", "mfmsr",
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(ctx->instr_code >> 21) & 0x1F);
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@ -696,9 +776,374 @@ void opc_group31(PPCDisasmContext* ctx)
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case 339: /* mfspr */
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fmt_twoop_fromspr(ctx->instr_str, "mfspr", rs, ref_spr);
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break;
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case 371: /* mftb */
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fmt_twoop_tospr(ctx->instr_str, "mftb", ref_spr, rs);
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break;
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case 467: /* mtspr */
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fmt_twoop_tospr(ctx->instr_str, "mtspr", ref_spr, rs);
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break;
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case 598: /* sync */
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ctx->instr_str = my_sprintf("%-8s", "sync");
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break;
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default:
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opc_illegal(ctx);
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}
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}
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void opc_group59(PPCDisasmContext* ctx)
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{
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char opcode[10] = "";
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auto rc = (ctx->instr_code >> 6) & 0x1F;
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auto rb = (ctx->instr_code >> 11) & 0x1F;
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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auto rs = (ctx->instr_code >> 21) & 0x1F;
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int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
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int index = ext_opc >> 5;
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bool rc_set = ctx->instr_code & 1;
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switch (ext_opc & 0x1F) {
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case 18: /* floating point division */
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strcpy_s(opcode, "fdivs");
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if (rc_set)
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strcat_s(opcode, ".");
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if (rc != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 20: /* floating point subtract */
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strcpy_s(opcode, "fsubs");
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if (rc_set)
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strcat_s(opcode, ".");
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if (rc != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 21: /* floating point addition */
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strcpy_s(opcode, "fadds");
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if (rc_set)
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strcat_s(opcode, ".");
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if (rc != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 22: /* floating point square root */
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strcpy_s(opcode, "fsqrts");
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if (rc_set)
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strcat_s(opcode, ".");
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if ((rc != 0) | (ra != 0))
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opc_illegal(ctx);
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else
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fmt_twoop_flt(ctx->instr_str, "fsqrts", rs, rb);
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return;
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case 24: /* fres */
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strcpy_s(opcode, "fres");
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if (rc_set)
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strcat_s(opcode, ".");
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if ((rc != 0) | (ra != 0))
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opc_illegal(ctx);
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else
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fmt_twoop_flt(ctx->instr_str, opcode, rs, rb);
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return;
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case 25: /* fmuls */
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strcpy_s(opcode, opc_flt_ext_arith[25]);
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strcat_s(opcode, "s");
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if (rc_set)
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strcat_s(opcode, ".");
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if (rb != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rc);
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return;
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case 28: /* fmsubs */
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strcpy_s(opcode, opc_flt_ext_arith[28]);
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strcat_s(opcode, "s");
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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case 29: /* fmadds */
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strcpy_s(opcode, opc_flt_ext_arith[29]);
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strcat_s(opcode, "s");
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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case 30: /* fnmsubs */
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strcpy_s(opcode, opc_flt_ext_arith[30]);
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strcat_s(opcode, "s");
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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case 31: /* fnmadds */
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strcpy_s(opcode, opc_flt_ext_arith[31]);
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strcat_s(opcode, "s");
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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}
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}
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void opc_group63(PPCDisasmContext* ctx)
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{
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char opcode[10] = "";
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auto rc = (ctx->instr_code >> 6) & 0x1F;
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auto rb = (ctx->instr_code >> 11) & 0x1F;
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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auto rs = (ctx->instr_code >> 21) & 0x1F;
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int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
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int index = ext_opc >> 5;
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bool rc_set = ctx->instr_code & 1;
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switch (ext_opc & 0x1F) {
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case 18: /* floating point division */
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strcpy_s(opcode, "fdiv");
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if (rc_set)
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strcat_s(opcode, ".");
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if (rc != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 20: /* floating point subtract */
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strcpy_s(opcode, "fsub");
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if (rc_set)
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strcat_s(opcode, ".");
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if (rc != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 21: /* floating point addition */
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strcpy_s(opcode, "fadd");
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if (rc_set)
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strcat_s(opcode, ".");
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if (rc != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 22: /* floating point square root */
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strcpy_s(opcode, "fsqrt");
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if (rc_set)
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strcat_s(opcode, ".");
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if ((rc != 0) | (ra != 0))
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 25: /* fmul */
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strcpy_s(opcode, opc_flt_ext_arith[25]);
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if (rc_set)
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strcat_s(opcode, ".");
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if (rb != 0)
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opc_illegal(ctx);
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else
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fmt_threeop_flt(ctx->instr_str, opcode, rs, ra, rc);
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return;
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case 26: /* frsqrte */
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strcpy_s(opcode, "frsqrte");
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if (rc_set)
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strcat_s(opcode, ".");
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if ((rc != 0) | (ra != 0))
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, fr%d, fr%d", opcode, rs, rb);
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return;
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case 28: /* fmsub */
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strcpy_s(opcode, opc_flt_ext_arith[28]);
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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case 29: /* fmadd */
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strcpy_s(opcode, opc_flt_ext_arith[29]);
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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case 30: /* fnmsub */
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strcpy_s(opcode, opc_flt_ext_arith[30]);
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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case 31: /* fnmadd */
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strcpy_s(opcode, opc_flt_ext_arith[31]);
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if (rc_set)
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strcat_s(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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return;
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}
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auto fm = (ctx->instr_code >> 17) & 0xFF;
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switch (ext_opc) {
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case 0: /* fcmpu */
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if (rs & 3)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, crf%d, r%d, r%d", "fcmpu", (rs >> 2), ra, rb);
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break;
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case 12: /* frsp */
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if (ra != 0)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "frsp", rs, rb);
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break;
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case 14: /* fctiw */
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if (ra != 0)
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opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "fctiw", rs, rb);
|
||||
break;
|
||||
case 15: /* fctiwz */
|
||||
if (ra != 0)
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "fctiwz", rs, rb);
|
||||
break;
|
||||
case 32: /* fcmpo */
|
||||
if (rs & 3)
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8s%d, crf%d, r%d, r%d", "fcmpu", (rs >> 2), ra, rb);
|
||||
break;
|
||||
case 40: /* fneg */
|
||||
strcpy_s(opcode, "fneg");
|
||||
|
||||
if (rc_set)
|
||||
strcat_s(opcode, ".");
|
||||
|
||||
if (ra != 0)
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8sr%d, r%d", opcode, rs, rb);
|
||||
break;
|
||||
case 72: /* fmr */
|
||||
if (ra != 0)
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8sr%d, r%d", "fmr", rs, rb);
|
||||
break;
|
||||
case 134: /* mtfsfi */
|
||||
if (ra != 0)
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8scrf%d, r%d", "mtfsfi", (rs >> 2), (rb >> 1));
|
||||
break;
|
||||
case 136: /* fnabs */
|
||||
if (ra != 0)
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8s%d, fr%d, fr%d", "fnabs", rs, rb);
|
||||
break;
|
||||
case 264: /* fabs */
|
||||
if (ra != 0)
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
ctx->instr_str = my_sprintf("%-8s%d, fr%d, fr%d", "fabs", rs, rb);
|
||||
break;
|
||||
case 467: /* mffs */
|
||||
if ((ra != 0) | (rb != 0))
|
||||
opc_illegal(ctx);
|
||||
else
|
||||
fmt_oneop(ctx->instr_str, "mffs", rs);
|
||||
break;
|
||||
case 711: /* mtfsf */
|
||||
ctx->instr_str = my_sprintf("%-8sfm%d, r%d", "mtfsf", fm, rb);
|
||||
break;
|
||||
default:
|
||||
opc_illegal(ctx);
|
||||
}
|
||||
@ -770,28 +1215,8 @@ static std::function<void(PPCDisasmContext*)> OpcodeDispatchTable[64] = {
|
||||
opc_intldst, opc_intldst, opc_intldst, opc_intldst,
|
||||
opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst,
|
||||
opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst,
|
||||
opc_illegal, opc_illegal, opc_illegal, opc_illegal,
|
||||
opc_illegal, opc_illegal, opc_illegal, opc_illegal
|
||||
|
||||
/*
|
||||
{15, &opc_addis}, {16, &opc_bcx}, {17, &opc_sc},
|
||||
{18, &opc_bx}, {19, &opc_opcode19}, {20, &opc_rlwimi},
|
||||
{21, &opc_rlwinm}, {22, &power_rlmi}, {23, &opc_rlwnm},
|
||||
{24, &opc_ori}, {25, &opc_oris}, {26, &opc_xori},
|
||||
{27, &opc_xoris}, {28, &opc_andidot}, {29, &opc_andisdot},
|
||||
{30, &opc_illegal}, {31, &opc_group31}, {32, &opc_lwz},
|
||||
{33, &opc_lwzu}, {34, &opc_lbz}, {35, &opc_lbzu},
|
||||
{36, &opc_stw}, {37, &opc_stwu}, {38, &opc_stb},
|
||||
{39, &opc_stbu}, {40, &opc_lhz}, {41, &opc_lhzu},
|
||||
{42, &opc_lha}, {43, &opc_lhau}, {44, &opc_sth},
|
||||
{45, &opc_sthu}, {46, &opc_lmw}, {47, &opc_stmw},
|
||||
{48, &opc_lfs}, {49, &opc_lfsu}, {50, &opc_lfd},
|
||||
{51, &opc_lfdu}, {52, &opc_stfs}, {53, &opc_stfsu},
|
||||
{54, &opc_stfd}, {55, &opc_stfdu}, {56, &opc_psq_l},
|
||||
{57, &opc_psq_lu}, {58, &opc_illegal}, {59, &opc_illegal},
|
||||
{60, &opc_psq_st}, {61, &opc_psq_stu}, {62, &opc_illegal},
|
||||
{63, &opc_opcode63}
|
||||
*/
|
||||
opc_illegal, opc_illegal, opc_illegal, opc_group59,
|
||||
opc_illegal, opc_illegal, opc_illegal, opc_group63
|
||||
};
|
||||
|
||||
string disassemble_single(PPCDisasmContext* ctx)
|
||||
|
||||
@ -29,7 +29,7 @@ void show_help()
|
||||
#ifdef PROFILER
|
||||
cout << " profiler -- show stats related to the processor" << endl;
|
||||
#endif
|
||||
cout << " disas X,n -- disassemble N instructions starting at address X" << endl;
|
||||
cout << " disas N,X -- disassemble N instructions starting at address X" << endl;
|
||||
cout << " quit -- quit the debugger" << endl << endl;
|
||||
cout << "Pressing ENTER will repeat last command." << endl;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user