Initial work on Rage 128
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dingusdev
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@ -1 +1,154 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <core/bitops.h>
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#include <core/timermanager.h>
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#include <devices/common/hwcomponent.h>
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#include <devices/common/pci/pcidevice.h>
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#include <devices/deviceregistry.h>
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#include <devices/video/atirage128.h>
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#include <devices/video/displayid.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <memaccess.h>
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#include <chrono>
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#include <cstdint>
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#include <map>
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#include <memory>
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/* Human readable ATI Rage 128 HW register names for easier debugging. */
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static const std::map<uint16_t, std::string> rage128_reg_names = {
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{0x0000, "ATI_MM_INDEX"}, {0x0004, "ATI_MM_DATA"},
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{0x0008, "ATI_CLOCK_CNTL_INDEX"}, {0x000C, "ATI_CLOCK_CNTL_DATA"},
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{0x0010, "ATI_BIOS_0_SCRATCH"}, {0x0014, "ATI_BIOS_1_SCRATCH"},
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{0x0018, "ATI_BIOS_2_SCRATCH"}, {0x001C, "ATI_BIOS_3_SCRATCH"},
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{0x0030, "ATI_BUS_CNTL"},
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{0x0034, "ATI_BUS_CNTL1"}, {0x0040, "ATI_GEN_INT_CNTL"},
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{0x0044, "ATI_GEN_INT_STATUS"}, {0x0050, "ATI_CRTC_GEN_CNTL"},
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{0x0054, "ATI_CRTC_EXT_CNTL"}, {0x0058, "ATI_DAC_CNTL"},
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{0x005C, "ATI_CRTC_STATUS"}, {0x0068, "ATI_GPIO_MONID"},
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{0x006C, "ATI_SEPROM_CNTL"}, {0x0094, "ATI_I2C_CNTL_1"},
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{0x00B0, "ATI_PALETTE_INDEX"}, {0x00B4, "ATI_PALETTE_DATA"},
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{0x00E0, "ATI_CONFIG_CNTL"}, {0x00F0, "ATI_GEN_RESET_CNTL"},
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{0x00F4, "ATI_GEN_STATUS"}, {0x00F8, "ATI_CNFG_MEMSIZE"},
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{0x0130, "ATI_HOST_PATH_CNTL"}, {0x0140, "ATI_MEM_CNTL"},
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{0x0144, "ATI_EXT_MEM_CNTL"}, {0x05D0, "ATI_GUI_STAT"},
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};
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ATIRage128::ATIRage128(uint16_t dev_id) : PCIDevice("ati-rage128"), VideoCtrlBase(640, 480) {
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uint8_t asic_id;
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supports_types(HWCompType::MMIO_DEV | HWCompType::PCI_DEV);
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this->vram_size = GET_INT_PROP("gfxmem_size") << 20; // convert MBs to bytes
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// allocate video RAM
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this->vram_ptr = std::unique_ptr<uint8_t[]>(new uint8_t[this->vram_size]);
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// ATI Rage driver needs to know ASIC ID (manufacturer's internal chip code)
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// to operate properly
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switch (dev_id) {
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case ATI_RAGE_128_PRO_DEV_ID:
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asic_id = 0x50;
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break;
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default:
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asic_id = 0xDD;
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LOG_F(WARNING, "ATI Rage 128: bogus ASIC ID assigned!");
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}
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// set up PCI configuration space header
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this->vendor_id = PCI_VENDOR_ATI;
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this->device_id = dev_id;
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this->subsys_vndr = PCI_VENDOR_ATI;
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this->subsys_id = 0x6987; // adapter ID
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this->class_rev = (0x030000 << 8) | asic_id;
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this->min_gnt = 8;
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this->irq_pin = 1;
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for (int i = 0; i < this->aperture_count; i++) {
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this->bars_cfg[i] = (uint32_t)(-this->aperture_size[i] | this->aperture_flag[i]);
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}
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this->finish_config_bars();
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//this->pci_notify_bar_change = [this](int bar_num) {
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// this->notify_bar_change(bar_num);
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//};
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// stuff default values into chip registers
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//this->regs[ATI_CONFIG_CHIP_ID] = (asic_id << 24) | dev_id;
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// initialize display identification
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this->disp_id = std::unique_ptr<DisplayID>(new DisplayID());
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//uint8_t mon_code = this->disp_id->read_monitor_sense(0, 0);
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//this->regs[ATI_GP_IO] = ((mon_code & 6) << 11) | ((mon_code & 1) << 8);
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}
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const char* ATIRage128::get_reg_name(uint32_t reg_offset) {
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auto iter = rage128_reg_names.find(reg_offset & ~3);
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if (iter != rage128_reg_names.end()) {
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return iter->second.c_str();
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} else {
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return "unknown Rage 128 register";
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}
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}
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void ATIRage128::change_one_bar(
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uint32_t& aperture, uint32_t aperture_size, uint32_t aperture_new, int bar_num) {
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if (aperture != aperture_new) {
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if (aperture)
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this->host_instance->pci_unregister_mmio_region(aperture, aperture_size, this);
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aperture = aperture_new;
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if (aperture)
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this->host_instance->pci_register_mmio_region(aperture, aperture_size, this);
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LOG_F(INFO, "%s: aperture[%d] set to 0x%08X", this->name.c_str(), bar_num, aperture);
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}
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}
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uint32_t ATIRage128::read_reg(uint32_t reg_offset, uint32_t size) {
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uint64_t result;
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uint32_t offset = reg_offset & 3;
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switch (reg_offset >> 2) {
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default:
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result = this->regs[reg_offset >> 2];
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}
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if (!offset && size == 4) { // fast path
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return result;
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} else { // slow path
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if ((offset + size) > 4) {
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result |= (uint64_t)(this->regs[(reg_offset >> 2) + 1]) << 32;
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}
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return extract_bits<uint64_t>(result, offset * 8, size * 8);
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}
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}
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uint32_t ATIRage128::pci_cfg_read(uint32_t reg_offs, AccessDetails& details) {
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if (reg_offs < 128) {
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return PCIDevice::pci_cfg_read(reg_offs, details);
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}
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LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER();
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return 0;
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}
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@ -0,0 +1,124 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef ATI_RAGE_H
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#define ATI_RAGE_H
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#include <devices/common/pci/pcidevice.h>
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#include <devices/video/atirage128defs.h>
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#include <devices/video/displayid.h>
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#include <devices/video/videoctrl.h>
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#include <cinttypes>
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#include <memory>
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/* Rage 128 PLL register indices. */
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enum {
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CLK_PIN_CNTL = 1,
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PPLL_CNTL = 2,
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PPLL_REF_DIV = 3,
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PPLL_DIV_0 = 4,
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PPLL_DIV_1 = 5,
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PPLL_DIV_2 = 6,
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PPLL_DIV_3 = 7,
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VCLK_ECP_CNTL = 8,
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HTOTAL_CNTL = 9,
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X_MPLL_REF_FB_DIV = 10,
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XPLL_CNTL = 11,
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XDLL_CNTL = 12,
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XCLK_CNTL = 13,
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MPLL_CNTL = 14,
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MCLK_CNTL = 15,
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FCP_CNTL = 18,
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PPLL_TEST_CNTL = 42,
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P2PLL_DIV_0 = 43,
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POWER_MGMT = 47
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};
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class ATIRage128 : public PCIDevice, public VideoCtrlBase {
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public:
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ATIRage128(uint16_t dev_id);
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~ATIRage128() = default;
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static std::unique_ptr<HWComponent> create_gl() {
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return std::unique_ptr<ATIRage128>(new ATIRage128(ATI_RAGE_128_GL_DEV_ID));
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}
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static std::unique_ptr<HWComponent> create_vr() {
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return std::unique_ptr<ATIRage128>(new ATIRage128(ATI_RAGE_128_VR_DEV_ID));
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}
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static std::unique_ptr<HWComponent> create_pro_128() {
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return std::unique_ptr<ATIRage128>(new ATIRage128(ATI_RAGE_128_PRO_DEV_ID));
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}
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// MMIODevice methods
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//uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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//void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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// PCI device methods
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uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails& details);
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//void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails& details);
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// I/O space access methods
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// bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res);
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//bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size);
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protected:
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//void notify_bar_change(int bar_num);
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const char* get_reg_name(uint32_t reg_offset);
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//bool io_access_allowed(uint32_t offset);
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uint32_t read_reg(uint32_t reg_offset, uint32_t size);
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//void write_reg(uint32_t reg_addr, uint32_t value, uint32_t size);
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//float calc_pll_freq(int scale, int fb_div);
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//void verbose_pixel_format(int crtc_index);
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//void crtc_update();
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//void crtc_enable();
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//void draw_hw_cursor(uint8_t* dst_buf, int dst_pitch);
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//void get_cursor_position(int& x, int& y);
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private:
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void change_one_bar(uint32_t& aperture, uint32_t aperture_size, uint32_t aperture_new, int bar_num);
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uint32_t regs[2048] = {}; // internal registers
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uint8_t cfg[128] = {}; // config registers
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uint8_t crt[100] = {}; // internal CRT registers
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uint8_t plls[32] = {}; // internal PLL registers
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// Video RAM variables
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std::unique_ptr<uint8_t[]> vram_ptr;
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uint32_t vram_size;
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uint32_t aperture_count = 3;
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uint32_t aperture_size[3] = {0x1000000, 0x100, 0x1000};
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uint32_t aperture_flag[3] = {0, 1, 0};
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uint32_t aperture_base = 0;
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uint32_t io_base = 0;
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uint8_t user_cfg = 8;
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std::unique_ptr<DisplayID> disp_id;
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// DAC interface state
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uint8_t dac_wr_index = 0; // current DAC color index for writing
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uint8_t dac_rd_index = 0; // current DAC color index for reading
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uint8_t dac_mask = 0; // current DAC mask
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int comp_index = 0; // current color component index
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uint8_t color_buf[3] = {}; // buffer for storing DAC color components
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};
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#endif // ATI_RAGE_H
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@ -0,0 +1,214 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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||||
(theweirdo) spatium
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||||
|
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef ATI_RAGE128_DEFS_H
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#define ATI_RAGE128_DEFS_H
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/* ATI PCI device IDs. */
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enum {
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ATI_RAGE_128_PRO_DEV_ID = 0x5046,
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ATI_RAGE_128_GL_DEV_ID = 0x5245,
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ATI_RAGE_128_VR_DEV_ID = 0x524B,
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};
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/** Rage 128 register offsets. */
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enum {
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// MMR registers
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ATI_MM_INDEX = 0x000, // 0x0000
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ATI_MM_DATA = 0x001, // 0x0004
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ATI_CLOCK_CNTL_INDEX = 0x002, // 0x0008
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ATI_CLOCK_CNTL_DATA = 0x003, // 0x000C
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ATI_BIOS_0_SCRATCH = 0x004, // 0x0010
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ATI_BIOS_1_SCRATCH = 0x005, // 0x0014
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ATI_BIOS_2_SCRATCH = 0x006, // 0x0018
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ATI_BIOS_3_SCRATCH = 0x007, // 0x001C
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ATI_BUS_CNTL = 0x00C, // 0x0030
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ATI_BUS_CNTL1 = 0x00D, // 0x0034
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ATI_GEN_INT_CNTL = 0x010, // 0x0040
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ATI_GEN_INT_STATUS = 0x011, // 0x0044
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ATI_CRTC_GEN_CNTL = 0x014, // 0x0050
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ATI_CRTC_EXT_CNTL = 0x015, // 0x0054
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ATI_DAC_CNTL = 0x016, // 0x0058
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ATI_CRTC_STATUS = 0x017, // 0x005C
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ATI_GPIO_MONID = 0x01A, // 0x0068
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ATI_SEPROM_CNTL = 0x01B, // 0x006C
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ATI_I2C_CNTL_1 = 0x025, // 0x0094
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ATI_PALETTE_INDEX = 0x02C, // 0x00B0
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ATI_PALETTE_DATA = 0x02D, // 0x00B4
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ATI_CONFIG_CNTL = 0x038, // 0x00E0
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ATI_CONFIG_XSTRAP = 0x039, // 0x00E4
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ATI_CONFIG_BONDS = 0x03A, // 0x00E8
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ATI_GEN_RESET_CNTL = 0x03C, // 0x00F0
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ATI_GEN_STATUS = 0x03D, // 0x00F4
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ATI_CNFG_MEMSIZE = 0x03E, // 0x00F8
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ATI_CONFIG_APER_0_BASE = 0x040, // 0x0100
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ATI_CONFIG_APER_1_BASE = 0x041, // 0x0104
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ATI_CONFIG_APER_SIZE = 0x042, // 0x0108
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ATI_CONFIG_REG_1_BASE = 0x043, // 0x010C
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ATI_CONFIG_REG_APER_SIZE = 0x044, // 0x0110
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ATI_TEST_DEBUG_CNTL = 0x048, // 0x0120
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ATI_TEST_DEBUG_MUX = 0x049, // 0x0124
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ATI_HW_DEBUG = 0x04A, // 0x0128
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ATI_HOST_PATH_CNTL = 0x04C, // 0x0130
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ATI_MEM_CNTL = 0x050, // 0x0140
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ATI_EXT_MEM_CNTL = 0x051, // 0x0144
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ATI_MEM_ADDR_CONFIG = 0x052, // 0x0148
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ATI_MEM_INTF_CNTL = 0x053, // 0x014C
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ATI_MEM_STR_CNTL = 0x054, // 0x0150
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ATI_VIPH_CONTROL = 0x074, // 0x01D0
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ATI_CRTC_H_TOTAL_DISP = 0x080, // 0x0200
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ATI_CRTC_H_SYNC_STRT_WID = 0x081, // 0x0204
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ATI_CRTC_V_TOTAL_DISP = 0x082, // 0x0208
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ATI_CRTC_V_SYNC_STRT_WID = 0x083, // 0x020C
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ATI_CRTC_VLINE_CRNT_VLINE = 0x084, // 0x0210
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ATI_CRTC_CRNT_FRAME = 0x085, // 0x0214
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ATI_CRTC_GUI_TRIG_VLINE = 0x086, // 0x0218
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ATI_CRTC_DEBUG = 0x087, // 0x021C
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ATI_CRTC_OFFSET = 0x089, // 0x0224
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ATI_CRTC_OFFSET_CNTL = 0x08A, // 0x0228
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ATI_CRTC_PITCH = 0x08B, // 0x022C
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ATI_OVR_CLR = 0x08C, // 0x0230
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ATI_OVR_WID_LEFT_RIGHT = 0x08D, // 0x0234
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ATI_OVR_WID_TOP_BOTTOM = 0x08E, // 0x0238
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ATI_SNAPSHOT_VH_COUNTS = 0x090, // 0x0240
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ATI_SNAPSHOT_F_COUNT = 0x091, // 0x0244
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ATI_N_VIF_COUNT = 0x092, // 0x0248
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ATI_SNAPSHOT_VIF_COUNT = 0x093, // 0x024C
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ATI_CUR_OFFSET = 0x098, // 0x0260
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ATI_CUR_HORZ_VERT_POSN = 0x099, // 0x0264
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ATI_CUR_HORZ_VERT_OFF = 0x09A, // 0x0268
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ATI_CUR_CLR0 = 0x09B, // 0x026C
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ATI_CUR_CLR1 = 0x09C, // 0x0270
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ATI_DAC_EXT_CNTL = 0x0A0, // 0x0280
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ATI_DAC_CRC_SIG = 0x0B3, // 0x02CC
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||||
ATI_PM4_BUFFER_DL_WPTR_DELAY = 0x1C6, // 0x0718
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ATI_DST_OFFSET = 0x501, // 0x1404
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||||
ATI_DST_PITCH = 0x502, // 0x1408
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ATI_DST_WIDTH = 0x503, // 0x140C
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ATI_DST_HEIGHT = 0x504, // 0x1410
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||||
ATI_SRC_X = 0x505, // 0x1414
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||||
ATI_SRC_Y = 0x506, // 0x1418
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ATI_DST_X = 0x507, // 0x141C
|
||||
ATI_DST_Y = 0x508, // 0x1420
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ATI_SRC_PITCH_OFFSET = 0x50A, // 0x1428
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||||
ATI_DST_PITCH_OFFSET = 0x50B, // 0x142C
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ATI_SRC_Y_X = 0x50D, // 0x1434
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||||
ATI_DST_Y_X = 0x50E, // 0x1438
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||||
ATI_DST_HEIGHT_WIDTH = 0x50F, // 0x143C
|
||||
ATI_DST_WIDTH_X = 0x562, // 0x1588
|
||||
ATI_DST_HEIGHT_WIDTH_8 = 0x563, // 0x158C
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||||
ATI_SRC_X_Y = 0x564, // 0x1590
|
||||
ATI_DST_X_Y = 0x565, // 0x1594
|
||||
ATI_DST_WIDTH_HEIGHT = 0x566, // 0x1598
|
||||
ATI_DST_WIDTH_X_INCY = 0x567, // 0x159C
|
||||
ATI_DST_HEIGHT_Y = 0x568, // 0x15A0
|
||||
ATI_DST_X_SUB = 0x569, // 0x15A4
|
||||
ATI_DST_Y_SUB = 0x56A, // 0x15A8
|
||||
ATI_SRC_OFFSET = 0x56B, // 0x15AC
|
||||
ATI_SRC_PITCH = 0x56C, // 0x15B0
|
||||
ATI_DST_WIDTH_BW = 0x56D, // 0x15B4
|
||||
ATI_GUI_SCRATCH_REG0 = 0x578, // 0x15E0
|
||||
ATI_GUI_SCRATCH_REG1 = 0x579, // 0x15E4
|
||||
ATI_GUI_SCRATCH_REG2 = 0x57A, // 0x15E8
|
||||
ATI_GUI_SCRATCH_REG3 = 0x57B, // 0x15EC
|
||||
ATI_GUI_SCRATCH_REG4 = 0x57C, // 0x15F0
|
||||
ATI_GUI_SCRATCH_REG5 = 0x57D, // 0x15F4
|
||||
ATI_DST_BRES_ERR = 0x58A, // 0x1628
|
||||
ATI_DST_BRES_INC = 0x58B, // 0x162C
|
||||
ATI_DST_BRES_DEC = 0x58C, // 0x1630
|
||||
ATI_DST_BRES_LNTH = 0x58D, // 0x1634
|
||||
ATI_DST_BRES_LNTH_SUB = 0x58E, // 0x1638
|
||||
ATI_SC_LEFT = 0x590, // 0x1640
|
||||
ATI_SC_RIGHT = 0x591, // 0x1644
|
||||
ATI_SC_TOP = 0x592, // 0x1648
|
||||
ATI_SC_BOTTOM = 0x593, // 0x164C
|
||||
ATI_SC_CNTL = 0x598, // 0x1660
|
||||
ATI_DEFAULT_OFFSET = 0x5B8, // 0x16E0
|
||||
ATI_DEFAULT_PITCH = 0x5B9, // 0x16E4
|
||||
ATI_DEFAULT_SC_BOTTOM_RIGHT = 0x5BA, // 0x16E8
|
||||
ATI_SC_TOP_LEFT = 0x5BB, // 0x16EC
|
||||
ATI_SC_BOTTOM_RIGHT = 0x5BC, // 0x16F0
|
||||
ATI_SRC_SC_BOTTOM_RIGHT = 0x5BD, // 0x16F4
|
||||
ATI_WAIT_UNTIL = 0x5C8, // 0x1720
|
||||
ATI_GUI_STAT = 0x5D0, // 0x1740
|
||||
ATI_HOST_DATA0 = 0x5F0, // 0x17C0
|
||||
ATI_HOST_DATA1 = 0x5F1, // 0x17C4
|
||||
ATI_HOST_DATA2 = 0x5F2, // 0x17C8
|
||||
ATI_HOST_DATA3 = 0x5F3, // 0x17CC
|
||||
ATI_HOST_DATA4 = 0x5F4, // 0x17D0
|
||||
ATI_HOST_DATA5 = 0x5F5, // 0x17D4
|
||||
ATI_HOST_DATA6 = 0x5F6, // 0x17D8
|
||||
ATI_HOST_DATA7 = 0x5F7, // 0x17DC
|
||||
ATI_HOST_DATA_LAST = 0x5F8, // 0x17E0
|
||||
ATI_W_START = 0x633, // 0x18CC
|
||||
ATI_CONSTANT_COLOR = 0x68C, // 0x1A30
|
||||
ATI_Z_VIS = 0x6B4, // 0x1AD4
|
||||
ATI_WINDOW_XY_OFFSET = 0x6F3, // 0x1BCC
|
||||
ATI_DRAW_LINE_POINT = 0x6F4, // 0x1BD0
|
||||
ATI_DST_PITCH_OFFSET_C = 0x720, // 0x1C80
|
||||
ATI_SC_TOP_LEFT_C = 0x722, // 0x1C88
|
||||
|
||||
// CFG registers
|
||||
|
||||
ATI_VENDOR_ID = 0x000,
|
||||
ATI_DEVICE_ID = 0x002,
|
||||
ATI_COMMAND = 0x004,
|
||||
ATI_STATUS = 0x006,
|
||||
ATI_REVISION_ID = 0x008,
|
||||
ATI_REGPROG_INF = 0x009,
|
||||
ATI_SUB_CLASS = 0x00A,
|
||||
ATI_BASE_CODE = 0x00B,
|
||||
ATI_CACHE_LINE = 0x00C,
|
||||
ATI_LATENCY = 0x00D,
|
||||
ATI_HEADER = 0x00E,
|
||||
ATI_BIST = 0x00F,
|
||||
ATI_MEM_BASE = 0x010,
|
||||
ATI_IO_BASE = 0x014,
|
||||
ATI_REG_BASE = 0x018,
|
||||
ATI_ADAPTER_ID = 0x02C,
|
||||
ATI_BIOS_ROM = 0x030,
|
||||
ATI_CAPABILITES_PTR = 0x034,
|
||||
ATI_INTERRUPT_LINE = 0x03C,
|
||||
ATI_INTERRUPT_PIN = 0x03D,
|
||||
ATI_MIN_GRANT = 0x03E,
|
||||
ATI_MAX_LATENCY = 0x03F,
|
||||
ATI_ADAPTER_ID_W = 0x04C,
|
||||
ATI_CAPABILITIES_ID = 0x050,
|
||||
|
||||
// byte offsets for the built-in DAC registers
|
||||
ATI_DAC_W_INDEX = 0x00C0,
|
||||
ATI_DAC_DATA = 0x00C1,
|
||||
ATI_DAC_MASK = 0x00C2,
|
||||
ATI_DAC_R_INDEX = 0x00C3,
|
||||
|
||||
ATI_INVALID = 0xFFFF
|
||||
};
|
||||
|
||||
constexpr auto APERTURE_SIZE = 0x02000000UL; // Rage 128 aperture size
|
||||
constexpr auto MM_REGS_0_OFF = 0x007FFC00UL; // offset to memory mapped registers, block 0
|
||||
constexpr auto MM_REGS_1_OFF = 0x007FF800UL; // offset to memory mapped registers, block 1
|
||||
constexpr auto MM_REGS_2_OFF = 0x003FFC00UL; // offset to memory mapped registers, 4MB aperture
|
||||
constexpr auto BE_FB_OFFSET = 0x01000000UL; // Offset to the big-endian frame buffer
|
||||
|
||||
constexpr auto ATI_XTAL = 14318180.0f; // external crystal oscillator frequency
|
||||
|
||||
#endif // ATI_RAGE128_DEFS_H
|
||||
Loading…
Reference in New Issue