Allow the dbdma program to initiate reading/writing by adding in and out callbacks.
Support the DBDMA flush command by adding a flush callback. If the transfer completes, then clear the flush flag, otherwise leave it unchanged.
Clear the flush flag after it is copied to the xferStatus of the DBDMA command.
Switching from Watch to Arrow cursor at vertical position zero (top of the screen) would sometimes cut off the top half of the Arrow cursor. The following changes fix this:
Use the new cursor_dirty flag to signal when the cursor should be updated. This reduces the number of cursor updates and doesn't depend on registers being accessed in a specific order.
Set the cursor_dirty flag for any change that should cause the hardware cursor to be updated:
- CUR_CLR0, CUR_CLR1: Cursor color changes. We don't check if the colors actually changed (all cursors are usually black and white). Rather, writes to these registers usually means the cursor bytes have changed or will change.
- CUR_OFFSET: Offset to cursor bytes.
- CUR_VERT_OFF: First vertical line of cursor to draw.
Other changes that don't require the cursor to be updated:
- CUR_HORZ_OFF: Horizontal offset of cursor position. The cursor is unchanged - just need to adjust the drawing position.
- CUR_HORZ_VERT_POSN: The cursor is unchanged - only the drawing position is changed.
The only thing that could change the cursor that we don't check is a change to the cursor bytes.
Sense codes for displays like the 12 inch RGB display (512x384) weren't working since they had the extended part set to 0xff.
Related to issues #25.
Also added some descriptive information and sizes which may be used for UI purposes such as creating a menu of displays to choose from. The sizes may be used to set the default window size for the display.
This commit fixes conflict resolution mistakes in the following commits:
"atimach64gx: Let crtc_update calculate fb_ptr."
"atimach64gx: Redraw only when necessary."
"atimach64gx: Log unhandled overlay registers." was mistakenly included in "atimach64gx: Let crtc_update calculate fb_ptr.". The OVR_ registers were included because they may be needed for 2D acceleration in System 7.5.3 and later.
Init them to defaults.
Make CONFIG_CNTL 8 bytes so unaligned read/write is easier.
Write changes to CONFIG_CNTL even if offset + size is > 4.
Log aperture change only if first byte (LSB) of CONFIG_CNTL is written. The driver might only write to the 2 most significant bytes which won't affect aperture size.
Offset and size are applied to the destination, not to source value, so we shouldn't use extract_bits when logging value.
Use ATI bitfield enums in switch statement.
The first packet the one sec mode should send is a mode 1 real time packet, same as GET_REAL_TIME.
A mode 2 packet is the same but doesn't include the time.
They are incomplete or unused (includes cmd and count but not the data and the count isn't used). Might as well get everything from the class fields in_buf and in_count.
GET_REAL_TIME was using the wrong offset and wasn't setting out_count.
May need to add time zone offset which could be different between host and guest.
get-time and set-time can be tested in Open Firmware.
SET_REAL_TIME is used by the Date/Time Control Panel when you change the date.
It is unknown what method Mac OS uses to get the time at boot. Mac OS 8.6 does not use GET_REAL_TIME during boot, so the time is left as 12:00 AM Jan 1, 1904.
Last step of CMD_COMPLETE_STEPS includes INTSTAT_SO to indicate to CurioSCSIController::fsmCompleting that it returned both a status byte and a message byte in the FIFO.
- For pdm/amic, real_dma_xfer is called when SCSI_DMA_Ctrl has the run bit set.
- For tnt/grandcentral, dma_wait is called when the DBDMA is started (run bit is set). It will call real_dma_xfer when the phase and sequence are DATA_IN/RCV_DATA or DATA_OUT/SEND_DATA.
- dma_wait and real_dma_xfer uses a one shot timer instead of a loop to continue doing DMA while also giving time to the CPU. This and the above changes handles the case where the DBDMA is started before setting up the transfer phase and sequence.
- dma_stop will stop the one shot timer when the DBDMA channel is stopped.
Allow VRAM presence only in optional bank.
control: Implement banks.
The BAR is 64MB.
The little-endian/big-endian ranges repeat every 16MB.
An endian range can be addressed in d128 (wide) mode or d64 mode.
In d128 mode, there is a 4MB range followed by an undefined 4MB range. bytes 0..7 belong to the standard bank and bytes 8..15 belong to the optional bank.
In d64 mode:
- 2MB mirror ranges at 0MB and 2MB (both have the same read/write behavor: write to both banks or read from the standard bank.
- 2MB standard bank rage at 4MB.
- 2MB optional bank range at 6MB.
