12 Commits

Author	SHA1	Message	Date
Maxim Poliakovski	5668fc161f	macio: fix SWIM3 register space accesses.	2022-06-13 23:15:48 +02:00
Maxim Poliakovski	d4c08bbe31	Fix ESCC register addressing.	2022-05-07 21:47:22 +02:00
Maxim Poliakovski	4d87ed9b38	Make NVRAM a full-fledged HW component.	2022-03-29 01:55:11 +02:00
Maxim Poliakovski	276cd37cfe	Heathrow: interrupt registers & mode 1 interrupts.	2022-03-14 18:13:47 +01:00
Maxim Poliakovski	4c45b3dfa2	Heathrow: use common PCI configuration code.	2022-03-14 18:13:47 +01:00
Maxim Poliakovski	c946693450	escc: unify compatible and MacRISC addressing.	2022-02-26 10:57:13 +01:00
Maxim Poliakovski	5c177cc50f	Simplify registration of HW component types.	2022-01-26 16:45:21 +01:00
Maxim Poliakovski	9a0c340712	Basic SWIM3 and Superdrive emulation.	2021-12-12 21:40:04 +01:00
Maxim Poliakovski	fc44cdcc83	Heathrow: logging monitor sense status.	2021-11-09 13:41:48 +01:00
Maxim Poliakovski	87b8e1759a	Connect ESCC to AMIC and Heathrow.	2021-10-25 22:19:45 +02:00
Maxim Poliakovski	3f20d0a700	heathrow: use unique_ptr with internal objects.	2021-10-25 22:19:45 +02:00
Maxim Poliakovski	9329d56d83	Move devices into dedicated subdirectories.	2021-10-23 20:17:47 +02:00