Commit Graph

140 Commits

Author SHA1 Message Date
Mihai Parparita
b759f25d87 ppc: Use a unified opcode lookup table
Instead of a primary opcode lookup table with 64 entries and a few
smaller tables with 4-2048 entries, use a single 64 * 2048 (128K)
entry table to dispatch opcodes.

Helps with performance, since we avoid the function call overhead for
some frequently-used instructions (e.g. branch, integer, floating point).
Saves ~2 seconds from the time to Welcome to Macintosh (same measurement
methodology as #125)

Secondarily also makes opcode registration/decoding a bit more uniform,
and scannable, since it's now all in initialize_ppc_opcode_table.
2024-11-30 20:37:26 +01:00
Mihai Parparita
564c43c907 Remove ppc_cur_instruction global variable
Replace it wth an explicit opcode parameter that is passed around. That
is both slightly easier to reason about (to trace where it comes from)
and slightly faster, since it can be read from a register.

On my machine takes booting to "Welcome to Macintosh" being output in
a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5
runs, measured using deterministic mode and looking at when execution
reaches PC 0x90004a88).
2024-11-28 23:41:38 +01:00
Mihai Parparita
2d90aff408 ppc: Remove unncesessary function declarations
ppc_opcode16 and other functions are only needed in the implementation in
ppcexec.cpp, they don't need to be in the header.

fp_return_double and fp_return_uint64 have no uses (as of 2141a72b87)
can can thus be removed altogether.

Similarly ppc_fpu_off has no uses (as of bb3f4e596e)
and can be removed.
2024-11-28 22:12:16 +01:00
joevt
b38b1731a0 ppcopcodes: Don't change MQ if not MPC601.
MQ should not be writable if not doing MPC601.
Fix is_601 and include_601.
This fixes risu tests.
2024-11-27 07:59:19 -07:00
Mihai Parparita
f65f9b9845 Add a deterministic execution mode
Adds support for a --deterministic command-line option that makes
repeated runs the same:
- Keyboard and mouse input is ignored
- The sound server does a periodic pull from the DMA channel (so that
  it gets drained), but only does so via a periodic timer (instead of
  being driven by a cubeb callback, which could arrive at different
  times)
- Disk image writes are disabled (reads of a modified area still
  work via an in-memory copy)
- NVRAM writes are disabled
- The current time that ViaCuda initializes the guest OS is always the
  same.

This makes execution exactly the same each time, which should
make debugging of more subtle issues easier.

To validate that the deterministic mode is working, I've added a
periodic log of the current "time" (measured in cycle count), PC
and opcode. When comparing two runs with --log-no-uptime, the generated
log files are identical.
2024-11-09 22:48:06 -08:00
dingusdev
01ceaef8d7 Slightly delaying a race condition 2024-09-24 21:10:10 -07:00
joevt
78da2457e8 ppcexec: Simplify next event time calculation. 2024-09-02 19:00:33 -07:00
joevt
7e70432495 ppcexec: Remove unused g_icycles_base. 2024-09-02 18:58:07 -07:00
dingusdev
b5850f1cd2 Slight clean-up to ppcexec 2024-08-26 06:48:40 -07:00
Mihai Parparita
bdbeb742d4 ppc: remove two unused global variables
Last use of grab_return was removed in f204caa907.
grab_breakpoint was added in 2bd717e293 but
never used.
2024-08-18 22:46:52 -07:00
Mihai Parparita
e7d8e71297 ppc: make ppc_effective_address into a local
There's no reason for it to be a global, we always set it and use it
in instruction implementations, and we never read it directly.

Perhaps the compiler could optimize this away, but it's better to be
simpler (and also be easier to read).
2024-08-18 22:38:50 -07:00
dingusdev
17cdcc5560 Fixes issue #97 2024-06-30 06:53:44 -07:00
Mihai Parparita
50018010c7 Add instruction counters to CPU profiler
Keeps track of instructions (including operands) that are executed,
to see if there are any hotspots that could be optimized or fastpaths
that should be added.

Also adds a mode where CPU profiler data is periodically output, to
make it easier to get at these instruction counts during startup.
2024-06-14 19:55:42 +02:00
joevt
5022ac89b4 ppcexec: Improve realtime. 2024-04-21 07:16:47 -07:00
joevt
cb88bab67d ppcopcodes: Fixes for SPRs.
- Rename DEC to DEC_S and add DEC_U.
- MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction.
- For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601.
- For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC.
- For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
2024-04-10 07:21:54 -07:00
joevt
4f45d7de35 cpu: Add cpu options to ppc_cpu_init.
The first option is a flag that enables MPC601 (POWER) instructions for CPUs that are not MPC601.
This can be useful for the following reasons:
1) To produce results similar to classic Mac OS which emulates MPC601 instructions on CPUs that don't implement MPC601 instructions. This option is used to compare the risu traces produced in Mac OS 9 on a G3 or G4 with DPPC.
2) May increase performance in apps that use POWER instructions on emulated machines with CPUs that are not MPC601. It is not known if any such apps exist but there could be since Apple included MPC601 emulation in classic Mac OS.
2024-04-10 06:43:18 -07:00
joevt
3c16870f86 ppcmmu: Replace defines.
They may interfere with system headers.
2024-04-09 07:57:48 -07:00
Maxim Poliakovski
524daa45a5 ppcexec.cpp: fix compilation with Apple Clang 10. 2024-04-07 20:39:24 +02:00
dingusdev
43d87b4791 Temp revert for icnt_factor
We should, at minimum, make icnt_factor adjustable. That said, powermax is suggesting we develop a more sophisticated scheduler.
2024-03-31 14:13:45 -07:00
joevt
6267685920 ppcexec: Make EXEF_TIMER separate variable. 2024-03-31 12:15:48 -07:00
joevt
48882f3fec ppcexec: Adjust icnt_factor.
So that 1000 ms takes ≈ 1 second in Open Firmware on 4 GHz Intel CPU.
2024-03-31 11:51:04 -07:00
joevt
0ac54ea1ea ppcexec: Add host time option. 2024-03-31 11:50:55 -07:00
joevt
58ed5bb56e ppcexec: Opcode initialization to one function.
Move all opcode initialization to initialize_ppc_opcode_tables.
Some opcodes are illegal for some processors.
2024-03-28 07:35:57 -07:00
joevt
60a76e9348 ppcexec: Fix branch check in ppc_exec_single. 2024-03-28 07:17:13 -07:00
joevt
5b4ed01bec ppcexec: Make separate enum for shift instructions. 2024-03-27 18:43:46 -07:00
joevt
64df253053 ppcexec: Rename bool function enums.
Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
joevt
d8129bd643 ppcexec: Add comments for macros. 2024-03-27 18:43:15 -07:00
Maxim Poliakovski
6aa54b8dda ppcexec: break long lines, improve indentation. 2024-03-27 13:55:05 +01:00
dingusdev
ec56dffd19 Adding missing includes 2024-03-26 19:25:05 -07:00
dingusdev
a09f2093b5 Optimize register initialization
Courtesy of joevt, adapted to fit the C++ standard
2024-03-26 18:52:56 -07:00
dingusdev
b15d3be88a Moving is_601 up, so the opcodes get initialized correctly 2024-03-26 18:41:16 -07:00
joevt
224ae50e91 ppcexec: Make more instructions illegal for 601. 2024-03-26 06:50:33 -07:00
joevt
03d7728d46 ppcexec: Use macros to assign subopcode functions. 2024-03-26 06:50:17 -07:00
joevt
19ba15f2f1 ppc: Separate enums for separate fields. 2024-03-26 06:44:26 -07:00
dingusdev
9b76c9fe3e Fix for mffs in opcode table 2024-03-25 20:04:13 -07:00
joevt
f08d9ba81e ppcexec: Fix templated lhzux. 2024-03-25 07:43:34 -07:00
joevt
effe0198ce ppcexec: Fix bcctr templated parameters. 2024-03-25 07:36:46 -07:00
dingusdev
c781820bf6 Continued table fixes 2024-03-24 17:43:14 -07:00
dingusdev
30802affd4 Continued fixes for tables 2024-03-24 17:24:36 -07:00
dingusdev
5631485465 Cleaning up templating 2024-03-24 14:06:07 -07:00
dingusdev
c281b27220 Attempted templating for interpreter 2024-03-24 12:21:19 -07:00
joevt
1d5502dc3c ppcemu: Make flags atomic.
For flags that might be accessed by other threads.
2024-03-22 19:04:51 -07:00
joevt
833f74dce6 timemanager: Remove unnecessary parameter. 2024-03-16 11:36:41 -07:00
dingusdev
daeecbe99e Clean-up bc and bcl
Using templating to make the code a touch more readable
2024-03-08 19:22:25 -07:00
dingusdev
eb07a3c2f1 Templating bclr to match with bcctr 2024-03-07 20:44:36 -07:00
joevt
67bd47f11f ppcopcodes: Fixes for bcctr(l)?.
Add MPC601 variants. Variants that decrement and test the ctr are invalid bon't don't appear to trigger an exception. The manual says MPC601 can decrement the counter. Other CPUs do not decrement the counter but will branch based on the value.
2024-03-07 06:55:54 -07:00
joevt
e44676e491 ppcfpopcodes: Template mffs variants. 2024-03-07 06:45:46 -07:00
Maxim Poliakovski
30c6cbefbd ppcexec: fix indentation, break long lines. 2024-03-06 23:28:40 +01:00
joevt
20b4a33c00 ppcexec: Remove EXHAUSTIVE_DEBUG. 2024-03-05 07:05:03 -07:00
joevt
f61055ebc0 ppcexec: Convert if to switch for ppc_opcode19. 2024-03-05 07:03:16 -07:00