===============
Rairii changes:
memctrlbase: The memory controller may have an endian swap mode.
mpc106: Only mmio regions need endian swap and only if PCIR_LE_MODE is
set.
videoctrl: Add framebuffer_in_main_memory flag. Use needs_swap_endian.
debugger: Fix disasm for little endian mode.
ppcmmu: little endian mode requires munging of the data and instruction
addresses, affecting the 3 least significant bits.
ppcexec: pc_real is always recalculated during little endian mode
because instructions are swapped every 8 bytes (due to the address
munging).
==============
joevt changes:
Add SUPPORTS_MEMORY_CTRL_ENDIAN_MODE for memory controller.
Use cmake -DDPPC_SUPPORT_PPC_LE=ON to enable.
Add SUPPORTS_PPC_LITTLE_ENDIAN_MODE for CPU.
Use cmake -DDPPC_SUPPORT_MEM_LE=ON to enable.
Add ppc_change_endian to handle endian switch for MPC601 (uses HID0
instead of MSR) and later PPC CPUs.
Add is_LE flag to ppc_state to indicate little endian mode for all
processor versions.
Create separate ppc_exec_inner template functions for little and big
endian.
Switch endian mode in the ppc_exec outer functions when power_off_reason
is po_endian_switch.
Since MPC601 doesn't have ILE and LE bits, remove that code for that
CPU.
videoctrl: Uses templated methods. See next commit for a fix that this
change introduces.
Previously, only the total size of all DIMMs was used. For example, four
8 MB DIMMs would behave as a single 32 MB DIMM.
This change forces handling of the individual DIMM sizes.
We currently do not emulate shuffling of 4MB pages. For example, the
data of the first page of bank 1 does not move if you move it to a
different page.
The important parts of this algorithm are:
1) DIMM sizes can be determined.
2) The final memory allocation will be a single contiguous block.
Add supports_types to device descriptors so that we can determine
supported types without having to create the hardware device.
Add description so that each device can have an optional description.
joevt
Maxim Poliakovski
Rairii
dingusdev
Paper
