Macintosh-Tools/dingusppc
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1,751 Commits 30 Branches 2 Tags 8.4 MiB
ffa221192d
Commit Graph

890 Commits

Author SHA1 Message Date
Maxim Poliakovski
ffa221192d athens: use component's name in logging messages. 2024-04-15 14:21:08 +02:00
Maxim Poliakovski
751f964139 athens: clean up initialization. 2024-04-15 14:21:08 +02:00
joevt
14f75d834a macio: Add list of OHare/Heathrow bits. 2024-04-12 19:54:34 -07:00
Maxim Poliakovski
96efc99a00 control: clean up register bit definitions. 2024-04-11 17:50:50 +02:00
Maxim Poliakovski
45d2c8854d Revert "macio: Add fatman bits register." 
This reverts commit 8aaf211c5b.
 2024-04-11 17:18:20 +02:00
Maxim Poliakovski
c22843f238 appleramdac: vendor ID for AT&T fabbed RAMDACs. 2024-04-11 17:10:44 +02:00
joevt
1c5009fcb0 amic: Add more registers. 2024-04-10 20:59:34 -07:00
joevt
bd63d1dcda platinum: Validity check before enable display. 2024-04-10 20:56:51 -07:00
joevt
8aaf211c5b macio: Add fatman bits register. 
This register is used in the control ndrv to detect presence of connected S-Video or composite video display.
 2024-04-10 20:48:29 -07:00
joevt
8cc5838efe control: More register bits. 2024-04-10 20:48:12 -07:00
joevt
be27ceed00 machinetnt: Remove sixty6 and mesh properties. 
Use the presence of the devices in the MachineDescription to determine these.
 2024-04-10 20:19:43 -07:00
joevt
1d75730d44 dbdma: Do interrupt on main thread. 
These may be triggered by other threads (such as for audio) so use the timer manager to handle them in the main thread.
 2024-04-10 19:17:49 -07:00
joevt
95d74a6940 scsihd: Check Lun for INQUIRY. 
INQUIRY now returns 0x7f for device type if LUN doesn't match. INQUIRY can get LUN from CDB or from IDENTIFY message.
 2024-04-10 19:02:01 -07:00
joevt
c6ea3a374e control: Fix PAL/NTSC interlaced display. 2024-04-10 07:32:35 -07:00
Maxim Poliakovski
1c8702d67a Add missing credits. 2024-04-09 01:51:51 +02:00
Mihai Parparita
cf4913deb0 bandit: Fix regression in non-Aspen PCI bridge 
Refactor from e7da98b6bd accidentally
made the non-Aspen PCI code path for CONFIG_ADDR writes by a no-op.
 2024-04-08 15:41:19 -05:00
Maxim Poliakovski
4c9fe06229 Implement Aspen memory controller. 2024-04-08 00:44:24 +02:00
Maxim Poliakovski
e7da98b6bd bandit: implement Aspen style PCI bridge. 2024-04-08 00:44:24 +02:00
Maxim Poliakovski
dcdfaabedf dbdma: skip transfer commands with reqCount=0. 2024-04-07 20:39:24 +02:00
Maxim Poliakovski
073b8fd981 atimach64defs: add ATI_DP_CHAIN_MSK register definition. 2024-04-07 18:48:52 +02:00
Maxim Poliakovski
d7749e0a2c awacs: small cosmetic improvements. 2024-04-07 18:48:52 +02:00
Maxim Poliakovski
7972a0f2a8 hammerhead: use instance name in logging messages. 2024-04-07 18:48:52 +02:00
Maxim Poliakovski
19dcb43658 pcibase.h: remove superfluous spaces. 2024-04-07 18:48:52 +02:00
joevt
d0a5a1e7be Add ability to override built-in GPU. 2024-04-04 19:04:06 -07:00
joevt
077e6ebae5 machineid: Don't decode board register address. 
All addresses return the same value. Converted for Board Register 1 and Board Register 66.
 2024-04-03 19:53:03 -07:00
joevt
abe0c14301 scsibus: push_data of zero bytes is ok. 
It just means the data hasn't been put on the fifo yet.
 2024-04-03 19:51:50 -07:00
joevt
61576d4032 sc53c94: Check drq_cb. 2024-04-03 19:35:58 -07:00
joevt
782a8d2c3c sc53c94: CMD_COMPLETE_STEPS includes INTSTAT_SO. 
Last step of CMD_COMPLETE_STEPS includes INTSTAT_SO to indicate to CurioSCSIController::fsmCompleting that it returned both a status byte and a message byte in the FIFO.
 2024-04-03 19:35:27 -07:00
joevt
e619dd2493 sc53c94: CMD_COMPLETE and XFER_END goes to IDLE. 
CMD_COMPLETE and XFER_END goes to the IDLE sequence state so that reentry doesn't cause a second interrupt.
 2024-04-03 19:35:13 -07:00
joevt
8a1055ed1b sc53c94: Add DBDMA support. 
- For pdm/amic, real_dma_xfer is called when SCSI_DMA_Ctrl has the run bit set.
- For tnt/grandcentral, dma_wait is called when the DBDMA is started (run bit is set). It will call real_dma_xfer when the phase and sequence are DATA_IN/RCV_DATA or DATA_OUT/SEND_DATA.
- dma_wait and real_dma_xfer uses a one shot timer instead of a loop to continue doing DMA while also giving time to the CPU. This and the above changes handles the case where the DBDMA is started before setting up the transfer phase and sequence.
- dma_stop will stop the one shot timer when the DBDMA channel is stopped.
 2024-04-03 19:19:42 -07:00
joevt
ff766b10eb sc53c94: Add seq_id to sequence descriptor. 
The seq_id can be used for logging the current command and step number.
 2024-04-03 18:43:46 -07:00
joevt
ceb2276098 sc53c94: Move chip_id to xfer_count. 
Method for reading chip_id needs verification.
 2024-04-03 18:43:40 -07:00
joevt
82f4d05f4b sc53c94: Set timer_id to zero. 
If a timer is not in progress then set its timer_id to zero. Also, don't start a newer timer if an existing one is still in progress.
 2024-04-03 18:36:53 -07:00
joevt
8a81cb4f9c sc53c94: Use enums. 2024-04-03 18:12:00 -07:00
joevt
1504bd2227 sc53c94: Move DATA_FIFO_MAX from header. 
Headers shouldn't make defines that are not meant to be used outside the source file.
 2024-04-03 18:11:07 -07:00
dingusdev
475f894582 Comment out log message 2024-04-02 19:21:56 -07:00
joevt
7007e002e6 macio: Make interrupt flags atomic. 
So they can be modified by other threads.
 2024-04-02 19:05:57 -07:00
joevt
9af1b1a720 control: Narrow the scope of local variable. 2024-04-01 22:12:20 -07:00
joevt
ca9657baf1 control: Update little-endian error message. 2024-04-01 22:12:05 -07:00
joevt
3e347746f9 control: Don't abort when setting little endian. 
If this gets set accidentally, (such as while playing in Open Firmware), allow the user to change it back.
 2024-04-01 22:11:35 -07:00
joevt
b5987afaa6 control: Implement BAR update. 2024-04-01 22:11:30 -07:00
joevt
ea46d08835 appleramdac: Allow read from CLUT part 2. 2024-04-01 21:47:59 -07:00
joevt
789114cc7d control: Save CNT_TST and MON_SENSE. 
These are writable registers that should return what was written to them.
 2024-04-01 21:34:26 -07:00
joevt
cf292fafcb control: vram changes. 
Allow VRAM presence only in optional bank.

control: Implement banks.

The BAR is 64MB.
The little-endian/big-endian ranges repeat every 16MB.
An endian range can be addressed in d128 (wide) mode or d64 mode.
In d128 mode, there is a 4MB range followed by an undefined 4MB range. bytes 0..7 belong to the standard bank and bytes 8..15 belong to the optional bank.
In d64 mode:
- 2MB mirror ranges at 0MB and 2MB (both have the same read/write behavor: write to both banks or read from the standard bank.
- 2MB standard bank rage at 4MB.
- 2MB optional bank range at 6MB.
 2024-04-01 21:17:17 -07:00
joevt
08fca7de69 control: Recalc framebuffer after each change. 2024-04-01 20:58:46 -07:00
joevt
b42437c458 control: Mask unmodifiable bits. 2024-04-01 19:01:03 -07:00
joevt
98e1787f93 machines: Remove duplicate gfxmem_size properties. 2024-04-01 18:28:13 -07:00
dingusdev
55b9f8bbe5 bzero -> memset 2024-04-01 08:03:12 -07:00
joevt
2968645f2e scsihd: Allow INQUIRY allocation length != 36. 
Truncate for < 36 and zero fill for > 36.
 2024-04-01 08:02:17 -07:00
joevt
92dea0e404 scsihd: Include invalid field info. 
For CHECK_CONDITION status from READ_CAPACITY_10.
 2024-04-01 08:01:09 -07:00