mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-06-02 05:41:39 +00:00
cb88bab67d
- Rename DEC to DEC_S and add DEC_U. - MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction. - For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601. - For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC. - For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
661 lines
18 KiB
C++
661 lines
18 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PPCEMU_H
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#define PPCEMU_H
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#include <devices/memctrl/memctrlbase.h>
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#include <endianswap.h>
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#include <memaccess.h>
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#include <atomic>
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#include <cinttypes>
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#include <functional>
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#include <setjmp.h>
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#include <string>
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// Uncomment this to have a more graceful approach to illegal opcodes
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//#define ILLEGAL_OP_SAFE 1
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//#define CPU_PROFILING // enable CPU profiling
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/** type of compiler used during execution */
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enum EXEC_MODE:uint32_t {
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interpreter = 0,
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debugger = 1,
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threaded_int = 2,
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jit = 3
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};
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enum endian_switch { big_end = 0, little_end = 1 };
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typedef void (*PPCOpcode)(void);
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union FPR_storage {
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double dbl64_r; // double floating-point representation
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uint64_t int64_r; // double integer representation
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};
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/**
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Except for the floating-point registers, all registers require
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32 bits for representation. Floating-point registers need 64 bits.
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gpr = General Purpose Register
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fpr = Floating Point (FP) Register
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cr = Condition Register
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tbr = Time Base Register
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fpscr = FP Status and Condition Register
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spr = Special Register
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msr = Machine State Register
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sr = Segment Register
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**/
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typedef struct struct_ppc_state {
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FPR_storage fpr[32];
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uint32_t pc; // Referred as the CIA in the PPC manual
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uint32_t gpr[32];
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uint32_t cr;
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uint32_t fpscr;
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uint32_t tbr[2];
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uint32_t spr[1024];
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uint32_t msr;
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uint32_t sr[16];
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bool reserve; // reserve bit used for lwarx and stcwx
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} SetPRS;
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extern SetPRS ppc_state;
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/** symbolic names for frequently used SPRs */
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enum SPR : int {
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MQ = 0, // MQ (601)
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XER = 1,
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RTCU_U = 4, // user mode RTCU (601)
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RTCL_U = 5, // user mode RTCL (601)
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DEC_U = 6, // user mode decrementer (601)
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LR = 8,
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CTR = 9,
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DSISR = 18,
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DAR = 19,
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RTCU_S = 20, // supervisor RTCU (601)
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RTCL_S = 21, // supervisor RTCL (601)
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DEC_S = 22, // supervisor decrementer
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SDR1 = 25,
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SRR0 = 26,
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SRR1 = 27,
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TBL_U = 268, // user mode TBL
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TBU_U = 269, // user mode TBU
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SPRG0 = 272,
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SPRG1 = 273,
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SPRG2 = 274,
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SPRG3 = 275,
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TBL_S = 284, // supervisor TBL
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TBU_S = 285, // supervisor TBU
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PVR = 287,
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MMCR0 = 952,
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PMC1 = 953,
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PMC2 = 954,
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SIA = 955,
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MMCR1 = 956,
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SDA = 959,
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HID0 = 1008,
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HID1 = 1009,
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};
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/** symbolic names for common PPC processors */
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enum PPC_VER : uint32_t {
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MPC601 = 0x00010001,
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MPC603 = 0x00030001,
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MPC604 = 0x00040001,
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MPC603E = 0x00060101,
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MPC603EV = 0x00070101,
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MPC750 = 0x00080200,
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MPC604E = 0x00090202,
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MPC970MP = 0x00440100,
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};
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/**
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typedef struct struct_ppc64_state {
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FPR_storage fpr [32];
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uint64_t pc; //Referred as the CIA in the PPC manual
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uint64_t gpr [32];
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uint32_t cr;
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uint32_t fpscr;
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uint32_t tbr [2];
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uint64_t spr [1024];
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uint32_t msr;
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uint32_t sr [16];
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bool reserve; //reserve bit used for lwarx and stcwx
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} SetPRS64;
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extern SetPRS64 ppc_state64;
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**/
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/**
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Specific SPRS to be weary of:
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USER MODEL
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SPR 1 - XER
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SPR 8 - Link Register / Branch
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b0 - Summary Overflow
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b1 - Overflow
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b2 - Carry
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b25-31 - Number of bytes to transfer
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SPR 9 - Count
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SUPERVISOR MODEL
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19 is the Data Address Register
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22 is the Decrementer
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26, 27 are the Save and Restore Registers (SRR0, SRR1)
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272 - 275 are the SPRGs
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284 - 285 for writing to the TBR's.
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528 - 535 are the Instruction BAT registers
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536 - 543 are the Data BAT registers
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**/
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extern uint64_t timebase_counter;
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extern uint64_t tbr_wr_timestamp;
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extern uint64_t dec_wr_timestamp;
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extern uint64_t rtc_timestamp;
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extern uint64_t tbr_wr_value;
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extern uint32_t dec_wr_value;
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extern uint32_t tbr_freq_ghz;
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extern uint64_t tbr_period_ns;
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extern uint32_t rtc_lo, rtc_hi;
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/* Flags for controlling interpreter execution. */
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enum {
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EXEF_BRANCH = 1 << 0,
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EXEF_EXCEPTION = 1 << 1,
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EXEF_RFI = 1 << 2,
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};
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enum CR_select : int32_t {
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CR0_field = (0xF << 28),
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CR1_field = (0xF << 24),
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};
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// Define bit masks for CR0.
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// To use them in other CR fields, just right shift it by 4*CR_num bits.
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enum CRx_bit : uint32_t {
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CR_SO = 1UL << 28,
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CR_EQ = 1UL << 29,
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CR_GT = 1UL << 30,
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CR_LT = 1UL << 31
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};
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enum CR1_bit : uint32_t {
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CR1_OX = 24,
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CR1_VX,
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CR1_FEX,
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CR1_FX,
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};
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enum FPSCR : uint32_t {
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RN_MASK = 0x3,
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NI = 1UL << 2,
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XE = 1UL << 3,
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ZE = 1UL << 4,
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UE = 1UL << 5,
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OE = 1UL << 6,
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VE = 1UL << 7,
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VXCVI = 1UL << 8,
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VXSQRT = 1UL << 9,
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VXSOFT = 1UL << 10,
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FPCC_FUNAN = 1UL << 12,
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FPCC_ZERO = 1UL << 13,
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FPCC_POS = 1UL << 14,
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FPCC_NEG = 1UL << 15,
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FPCC_MASK = FPCC_NEG | FPCC_POS | FPCC_ZERO | FPCC_FUNAN,
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FPRCD = 1UL << 16,
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FPRF_MASK = FPRCD | FPCC_MASK,
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FI = 1UL << 17,
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FR = 1UL << 18,
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VXVC = 1UL << 19,
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VXIMZ = 1UL << 20,
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VXZDZ = 1UL << 21,
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VXIDI = 1UL << 22,
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VXISI = 1UL << 23,
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VXSNAN = 1UL << 24,
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XX = 1UL << 25,
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ZX = 1UL << 26,
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UX = 1UL << 27,
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OX = 1UL << 28,
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VX = 1UL << 29,
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FEX = 1UL << 30,
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FX = 1UL << 31
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};
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enum MSR : int {
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LE = 0x1, //little endian mode
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RI = 0x2,
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DR = 0x10,
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IR = 0x20,
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IP = 0x40,
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FE1 = 0x100,
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BE = 0x200,
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SE = 0x400,
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FE0 = 0x800,
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ME = 0x1000,
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FP = 0x2000,
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PR = 0x4000,
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EE = 0x8000, //external interrupt
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ILE = 0x10000,
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POW = 0x40000
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};
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enum XER : uint32_t {
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CA = 1UL << 29,
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OV = 1UL << 30,
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SO = 1UL << 31
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};
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//for inf and nan checks
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enum FPOP : int {
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DIV = 0x12,
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SUB = 0x14,
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ADD = 0x15,
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SQRT = 0x16,
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MUL = 0x19
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};
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/** PowerPC exception types. */
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enum class Except_Type {
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EXC_SYSTEM_RESET = 1,
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EXC_MACHINE_CHECK,
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EXC_DSI,
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EXC_ISI,
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EXC_EXT_INT,
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EXC_ALIGNMENT,
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EXC_PROGRAM,
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EXC_NO_FPU,
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EXC_DECR,
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EXC_SYSCALL = 12,
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EXC_TRACE = 13
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};
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/** Program Exception subclasses. */
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enum Exc_Cause : uint32_t {
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FPU_OFF = 1 << (31 - 11),
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ILLEGAL_OP = 1 << (31 - 12),
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NOT_ALLOWED = 1 << (31 - 13),
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TRAP = 1 << (31 - 14),
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};
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extern unsigned exec_flags;
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extern jmp_buf exc_env;
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extern bool grab_return;
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enum Po_Cause : int {
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po_none,
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po_starting_up,
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po_shut_down,
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po_shutting_down,
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po_restarting,
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po_restart,
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po_disassemble_on,
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po_disassemble_off,
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po_enter_debugger,
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po_entered_debugger,
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po_signal_interrupt,
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};
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extern bool power_on;
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extern Po_Cause power_off_reason;
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extern bool int_pin;
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extern bool dec_exception_pending;
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extern bool is_601; // For PowerPC 601 Emulation
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extern bool is_altivec; // For Altivec Emulation
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extern bool is_64bit; // For PowerPC G5 Emulation
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// Important Addressing Integers
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extern uint32_t ppc_cur_instruction;
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extern uint32_t ppc_effective_address;
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extern uint32_t ppc_next_instruction_address;
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inline void ppc_set_cur_instruction(const uint8_t* ptr) {
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ppc_cur_instruction = READ_DWORD_BE_A(ptr);
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}
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// Profiling Stats
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#ifdef CPU_PROFILING
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extern uint64_t num_executed_instrs;
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extern uint64_t num_supervisor_instrs;
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extern uint64_t num_int_loads;
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extern uint64_t num_int_stores;
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extern uint64_t exceptions_processed;
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#endif
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// instruction enums
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typedef enum {
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ppc_and = 1,
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ppc_andc = 2,
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ppc_eqv = 3,
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ppc_nand = 4,
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ppc_nor = 5,
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ppc_or = 6,
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ppc_orc = 7,
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ppc_xor = 8,
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} logical_fun;
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typedef enum {
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LK0,
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LK1,
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} field_lk;
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typedef enum {
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AA0,
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AA1,
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} field_aa;
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typedef enum {
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SHFT0,
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SHFT1,
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} field_shift;
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typedef enum {
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RIGHT0,
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LEFT1,
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} field_direction;
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typedef enum {
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RC0,
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RC1,
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} field_rc;
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typedef enum {
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OV0,
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OV1,
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} field_ov;
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typedef enum {
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CARRY0,
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CARRY1,
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} field_carry;
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typedef enum {
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NOT601,
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IS601,
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} field_601;
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// Function prototypes
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extern void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version, bool include_601, uint64_t tb_freq);
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extern void ppc_mmu_init();
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void ppc_illegalop();
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void ppc_fpu_off();
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void ppc_assert_int();
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void ppc_release_int();
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//void ppc_opcode4();
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void ppc_opcode16();
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void ppc_opcode18();
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template <field_601 for601> void ppc_opcode19();
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void ppc_opcode31();
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void ppc_opcode59();
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void ppc_opcode63();
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void initialize_ppc_opcode_tables(bool include_601);
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extern double fp_return_double(uint32_t reg);
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extern uint64_t fp_return_uint64(uint32_t reg);
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void ppc_changecrf0(uint32_t set_result);
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void set_host_rounding_mode(uint8_t mode);
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void update_fpscr(uint32_t new_fpscr);
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/* Exception handlers. */
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void ppc_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
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[[noreturn]] void dbg_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
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void ppc_floating_point_exception();
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void ppc_alignment_exception(uint32_t ea);
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// MEMORY DECLARATIONS
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extern MemCtrlBase* mem_ctrl_instance;
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extern void add_ctx_sync_action(const std::function<void()> &);
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extern void do_ctx_sync(void);
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// The functions used by the PowerPC processor
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namespace dppc_interpreter {
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template <field_lk l, field_601 for601> extern void ppc_bcctr();
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template <field_lk l> extern void ppc_bclr();
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extern void ppc_crand();
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extern void ppc_crandc();
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extern void ppc_creqv();
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extern void ppc_crnand();
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extern void ppc_crnor();
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extern void ppc_cror();
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extern void ppc_crorc();
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extern void ppc_crxor();
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extern void ppc_isync();
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template <logical_fun logical_op, field_rc rec> extern void ppc_logical();
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template <field_carry carry, field_rc rec, field_ov ov> extern void ppc_add();
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template <field_rc rec, field_ov ov> extern void ppc_adde();
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template <field_rc rec, field_ov ov> extern void ppc_addme();
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template <field_rc rec, field_ov ov> extern void ppc_addze();
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extern void ppc_cmp();
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extern void ppc_cmpl();
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template <field_rc rec> extern void ppc_cntlzw();
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extern void ppc_dcbf();
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extern void ppc_dcbi();
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extern void ppc_dcbst();
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extern void ppc_dcbt();
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extern void ppc_dcbtst();
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extern void ppc_dcbz();
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template <field_rc rec, field_ov ov> extern void ppc_divw();
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template <field_rc rec, field_ov ov> extern void ppc_divwu();
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extern void ppc_eciwx();
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extern void ppc_ecowx();
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extern void ppc_eieio();
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template <class T, field_rc rec>extern void ppc_exts();
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extern void ppc_icbi();
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extern void ppc_mftb();
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extern void ppc_lhaux();
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extern void ppc_lhax();
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extern void ppc_lhbrx();
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extern void ppc_lwarx();
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extern void ppc_lwbrx();
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template <class T> extern void ppc_lzx();
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template <class T> extern void ppc_lzux();
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extern void ppc_mcrxr();
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extern void ppc_mfcr();
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template <field_rc rec> extern void ppc_mulhwu();
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template <field_rc rec> extern void ppc_mulhw();
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template <field_rc rec, field_ov ov> extern void ppc_mullw();
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template <field_rc rec, field_ov ov> extern void ppc_neg();
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template <field_direction shift, field_rc rec> extern void ppc_shift();
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template <field_rc rec> extern void ppc_sraw();
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template <field_rc rec> extern void ppc_srawi();
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template <class T> extern void ppc_stx();
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template <class T> extern void ppc_stux();
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extern void ppc_stfiwx();
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extern void ppc_sthbrx();
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extern void ppc_stwcx();
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extern void ppc_stwbrx();
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template <field_carry carry, field_rc rec, field_ov ov> extern void ppc_subf();
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template <field_rc rec, field_ov ov> extern void ppc_subfe();
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template <field_rc rec, field_ov ov> extern void ppc_subfme();
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template <field_rc rec, field_ov ov> extern void ppc_subfze();
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extern void ppc_sync();
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extern void ppc_tlbia();
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extern void ppc_tlbie();
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extern void ppc_tlbli();
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extern void ppc_tlbld();
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extern void ppc_tlbsync();
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extern void ppc_tw();
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extern void ppc_lswi();
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extern void ppc_lswx();
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extern void ppc_stswi();
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extern void ppc_stswx();
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extern void ppc_mfsr();
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extern void ppc_mfsrin();
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extern void ppc_mtsr();
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extern void ppc_mtsrin();
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extern void ppc_mcrf();
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extern void ppc_mtcrf();
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extern void ppc_mfmsr();
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extern void ppc_mfspr();
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extern void ppc_mtmsr();
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extern void ppc_mtspr();
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template <field_rc rec> extern void ppc_mtfsb0();
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template <field_rc rec> extern void ppc_mtfsb1();
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extern void ppc_mcrfs();
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template <field_rc rec> extern void ppc_fmr();
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template <field_601 for601, field_rc rec> extern void ppc_mffs();
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template <field_rc rec> extern void ppc_mtfsf();
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template <field_rc rec> extern void ppc_mtfsfi();
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template <field_shift shift> extern void ppc_addi();
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template <field_rc rec> extern void ppc_addic();
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template <field_shift shift> extern void ppc_andirc();
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template <field_lk l, field_aa a> extern void ppc_b();
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template <field_lk l, field_aa a> extern void ppc_bc();
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extern void ppc_cmpi();
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extern void ppc_cmpli();
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template <class T> extern void ppc_lz();
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template <class T> extern void ppc_lzu();
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extern void ppc_lha();
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extern void ppc_lhau();
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extern void ppc_lmw();
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extern void ppc_mulli();
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template <field_shift shift> extern void ppc_ori();
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extern void ppc_rfi();
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extern void ppc_rlwimi();
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extern void ppc_rlwinm();
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extern void ppc_rlwnm();
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extern void ppc_sc();
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template <class T> extern void ppc_st();
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template <class T> extern void ppc_stu();
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extern void ppc_stmw();
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extern void ppc_subfic();
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extern void ppc_twi();
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template <field_shift shift> extern void ppc_xori();
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extern void ppc_lfs();
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extern void ppc_lfsu();
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extern void ppc_lfsx();
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extern void ppc_lfsux();
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extern void ppc_lfd();
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extern void ppc_lfdu();
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extern void ppc_lfdx();
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extern void ppc_lfdux();
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extern void ppc_stfs();
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extern void ppc_stfsu();
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extern void ppc_stfsx();
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extern void ppc_stfsux();
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extern void ppc_stfd();
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extern void ppc_stfdu();
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extern void ppc_stfdx();
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extern void ppc_stfdux();
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template <field_rc rec> extern void ppc_fadd();
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template <field_rc rec> extern void ppc_fsub();
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template <field_rc rec> extern void ppc_fmul();
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template <field_rc rec> extern void ppc_fdiv();
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template <field_rc rec> extern void ppc_fadds();
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template <field_rc rec> extern void ppc_fsubs();
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template <field_rc rec> extern void ppc_fmuls();
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template <field_rc rec> extern void ppc_fdivs();
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template <field_rc rec> extern void ppc_fmadd();
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template <field_rc rec> extern void ppc_fmsub();
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template <field_rc rec> extern void ppc_fnmadd();
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template <field_rc rec> extern void ppc_fnmsub();
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template <field_rc rec> extern void ppc_fmadds();
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template <field_rc rec> extern void ppc_fmsubs();
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template <field_rc rec> extern void ppc_fnmadds();
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template <field_rc rec> extern void ppc_fnmsubs();
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template <field_rc rec> extern void ppc_fabs();
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template <field_rc rec> extern void ppc_fnabs();
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template <field_rc rec> extern void ppc_fneg();
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template <field_rc rec> extern void ppc_fsel();
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template <field_rc rec> extern void ppc_fres();
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template <field_rc rec> extern void ppc_fsqrts();
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template <field_rc rec> extern void ppc_fsqrt();
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template <field_rc rec> extern void ppc_frsqrte();
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template <field_rc rec> extern void ppc_frsp();
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template <field_rc rec> extern void ppc_fctiw();
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template <field_rc rec> extern void ppc_fctiwz();
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extern void ppc_fcmpo();
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extern void ppc_fcmpu();
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// Power-specific instructions
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template <field_rc rec, field_ov ov> extern void power_abs();
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extern void power_clcs();
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template <field_rc rec, field_ov ov> extern void power_div();
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template <field_rc rec, field_ov ov> extern void power_divs();
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template <field_rc rec, field_ov ov> extern void power_doz();
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extern void power_dozi();
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template <field_rc rec> extern void power_lscbx();
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template <field_rc rec> extern void power_maskg();
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template <field_rc rec> extern void power_maskir();
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template <field_rc rec, field_ov ov> extern void power_mul();
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template <field_rc rec, field_ov ov> extern void power_nabs();
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extern void power_rlmi();
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template <field_rc rec> extern void power_rrib();
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template <field_rc rec> extern void power_sle();
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template <field_rc rec> extern void power_sleq();
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template <field_rc rec> extern void power_sliq();
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template <field_rc rec> extern void power_slliq();
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template <field_rc rec> extern void power_sllq();
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template <field_rc rec> extern void power_slq();
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template <field_rc rec> extern void power_sraiq();
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template <field_rc rec> extern void power_sraq();
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template <field_rc rec> extern void power_sre();
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template <field_rc rec> extern void power_srea();
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template <field_rc rec> extern void power_sreq();
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template <field_rc rec> extern void power_sriq();
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template <field_rc rec> extern void power_srliq();
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template <field_rc rec> extern void power_srlq();
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|
template <field_rc rec> extern void power_srq();
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} // namespace dppc_interpreter
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// AltiVec instructions
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|
|
// 64-bit instructions
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|
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// G5+ instructions
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extern uint64_t get_virt_time_ns(void);
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extern void ppc_main_opcode(void);
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extern void ppc_exec(void);
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extern void ppc_exec_single(void);
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extern void ppc_exec_until(uint32_t goal_addr);
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extern void ppc_exec_dbg(uint32_t start_addr, uint32_t size);
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|
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/* debugging support API */
|
|
void print_fprs(void); /* print content of the floating-point registers */
|
|
uint64_t get_reg(std::string reg_name); /* get content of the register reg_name */
|
|
void set_reg(std::string reg_name, uint64_t val); /* set reg_name to val */
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#endif /* PPCEMU_H */
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