mirror of
https://github.com/dingusdev/dingusppc.git
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3ee2ea1871
base class uses reg_start so derived classes should do the same. Some derived class already uses reg_start for read method.
114 lines
3.2 KiB
C++
114 lines
3.2 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Hammerhead Memory Controller definitions.
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Author: Max Poliakovski
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Hammerhead is a custom memory controller and ARBus arbiter
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designed especially for the TNT family of Power Macintosh computers.
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*/
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#ifndef HAMMERHEAD_MEMCTRL_H
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#define HAMMERHEAD_MEMCTRL_H
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#include <devices/common/hwcomponent.h>
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#include <devices/common/mmiodevice.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <cinttypes>
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#include <memory>
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namespace Hammerhead {
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#define RISC_MACHINE 0x3
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#define MACH_TYPE_TNT 0x1
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#define HH_CPU_ID_TNT ((RISC_MACHINE << 4) | (1 << 3) | MACH_TYPE_TNT)
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// contants for the MBID field of the MOTHERBOARD_ID register
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enum {
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MBID_VCI0_PRESENT = 4,
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MBID_PCI2_PRESENT = 2,
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};
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// ARBus speed constants for the CPU_SPEED register
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enum {
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BUS_SPEED_40_MHZ = 0,
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BUS_SPEED_33_MHZ = 1,
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BUS_SPEED_44_MHZ = 2,
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BUS_SPEED_50_MHZ = 3
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};
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// bus master IDs for the WHO_AM_I register
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enum {
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BM_VIDEO_BRIDGE = 1 << 4,
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BM_PCI_BRIDGE_1 = 1 << 3,
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BM_PCI_BRIDGE_2 = 1 << 2,
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BM_PRIMARY_CPU = 1 << 1,
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BM_SECONDARY_CPU = 1 << 0
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};
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// Configuration and status registers.
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enum HammerheadReg : uint16_t {
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CPU_ID = 0x00,
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ASIC_REVISION = 0x10,
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MOTHERBOARD_ID = 0x20,
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CPU_SPEED = 0x30,
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MB_DRAM_CONFIG = 0x40,
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MEM_TIMING_0 = 0x50,
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MEM_TIMING_1 = 0x60,
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REFRESH_TIMING = 0x70,
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ROM_TIMING = 0x80,
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ARBITER_CONFIG = 0x90,
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ARBUS_TIMEOUT = 0xA0,
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WHO_AM_I = 0xB0,
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L2_CACHE_CONFIG = 0xE0,
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BANK_0_BASE_MSB = 0x1C0,
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BANK_25_BASE_LSB = 0x4F0,
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};
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}; // namespace Hammerhead
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class HammerheadCtrl : public MemCtrlBase, public MMIODevice {
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public:
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HammerheadCtrl();
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~HammerheadCtrl() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<HammerheadCtrl>(new HammerheadCtrl());
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}
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// MMIODevice methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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void insert_ram_dimm(int slot_num, uint32_t capacity);
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void map_phys_ram();
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private:
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uint8_t arb_config = 0;
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uint16_t bank_base[26];
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uint32_t bank_size[26] = { 0 };
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};
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#endif // HAMMERHEAD_MEMCTRL_H
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