mirror of
https://github.com/dingusdev/dingusppc.git
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306 lines
8.9 KiB
C++
306 lines
8.9 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Descriptor-based direct memory access emulation. */
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#include <cpu/ppc/ppcmmu.h>
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#include <devices/common/dbdma.h>
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#include <devices/common/dmacore.h>
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#include <endianswap.h>
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#include <memaccess.h>
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#include <cinttypes>
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#include <cstring>
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#include <loguru.hpp>
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void DMAChannel::set_callbacks(DbdmaCallback start_cb, DbdmaCallback stop_cb)
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{
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this->start_cb = start_cb;
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this->stop_cb = stop_cb;
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}
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void DMAChannel::fetch_cmd(uint32_t cmd_addr, DMACmd* p_cmd) {
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/* load DMACmd from physical memory */
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memcpy((uint8_t*)p_cmd, mmu_get_dma_mem(cmd_addr, 16, nullptr), 16);
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}
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uint8_t DMAChannel::interpret_cmd() {
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DMACmd cmd_struct;
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bool is_writable;
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int cmd;
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if (this->cmd_in_progress) {
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// return current command if there is data to transfer
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if (this->queue_len)
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return cmd;
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// obtain real pointer to the descriptor of the completed command
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uint8_t *curr_cmd = mmu_get_dma_mem(this->cmd_ptr - 16, 16, &is_writable);
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// get command code
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cmd = curr_cmd[3] >> 4;
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// all commands except STOP update cmd.xferStatus
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if (cmd < 7 && is_writable) {
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WRITE_WORD_LE_A(&curr_cmd[14], this->ch_stat | CH_STAT_ACTIVE);
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}
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// all INPUT and OUTPUT commands update cmd.resCount
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if (cmd < 4 && is_writable) {
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WRITE_WORD_LE_A(&curr_cmd[12], this->queue_len & 0xFFFFUL);
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}
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this->cmd_in_progress = false;
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}
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fetch_cmd(this->cmd_ptr, &cmd_struct);
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cmd = cmd_struct.cmd_key >> 4;
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this->ch_stat &= ~CH_STAT_WAKE; /* clear wake bit (DMA spec, 5.5.3.4) */
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switch (cmd_struct.cmd_key >> 4) {
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case 0: // OUTPUT_MORE
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case 1: // OUTPUT_LAST
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case 2: // INPUT_MORE
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case 3: // INPUT_LAST
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if (cmd_struct.cmd_key & 7) {
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LOG_F(ERROR, "Key > 0 not implemented");
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break;
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}
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if (cmd_struct.cmd_bits & 0x3F) {
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LOG_F(ERROR, "non-zero i/b/w not implemented");
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break;
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}
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this->queue_data = mmu_get_dma_mem(cmd_struct.address, cmd_struct.req_count, &is_writable);
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this->queue_len = cmd_struct.req_count;
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this->cmd_ptr += 16;
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this->cmd_in_progress = true;
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break;
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case 4:
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LOG_F(ERROR, "Unsupported DMA Command STORE_QUAD");
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break;
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case 5:
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LOG_F(ERROR, "Unsupported DMA Command LOAD_QUAD");
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break;
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case 6:
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LOG_F(ERROR, "Unsupported DMA Command NOP");
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break;
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case 7:
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this->ch_stat &= ~CH_STAT_ACTIVE;
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this->cmd_in_progress = false;
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break;
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default:
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LOG_F(ERROR, "Unsupported DMA command 0x%X", cmd_struct.cmd_key >> 4);
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this->ch_stat |= CH_STAT_DEAD;
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this->ch_stat &= ~CH_STAT_ACTIVE;
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}
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return (cmd_struct.cmd_key >> 4);
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}
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uint32_t DMAChannel::reg_read(uint32_t offset, int size) {
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uint32_t res = 0;
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if (size != 4) {
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LOG_F(WARNING, "Unsupported non-DWORD read from DMA channel");
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return 0;
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}
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switch (offset) {
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case DMAReg::CH_CTRL:
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res = 0; /* ChannelControl reads as 0 (DBDMA spec 5.5.1, table 74) */
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break;
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case DMAReg::CH_STAT:
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res = BYTESWAP_32(this->ch_stat);
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break;
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default:
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LOG_F(WARNING, "Unsupported DMA channel register 0x%X", offset);
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}
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return res;
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}
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void DMAChannel::reg_write(uint32_t offset, uint32_t value, int size) {
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uint16_t mask, old_stat, new_stat;
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if (size != 4) {
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LOG_F(WARNING, "Unsupported non-DWORD write to DMA channel");
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return;
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}
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value = BYTESWAP_32(value);
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old_stat = this->ch_stat;
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switch (offset) {
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case DMAReg::CH_CTRL:
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mask = value >> 16;
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new_stat = (value & mask & 0xF0FFU) | (old_stat & ~mask);
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LOG_F(9, "New ChannelStatus value = 0x%X", new_stat);
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if ((new_stat & CH_STAT_RUN) != (old_stat & CH_STAT_RUN)) {
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if (new_stat & CH_STAT_RUN) {
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new_stat |= CH_STAT_ACTIVE;
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this->ch_stat = new_stat;
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this->start();
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} else {
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new_stat &= ~CH_STAT_ACTIVE;
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new_stat &= ~CH_STAT_DEAD;
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this->ch_stat = new_stat;
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this->abort();
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}
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} else if ((new_stat & CH_STAT_WAKE) != (old_stat & CH_STAT_WAKE)) {
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new_stat |= CH_STAT_ACTIVE;
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this->ch_stat = new_stat;
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this->resume();
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} else if ((new_stat & CH_STAT_PAUSE) != (old_stat & CH_STAT_PAUSE)) {
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if (new_stat & CH_STAT_PAUSE) {
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new_stat &= ~CH_STAT_ACTIVE;
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this->ch_stat = new_stat;
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this->pause();
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}
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}
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if (new_stat & CH_STAT_FLUSH) {
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LOG_F(WARNING, "DMA flush not implemented!");
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new_stat &= ~CH_STAT_FLUSH;
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this->ch_stat = new_stat;
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}
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break;
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case DMAReg::CH_STAT:
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break; /* ingore writes to ChannelStatus */
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case DMAReg::CMD_PTR_LO:
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if (!(this->ch_stat & CH_STAT_RUN) && !(this->ch_stat & CH_STAT_ACTIVE)) {
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this->cmd_ptr = value;
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LOG_F(9, "CommandPtrLo set to 0x%X", this->cmd_ptr);
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}
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break;
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default:
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LOG_F(WARNING, "Unsupported DMA channel register 0x%X", offset);
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}
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}
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DmaPullResult DMAChannel::pull_data(uint32_t req_len, uint32_t *avail_len, uint8_t **p_data)
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{
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*avail_len = 0;
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if (this->ch_stat & CH_STAT_DEAD || !(this->ch_stat & CH_STAT_ACTIVE)) {
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/* dead or idle channel? -> no more data */
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LOG_F(WARNING, "Dead/idle channel -> no more data");
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return DmaPullResult::NoMoreData;
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}
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/* interpret DBDMA program until we get data or become idle */
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while ((this->ch_stat & CH_STAT_ACTIVE) && !this->queue_len) {
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this->interpret_cmd();
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}
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/* dequeue data if any */
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if (this->queue_len) {
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if (this->queue_len >= req_len) {
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LOG_F(9, "Return req_len = %d data", req_len);
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*p_data = this->queue_data;
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*avail_len = req_len;
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this->queue_len -= req_len;
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this->queue_data += req_len;
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} else { /* return less data than req_len */
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LOG_F(9, "Return queue_len = %d data", this->queue_len);
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*p_data = this->queue_data;
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*avail_len = this->queue_len;
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this->queue_len = 0;
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}
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return DmaPullResult::MoreData; /* tell the caller there is more data */
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}
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return DmaPullResult::NoMoreData; /* tell the caller there is no more data */
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}
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int DMAChannel::push_data(const char* src_ptr, int len)
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{
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if (this->ch_stat & CH_STAT_DEAD || !(this->ch_stat & CH_STAT_ACTIVE)) {
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LOG_F(WARNING, "DBDMA: attempt to push data to dead/idle channel");
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return -1;
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}
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// interpret DBDMA program until we get buffer to fill in or become idle
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while ((this->ch_stat & CH_STAT_ACTIVE) && !this->queue_len) {
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this->interpret_cmd();
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}
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if (this->queue_len) {
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len = std::min((int)this->queue_len, len);
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std::memcpy(this->queue_data, src_ptr, len);
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this->queue_data += len;
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this->queue_len -= len;
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}
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// proceed with the DBDMA program if the buffer became exhausted
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if (!this->queue_len) {
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this->interpret_cmd();
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}
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return 0;
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}
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bool DMAChannel::is_active()
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{
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if (this->ch_stat & CH_STAT_DEAD || !(this->ch_stat & CH_STAT_ACTIVE)) {
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return false;
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}
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else {
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return true;
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}
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}
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void DMAChannel::start()
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{
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if (this->ch_stat & CH_STAT_PAUSE) {
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LOG_F(WARNING, "Cannot start DMA channel, PAUSE bit is set");
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return;
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}
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LOG_F(INFO, "Starting DMA channel, stat = 0x%X", this->ch_stat);
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this->queue_len = 0;
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if (this->start_cb)
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this->start_cb();
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}
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void DMAChannel::resume() {
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if (this->ch_stat & CH_STAT_PAUSE) {
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LOG_F(WARNING, "Cannot resume DMA channel, PAUSE bit is set");
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return;
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}
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LOG_F(INFO, "Resuming DMA channel");
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}
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void DMAChannel::abort() {
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LOG_F(INFO, "Aborting DMA channel");
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}
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void DMAChannel::pause() {
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LOG_F(INFO, "Pausing DMA channel");
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if (this->stop_cb)
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this->stop_cb();
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}
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