mirror of
https://github.com/dingusdev/dingusppc.git
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3ee2ea1871
base class uses reg_start so derived classes should do the same. Some derived class already uses reg_start for read method.
144 lines
4.3 KiB
C++
144 lines
4.3 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file TNT on-board video output definitions. */
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#ifndef CONTROL_VIDEO_H
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#define CONTROL_VIDEO_H
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#include <devices/common/i2c/athens.h>
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#include <devices/common/pci/pcidevice.h>
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#include <devices/ioctrl/macio.h>
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#include <devices/video/displayid.h>
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#include <devices/video/videoctrl.h>
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#include <cinttypes>
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#include <memory>
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#define TEST_STROBE (1 << 3) // strobe bit
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// Memory-mapped registers.
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namespace ControlRegs {
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enum ControlRegs : int {
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CUR_LINE = 0x00, // current active video line
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VFPEQ = 0x01,
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VFP = 0x02,
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VAL = 0x03, // vertical active line
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VBP = 0x04,
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VBPEQ = 0x05, // begin of th vertical back porch with equalization
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VSYNC = 0x06,
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VHLINE = 0x07,
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PIPED = 0x08,
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HPIX = 0x09,
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HFP = 0x0A,
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HAL = 0x0B, // horizontal active line
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HBWAY = 0x0C,
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HSP = 0x0D,
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HEQ = 0x0E,
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HLFLN = 0x0F,
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HSERR = 0x10,
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CNTTST = 0x11, // Swatch counter test
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TEST = 0x12,
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GBASE = 0x13, // Graphics base address
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ROW_WORDS = 0x14,
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MON_SENSE = 0x15, // Monitor sense control & status
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ENABLE = 0x16,
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GSC_DIVIDE = 0x17, // graphics clock divide count
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REFRESH_COUNT = 0x18,
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INT_ENABLE = 0x19,
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INT_STATUS = 0x1A
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};
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}; // namespace ControlRegs
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namespace RadacalRegs {
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enum RadacalRegs : uint8_t {
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ADDRESS = 0, // address register
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CURSOR_DATA = 1, // cursor data
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MULTI = 2, // multipurpose section
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CLUT_DATA = 3, // color palette data
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// multipurpose section registers
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CURSOR_POS_HI = 0x10, // cursor position, high-order byte
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CURSOR_POS_LO = 0x11, // cursor position, low-order byte
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MISC_CTRL = 0x20, // miscellaneus control bits
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DBL_BUF_CTRL = 0x21, // double buffer control bits
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};
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}; // namespace RadacalRegs
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class ControlVideo : public PCIDevice, public VideoCtrlBase, public IobusDevice {
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public:
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ControlVideo();
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~ControlVideo() = default;
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<ControlVideo>(new ControlVideo());
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}
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// MMIODevice methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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protected:
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void notify_bar_change(int bar_num);
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void enable_display();
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void disable_display();
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// IobusDevice methods for RaDACal
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uint16_t iodev_read(uint32_t address);
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void iodev_write(uint32_t address, uint16_t value);
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private:
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std::unique_ptr<DisplayID> display_id;
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std::unique_ptr<AthensClocks> clk_gen;
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std::unique_ptr<uint8_t[]> vram_ptr;
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uint32_t vram_size;
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uint32_t vram_base = 0;
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uint32_t regs_base = 0;
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uint32_t prev_test = 0x433;
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uint32_t test = 0;
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uint32_t clock_divider = 0;
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uint32_t row_words = 0;
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uint32_t fb_base = 0;
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uint16_t swatch_params[16];
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int test_shift = 0;
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uint8_t cur_mon_id = 0;
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uint8_t flags = 0;
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uint8_t int_enable = 0;
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// RaDACal internal state
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uint8_t rad_addr = 0;
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uint8_t rad_cr = 0;
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uint8_t rad_dbl_buf_cr = 0;
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uint8_t rad_cur_pos_hi = 0;
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uint8_t rad_cur_pos_lo = 0;
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uint8_t comp_index;
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uint8_t clut_color[3];
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};
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#endif // CONTROL_VIDEO_H
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