mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-09-01 17:29:17 +00:00
326 lines
11 KiB
C++
326 lines
11 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu/ppc/ppcemu.h>
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#include <devices/deviceregistry.h>
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#include <devices/common/scsi/sc53c94.h>
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#include <devices/ethernet/mace.h>
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#include <devices/floppy/swim3.h>
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#include <devices/ioctrl/macio.h>
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#include <devices/serial/escc.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <cinttypes>
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#include <memory>
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GrandCentral::GrandCentral() : PCIDevice("mac-io/grandcentral"), InterruptCtrl()
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{
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supports_types(HWCompType::MMIO_DEV | HWCompType::INT_CTRL);
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// populate my PCI config header
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = 0x0002;
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this->class_rev = 0xFF000002;
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this->cache_ln_sz = 8;
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this->bars_cfg[0] = 0xFFFE0000UL; // declare 128Kb of memory-mapped I/O space
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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// NVRAM connection
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this->nvram = dynamic_cast<NVram*>(gMachineObj->get_comp_by_name("NVRAM"));
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// connect Cuda
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this->viacuda = dynamic_cast<ViaCuda*>(gMachineObj->get_comp_by_name("ViaCuda"));
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// initialize sound chip and its DMA output channel, then wire them together
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this->awacs = std::unique_ptr<AwacsScreamer> (new AwacsScreamer());
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this->snd_out_dma = std::unique_ptr<DMAChannel> (new DMAChannel());
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this->awacs->set_dma_out(this->snd_out_dma.get());
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this->snd_out_dma->set_callbacks(
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std::bind(&AwacsScreamer::dma_start, this->awacs.get()),
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std::bind(&AwacsScreamer::dma_end, this->awacs.get())
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);
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// connect serial HW
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this->escc = dynamic_cast<EsccController*>(gMachineObj->get_comp_by_name("Escc"));
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// connect SCSI HW
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this->scsi_0 = dynamic_cast<Sc53C94*>(gMachineObj->get_comp_by_name("Sc53C94"));
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// connect Ethernet HW
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this->mace = dynamic_cast<MaceController*>(gMachineObj->get_comp_by_name("Mace"));
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// connect floppy disk HW
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this->swim3 = dynamic_cast<Swim3::Swim3Ctrl*>(gMachineObj->get_comp_by_name("Swim3"));
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// set EMMO pin status (active low)
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this->emmo_pin = GET_BIN_PROP("emmo") ^ 1;
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}
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void GrandCentral::notify_bar_change(int bar_num)
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{
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if (bar_num) // only BAR0 is supported
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return;
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if (this->base_addr != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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if (this->base_addr) {
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LOG_F(WARNING, "GC: deallocating I/O memory not implemented");
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}
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this->base_addr = this->bars[0] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->base_addr, 0x20000, this);
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LOG_F(INFO, "%s: base address set to 0x%X", this->pci_name.c_str(), this->base_addr);
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}
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}
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uint32_t GrandCentral::read(uint32_t rgn_start, uint32_t offset, int size)
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{
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if (offset & 0x10000) { // Device register space
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unsigned subdev_num = (offset >> 12) & 0xF;
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switch (subdev_num) {
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case 0: // Curio SCSI
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return this->scsi_0->read((offset >> 4) & 0xF);
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case 1: // MACE
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return this->mace->read((offset >> 4) & 0x1F);
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case 2: // ESCC compatible addressing
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if ((offset & 0xFF) < 16) {
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return this->escc->read(compat_to_macrisc[(offset >> 1) & 0xF]);
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}
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// fallthrough
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case 3: // ESCC MacRISC addressing
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return this->escc->read((offset >> 4) & 0xF);
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case 4: // AWACS
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return this->awacs->snd_ctrl_read(offset & 0xFF, size);
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case 5: // SWIM3
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return this->swim3->read((offset >> 4) & 0xF);
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case 6:
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case 7: // VIA-CUDA
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return this->viacuda->read((offset >> 9) & 0xF);
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case 0xA: // Board register 1 (IOBus dev #1)
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return BYTESWAP_32(this->emmo_pin << 8);
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case 0xB: // IOBus dev #2
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case 0xC: // IOBus dev #3
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case 0xE: // IOBus dev #5
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if (this->iobus_devs[subdev_num - 10] != nullptr) {
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return BYTESWAP_16(this->iobus_devs[subdev_num - 10]->iodev_read(
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(offset >> 4) & 0x1F));
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} else {
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LOG_F(ERROR, "GC: IOBus device #%d doesn't exist", subdev_num - 9);
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return 0;
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}
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break;
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case 0xF: // NVRAM Data (IOBus dev #6)
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return this->nvram->read_byte(
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(this->nvram_addr_hi << 5) + ((offset >> 4) & 0x1F));
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}
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} else if (offset & 0x8000) { // DMA register space
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unsigned subdev_num = (offset >> 12) & 0xF;
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switch (subdev_num) {
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case 8:
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return this->snd_out_dma->reg_read(offset & 0xFF, size);
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default:
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LOG_F(WARNING, "GC: unimplemented DMA register at 0x%X",
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this->base_addr + offset);
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}
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} else { // Interrupt related registers
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switch (offset) {
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case MIO_INT_MASK1:
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return BYTESWAP_32(this->int_mask);
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case MIO_INT_LEVELS1:
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return BYTESWAP_32(this->int_levels);
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case MIO_INT_EVENTS1:
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return BYTESWAP_32(this->int_events);
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}
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}
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LOG_F(WARNING, "GC: reading from unmapped I/O memory 0x%X", this->base_addr + offset);
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return 0;
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}
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void GrandCentral::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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{
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if (offset & 0x10000) { // Device register space
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unsigned subdev_num = (offset >> 12) & 0xF;
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switch (subdev_num) {
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case 0: // Curio SCSI
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this->scsi_0->write((offset >> 4) & 0xF, value);
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break;
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case 1: // MACE registers
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this->mace->write((offset >> 4) & 0x1F, value);
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break;
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case 2: // ESCC compatible addressing
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if ((offset & 0xFF) < 16) {
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this->escc->write(compat_to_macrisc[(offset >> 1) & 0xF], value);
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break;
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}
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// fallthrough
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case 3: // ESCC MacRISC addressing
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this->escc->write((offset >> 4) & 0xF, value);
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break;
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case 4: // AWACS
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this->awacs->snd_ctrl_write(offset & 0xFF, value, size);
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break;
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case 5:
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this->swim3->write((offset >> 4) & 0xF, value);
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break;
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case 6:
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case 7: // VIA-CUDA
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this->viacuda->write((offset >> 9) & 0xF, value);
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break;
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case 0xA: // IOBus dev #1
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case 0xB: // IOBus dev #2
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case 0xC: // IOBus dev #3
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case 0xE: // IOBus dev #5
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if (this->iobus_devs[subdev_num - 10] != nullptr) {
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this->iobus_devs[subdev_num - 10]->iodev_write(
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(offset >> 4) & 0x1F, value);
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} else {
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LOG_F(ERROR, "GC: IOBus device #%d doesn't exist", subdev_num - 9);
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}
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break;
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case 0xD: // NVRAM High Address (IOBus dev #4)
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switch (size) {
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case 4:
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this->nvram_addr_hi = BYTESWAP_32(value);
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break;
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case 2:
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this->nvram_addr_hi = BYTESWAP_16(value);
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break;
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default:
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this->nvram_addr_hi = value;
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}
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break;
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case 0xF: // NVRAM Data (IOBus dev #6)
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this->nvram->write_byte(
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(this->nvram_addr_hi << 5) + ((offset >> 4) & 0x1F), value);
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break;
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default:
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LOG_F(WARNING, "GC: writing to unmapped I/O memory 0x%X",
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this->base_addr + offset);
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}
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} else if (offset & 0x8000) { // DMA register space
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unsigned subdev_num = (offset >> 12) & 0xF;
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switch (subdev_num) {
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case 8:
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this->snd_out_dma->reg_write(offset & 0xFF, value, size);
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break;
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default:
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LOG_F(WARNING, "GC: unimplemented DMA register at 0x%X",
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this->base_addr + offset);
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}
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} else { // Interrupt related registers
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switch (offset) {
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case MIO_INT_MASK1:
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this->int_mask = BYTESWAP_32(value);
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break;
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case MIO_INT_CLEAR1:
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if (value & MACIO_INT_CLR) {
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this->int_events = 0;
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this->cpu_int_latch = false;
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ppc_release_int();
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LOG_F(5, "GC: CPU INT latch cleared");
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} else {
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this->int_events &= BYTESWAP_32(value);
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}
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break;
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default:
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LOG_F(WARNING, "GC: writing to unmapped I/O memory 0x%X",
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this->base_addr + offset);
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}
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}
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}
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void GrandCentral::attach_iodevice(int dev_num, IobusDevice* dev_obj)
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{
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if (dev_num >= 0 && dev_num < 6) {
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this->iobus_devs[dev_num] = dev_obj;
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}
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}
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uint32_t GrandCentral::register_dev_int(IntSrc src_id)
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{
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switch (src_id) {
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case IntSrc::VIA_CUDA:
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return 1 << 18;
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case IntSrc::SCSI1:
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return 1 << 12;
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case IntSrc::SWIM3:
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return 1 << 19;
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default:
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ABORT_F("GC: unknown interrupt source %d", src_id);
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}
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return 0;
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}
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uint32_t GrandCentral::register_dma_int(IntSrc src_id)
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{
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ABORT_F("GC: register_dma_int() not implemened");
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return 0;
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}
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void GrandCentral::ack_int(uint32_t irq_id, uint8_t irq_line_state)
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{
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if (this->int_mask & MACIO_INT_MODE) { // 68k interrupt emulation mode?
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this->int_events |= irq_id; // signal IRQ line change
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this->int_events &= this->int_mask;
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// update IRQ line state
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if (irq_line_state) {
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this->int_levels |= irq_id;
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} else {
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this->int_levels &= ~irq_id;
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}
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// signal CPU interrupt
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if (this->int_events) {
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if (!this->cpu_int_latch) {
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this->cpu_int_latch = true;
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ppc_assert_int();
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LOG_F(5, "GC: CPU INT asserted, source: %d", irq_id);
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} else {
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LOG_F(5, "GC: CPU INT already latched");
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}
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}
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} else {
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ABORT_F("GC: native interrupt mode not implemented");
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}
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}
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void GrandCentral::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state)
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{
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ABORT_F("GC: ack_dma_int() not implemened");
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}
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static const vector<string> GCSubdevices = {
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"NVRAM", "ViaCuda", "Escc", "Sc53C94", "Mace", "Swim3"
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};
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static const DeviceDescription GC_Descriptor = {
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GrandCentral::create, GCSubdevices, {}
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};
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REGISTER_DEVICE(GrandCentral, GC_Descriptor);
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