mirror of
https://github.com/dingusdev/dingusppc.git
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553 lines
20 KiB
C++
553 lines
20 KiB
C++
/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu/ppc/ppcemu.h>
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#include <devices/deviceregistry.h>
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#include <devices/common/ata/idechannel.h>
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#include <devices/common/dbdma.h>
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#include <devices/common/hwcomponent.h>
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#include <devices/common/viacuda.h>
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#include <devices/floppy/swim3.h>
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#include <devices/ioctrl/macio.h>
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#include <devices/serial/escc.h>
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#include <devices/sound/awacs.h>
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#include <endianswap.h>
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#include <loguru.hpp>
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#include <machines/machinebase.h>
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#include <cinttypes>
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#include <functional>
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#include <memory>
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/** Heathrow Mac I/O device emulation.
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Author: Max Poliakovski
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*/
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using namespace std;
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HeathrowIC::HeathrowIC() : PCIDevice("mac-io_heathrow"), InterruptCtrl()
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{
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supports_types(HWCompType::MMIO_DEV | HWCompType::PCI_DEV | HWCompType::INT_CTRL);
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// populate my PCI config header
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = MIO_DEV_ID_HEATHROW;
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this->class_rev = 0xFF000001;
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this->cache_ln_sz = 8;
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this->setup_bars({{0, 0xFFF80000UL}}); // declare 512Kb of memory-mapped I/O space
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this->pci_notify_bar_change = [this](int bar_num) {
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this->notify_bar_change(bar_num);
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};
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// NVRAM connection
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this->nvram = dynamic_cast<NVram*>(gMachineObj->get_comp_by_name("NVRAM"));
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// connect Cuda
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this->viacuda = dynamic_cast<ViaCuda*>(gMachineObj->get_comp_by_name("ViaCuda"));
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// find appropriate sound chip, create a DMA output channel for sound,
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// then wire everything together
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this->snd_codec = dynamic_cast<MacioSndCodec*>(gMachineObj->get_comp_by_type(HWCompType::SND_CODEC));
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this->snd_out_dma = std::unique_ptr<DMAChannel> (new DMAChannel("snd_out"));
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this->snd_out_dma->register_dma_int(this, this->register_dma_int(IntSrc::DMA_DAVBUS_Tx));
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this->snd_codec->set_dma_out(this->snd_out_dma.get());
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this->snd_out_dma->set_callbacks(
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std::bind(&AwacsScreamer::dma_out_start, this->snd_codec),
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std::bind(&AwacsScreamer::dma_out_stop, this->snd_codec)
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);
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// connect SCSI HW and the corresponding DMA channel
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this->mesh = dynamic_cast<MeshController*>(gMachineObj->get_comp_by_name("MeshHeathrow"));
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this->mesh_dma = std::unique_ptr<DMAChannel> (new DMAChannel("mesh"));
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this->mesh_dma->register_dma_int(this, this->register_dma_int(IntSrc::DMA_SCSI_MESH));
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this->mesh_dma->connect(this->mesh);
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this->mesh->connect(this->mesh_dma.get());
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// connect IDE HW
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this->ide_0 = dynamic_cast<IdeChannel*>(gMachineObj->get_comp_by_name("Ide0"));
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this->ide_1 = dynamic_cast<IdeChannel*>(gMachineObj->get_comp_by_name("Ide1"));
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// connect serial HW
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this->escc = dynamic_cast<EsccController*>(gMachineObj->get_comp_by_name("Escc"));
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// connect DBDMA
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this->escc_b_rcv_dma = std::unique_ptr<DMAChannel>(new DMAChannel("DBDMABRx"));
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// connect floppy disk HW and initialize its DMA channel
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this->swim3 = dynamic_cast<Swim3::Swim3Ctrl*>(gMachineObj->get_comp_by_name("Swim3"));
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this->floppy_dma = std::unique_ptr<DMAChannel> (new DMAChannel("floppy"));
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this->swim3->set_dma_channel(this->floppy_dma.get());
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this->floppy_dma->register_dma_int(this, this->register_dma_int(IntSrc::DMA_SWIM3));
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// connect Ethernet HW
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this->bmac = dynamic_cast<BigMac*>(gMachineObj->get_comp_by_type(HWCompType::ETHER_MAC));
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this->enet_xmit_dma = std::unique_ptr<DMAChannel> (new DMAChannel("BmacTx"));
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this->enet_rcv_dma = std::unique_ptr<DMAChannel> (new DMAChannel("BmacRx"));
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// set EMMO pin status (active low)
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this->emmo_pin = GET_BIN_PROP("emmo") ^ 1;
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}
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static const char *get_name_dma(unsigned dma_channel) {
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switch (dma_channel) {
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case MIO_OHARE_DMA_MESH : return "DMA_MESH" ;
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case MIO_OHARE_DMA_FLOPPY : return "DMA_FLOPPY" ;
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case MIO_OHARE_DMA_ETH_XMIT : return "DMA_ETH_XMIT" ;
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case MIO_OHARE_DMA_ETH_RCV : return "DMA_ETH_RCV" ;
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case MIO_OHARE_DMA_ESCC_A_XMIT : return "DMA_ESCC_A_XMIT";
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case MIO_OHARE_DMA_ESCC_A_RCV : return "DMA_ESCC_A_RCV" ;
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case MIO_OHARE_DMA_ESCC_B_XMIT : return "DMA_ESCC_B_XMIT";
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case MIO_OHARE_DMA_ESCC_B_RCV : return "DMA_ESCC_B_RCV" ;
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case MIO_OHARE_DMA_AUDIO_OUT : return "DMA_AUDIO_OUT" ;
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case MIO_OHARE_DMA_AUDIO_IN : return "DMA_AUDIO_IN" ;
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case MIO_OHARE_DMA_IDE0 : return "DMA_IDE0" ;
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case MIO_OHARE_DMA_IDE1 : return "DMA_IDE1" ;
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default : return "unknown" ;
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}
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}
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void HeathrowIC::set_media_bay_id(uint8_t id) {
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this->mb_id = id;
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}
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void HeathrowIC::notify_bar_change(int bar_num)
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{
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if (bar_num) // only BAR0 is supported
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return;
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if (this->base_addr != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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if (this->base_addr) {
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this->host_instance->pci_unregister_mmio_region(this->base_addr, 0x80000, this);
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}
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this->base_addr = this->bars[0] & 0xFFFFFFF0UL;
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this->host_instance->pci_register_mmio_region(this->base_addr, 0x80000, this);
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LOG_F(INFO, "%s: base address set to 0x%X", this->get_name().c_str(), this->base_addr);
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}
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}
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uint32_t HeathrowIC::dma_read(uint32_t offset, int size) {
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int dma_channel = offset >> 8;
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switch (dma_channel) {
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case MIO_OHARE_DMA_MESH:
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if (this->mesh_dma)
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return this->mesh_dma->reg_read(offset & 0xFF, size);
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else
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return 0;
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case MIO_OHARE_DMA_FLOPPY:
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return this->floppy_dma->reg_read(offset & 0xFF, size);
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case MIO_OHARE_DMA_ETH_XMIT:
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return this->enet_xmit_dma->reg_read(offset & 0xFF, size);
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case MIO_OHARE_DMA_ETH_RCV:
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return this->enet_rcv_dma->reg_read(offset & 0xFF, size);
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case MIO_OHARE_DMA_ESCC_B_RCV:
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return this->escc_b_rcv_dma->reg_read(offset & 0xFF, size);
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case MIO_OHARE_DMA_AUDIO_OUT:
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return this->snd_out_dma->reg_read(offset & 0xFF, size);
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default:
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if (!(unsupported_dma_channel_read & (1 << dma_channel))) {
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unsupported_dma_channel_read |= (1 << dma_channel);
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LOG_F(WARNING, "%s: Unsupported DMA channel %d %s read @%02x.%c", this->name.c_str(),
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dma_channel, get_name_dma(dma_channel), offset & 0xFF, SIZE_ARG(size));
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}
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}
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return 0;
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}
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void HeathrowIC::dma_write(uint32_t offset, uint32_t value, int size) {
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int dma_channel = offset >> 8;
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switch (dma_channel) {
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case MIO_OHARE_DMA_MESH:
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if (this->mesh_dma) this->mesh_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_OHARE_DMA_FLOPPY:
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this->floppy_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_OHARE_DMA_ETH_XMIT:
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this->enet_xmit_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_OHARE_DMA_ETH_RCV:
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this->enet_rcv_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_OHARE_DMA_ESCC_B_RCV:
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this->escc_b_rcv_dma->reg_write(offset & 0xFF, value, size);
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break;
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case MIO_OHARE_DMA_AUDIO_OUT:
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this->snd_out_dma->reg_write(offset & 0xFF, value, size);
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break;
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default:
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if (!(unsupported_dma_channel_write & (1 << dma_channel))) {
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unsupported_dma_channel_write |= (1 << dma_channel);
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LOG_F(WARNING, "%s: Unsupported DMA channel %d %s write @%02x.%c = %0*x", this->name.c_str(),
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dma_channel, get_name_dma(dma_channel), offset & 0xFF, SIZE_ARG(size), size * 2, value);
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}
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}
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}
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uint32_t HeathrowIC::read(uint32_t rgn_start, uint32_t offset, int size) {
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uint32_t value;
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LOG_F(9, "%s: reading from offset %x", this->name.c_str(), offset);
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unsigned sub_addr = (offset >> 12) & 0x7F;
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switch (sub_addr) {
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case 0:
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value = mio_ctrl_read(offset, size);
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break;
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case 8:
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value = dma_read(offset & 0x7FFF, size);
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break;
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case 0x10: // SCSI
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value = this->mesh->read((offset >> 4) & 0xF);
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break;
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case 0x11: // Ethernet
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value = BYTESWAP_SIZED(this->bmac->read(offset & 0xFFFU), size);
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break;
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case 0x12: // ESCC compatible addressing
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if ((offset & 0xFF) < 0x0C) {
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value = this->escc->read(compat_to_macrisc[(offset >> 1) & 0xF]);
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break;
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}
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if ((offset & 0xFF) < 0x60) {
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value = 0;
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LOG_F(ERROR, "%s: ESCC compatible read @%x.%c", this->name.c_str(), offset, SIZE_ARG(size));
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break;
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}
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// fallthrough
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case 0x13: // ESCC MacRISC addressing
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value = this->escc->read((offset >> 4) & 0xF);
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break;
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case 0x14:
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value = this->snd_codec->snd_ctrl_read(offset & 0xFF, size);
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break;
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case 0x15: // SWIM3
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value = this->swim3->read((offset >> 4) & 0xF);
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break;
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case 0x16: // VIA-CUDA
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case 0x17:
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value = this->viacuda->read((offset >> 9) & 0xF);
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break;
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case 0x20: // IDE 0
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value = this->ide_0->read((offset >> 4) & 0x1F, size);
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break;
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case 0x21: // IDE 1
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value = this->ide_1->read((offset >> 4) & 0x1F, size);
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break;
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default:
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if (sub_addr >= 0x60) {
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value = this->nvram->read_byte((offset >> 4) & 0x1FFF);
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} else {
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value = 0;
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LOG_F(WARNING, "Attempting to read from unmapped I/O space: %x", offset);
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}
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}
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return value;
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}
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void HeathrowIC::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
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LOG_F(9, "%s: writing to offset %x", this->name.c_str(), offset);
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unsigned sub_addr = (offset >> 12) & 0x7F;
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switch (sub_addr) {
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case 0:
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this->mio_ctrl_write(offset, value, size);
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break;
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case 8:
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this->dma_write(offset & 0x7FFF, value, size);
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break;
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case 0x10: // SCSI
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this->mesh->write((offset >> 4) & 0xF, value);
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break;
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case 0x11: // Ethernet
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this->bmac->write(offset & 0xFFFU, BYTESWAP_SIZED(value, size));
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break;
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case 0x12: // ESCC compatible addressing
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if ((offset & 0xFF) < 0x0C) {
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this->escc->write(compat_to_macrisc[(offset >> 1) & 0xF], value);
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break;
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}
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if ((offset & 0xFF) < 0x60) {
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LOG_F(ERROR, "%s: SCC write @%x.%c = %0*x", this->name.c_str(),
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offset, SIZE_ARG(size), size * 2, value);
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break;
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}
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// fallthrough
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case 0x13: // ESCC MacRISC addressing
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this->escc->write((offset >> 4) & 0xF, value);
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break;
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case 0x14:
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this->snd_codec->snd_ctrl_write(offset & 0xFF, value, size);
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break;
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case 0x15: // SWIM3
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this->swim3->write((offset >> 4) & 0xF, value);
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break;
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case 0x16: // VIA-CUDA
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case 0x17:
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this->viacuda->write((offset >> 9) & 0xF, value);
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break;
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case 0x20: // IDE O
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this->ide_0->write((offset >> 4) & 0x1F, value, size);
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break;
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case 0x21: // IDE 1
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this->ide_1->write((offset >> 4) & 0x1F, value, size);
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break;
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default:
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if (sub_addr >= 0x60) {
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this->nvram->write_byte((offset - 0x60000) >> 4, value);
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} else {
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LOG_F(WARNING, "Attempting to write to unmapped I/O space: %x", offset);
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}
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}
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}
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uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
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uint32_t value;
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switch (offset & 0xFC) {
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case MIO_INT_EVENTS2:
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value = this->int_events >> 32;
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break;
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case MIO_INT_MASK2:
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value = this->int_mask >> 32;
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break;
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case MIO_INT_LEVELS2:
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value = this->int_levels >> 32;
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break;
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case MIO_INT_EVENTS1:
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value = uint32_t(this->int_events);
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break;
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case MIO_INT_MASK1:
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value = uint32_t(this->int_mask);
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break;
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case MIO_INT_LEVELS1:
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value = uint32_t(int_levels);
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break;
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case MIO_INT_CLEAR1:
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case MIO_INT_CLEAR2:
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// some Mac OS drivers reads from those write-only registers
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// so we return zero here as real HW does
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value = 0;
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break;
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case MIO_OHARE_ID:
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LOG_F(9, "read from MIO:ID register at Address %x", ppc_state.pc);
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value = (this->fp_id << 24) | (this->mon_id << 16) | (this->mb_id << 8) |
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(this->cpu_id | (this->emmo_pin << 4));
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break;
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case MIO_OHARE_FEAT_CTRL:
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LOG_F(9, "read from MIO:Feat_Ctrl register");
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value = this->feat_ctrl;
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break;
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default:
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value = 0;
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LOG_F(WARNING, "read from unknown MIO register at %x", offset);
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break;
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}
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return BYTESWAP_32(value);
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}
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void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
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switch (offset & 0xFC) {
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case MIO_INT_MASK2:
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this->int_mask |= uint64_t(BYTESWAP_32(value) & ~MACIO_INT_MODE) << 32;
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this->signal_cpu_int();
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break;
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case MIO_INT_CLEAR2:
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this->int_events &= ~(uint64_t(BYTESWAP_32(value) & 0x7FFFFFFFUL) << 32);
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clear_cpu_int();
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break;
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case MIO_INT_MASK1:
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this->int_mask = (this->int_mask & 0x7FFFFFFF00000000ULL) | BYTESWAP_32(value);
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// copy IntMode bit to InterruptMask2 register
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this->int_mask |= uint64_t(this->int_mask & MACIO_INT_MODE) << 32;
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this->signal_cpu_int();
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break;
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case MIO_INT_CLEAR1:
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if ((this->int_mask & MACIO_INT_MODE) && (value & MACIO_INT_CLR)) {
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this->int_events = 0;
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} else {
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this->int_events &= ~uint64_t(BYTESWAP_32(value) & 0x7FFFFFFFUL);
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}
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clear_cpu_int();
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break;
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case MIO_OHARE_ID:
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LOG_F(WARNING, "Attempted to write %x to MIO:ID at %x; Address : %x", value, offset, ppc_state.pc);
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break;
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case MIO_OHARE_FEAT_CTRL:
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this->feature_control(BYTESWAP_32(value));
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break;
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case MIO_AUX_CTRL:
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LOG_F(9, "write %x to MIO:Aux_Ctrl register", value);
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this->aux_ctrl = value;
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break;
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default:
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LOG_F(WARNING, "write %x to unknown MIO register at %x", value, offset);
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break;
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}
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}
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void HeathrowIC::feature_control(uint32_t value)
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{
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LOG_F(9, "write %x to MIO:Feat_Ctrl register", value);
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this->feat_ctrl = value;
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if (!(this->feat_ctrl & 1)) {
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LOG_F(9, "Heathrow: Monitor sense enabled");
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} else {
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LOG_F(9, "Heathrow: Monitor sense disabled");
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}
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}
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#define INT_TO_IRQ_ID(intx) (1ULL << intx)
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uint64_t HeathrowIC::register_dev_int(IntSrc src_id)
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{
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switch (src_id) {
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case IntSrc::SCSI_MESH : return INT_TO_IRQ_ID(0x0C);
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case IntSrc::IDE0 : return INT_TO_IRQ_ID(0x0D); // Beige G3 first IDE controller, or Yosemite ata-3
|
|
case IntSrc::IDE1 : return INT_TO_IRQ_ID(0x0E);
|
|
case IntSrc::SCCA : return INT_TO_IRQ_ID(0x0F);
|
|
case IntSrc::SCCB : return INT_TO_IRQ_ID(0x10);
|
|
case IntSrc::DAVBUS : return INT_TO_IRQ_ID(0x11);
|
|
case IntSrc::VIA_CUDA : return INT_TO_IRQ_ID(0x12);
|
|
case IntSrc::SWIM3 : return INT_TO_IRQ_ID(0x13);
|
|
case IntSrc::NMI : return INT_TO_IRQ_ID(0x14); // nmiSource in AppleHeathrow/Heathrow.cpp; programmer-switch in B&W G3
|
|
|
|
case IntSrc::PERCH2 : return INT_TO_IRQ_ID(0x15);
|
|
case IntSrc::PCI_GPU : return INT_TO_IRQ_ID(0x16);
|
|
case IntSrc::PCI_A : return INT_TO_IRQ_ID(0x17);
|
|
case IntSrc::PCI_B : return INT_TO_IRQ_ID(0x18);
|
|
case IntSrc::PCI_C : return INT_TO_IRQ_ID(0x19);
|
|
case IntSrc::PERCH1 : return INT_TO_IRQ_ID(0x1A);
|
|
case IntSrc::PCI_PERCH : return INT_TO_IRQ_ID(0x1C);
|
|
|
|
case IntSrc::FIREWIRE : return INT_TO_IRQ_ID(0x15); // Yosemite built-in PCI FireWire
|
|
case IntSrc::PCI_J12 : return INT_TO_IRQ_ID(0x16); // Yosemite 32-bit 66MHz slot for GPU
|
|
case IntSrc::PCI_J11 : return INT_TO_IRQ_ID(0x17); // Yosemite 64-bit 33MHz slot
|
|
case IntSrc::PCI_J10 : return INT_TO_IRQ_ID(0x18); // Yosemite 64-bit 33MHz slot
|
|
case IntSrc::PCI_J9 : return INT_TO_IRQ_ID(0x19); // Yosemite 64-bit 33MHz slot
|
|
case IntSrc::ATA : return INT_TO_IRQ_ID(0x1A); // Yosemite PCI pci-ata
|
|
case IntSrc::USB : return INT_TO_IRQ_ID(0x1C); // Yosemite PCI usb
|
|
|
|
case IntSrc::ETHERNET : return INT_TO_IRQ_ID(0x2A);
|
|
|
|
default:
|
|
ABORT_F("Heathrow: unknown interrupt source %d", src_id);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint64_t HeathrowIC::register_dma_int(IntSrc src_id)
|
|
{
|
|
switch (src_id) {
|
|
case IntSrc::DMA_SCSI_MESH : return INT_TO_IRQ_ID(0x00);
|
|
case IntSrc::DMA_SWIM3 : return INT_TO_IRQ_ID(0x01);
|
|
case IntSrc::DMA_IDE0 : return INT_TO_IRQ_ID(0x02);
|
|
case IntSrc::DMA_IDE1 : return INT_TO_IRQ_ID(0x03);
|
|
case IntSrc::DMA_SCCA_Tx : return INT_TO_IRQ_ID(0x04);
|
|
case IntSrc::DMA_SCCA_Rx : return INT_TO_IRQ_ID(0x05);
|
|
case IntSrc::DMA_SCCB_Tx : return INT_TO_IRQ_ID(0x06);
|
|
case IntSrc::DMA_SCCB_Rx : return INT_TO_IRQ_ID(0x07);
|
|
case IntSrc::DMA_DAVBUS_Tx : return INT_TO_IRQ_ID(0x08);
|
|
case IntSrc::DMA_DAVBUS_Rx : return INT_TO_IRQ_ID(0x09);
|
|
case IntSrc::DMA_ETHERNET_Tx : return INT_TO_IRQ_ID(0x20);
|
|
case IntSrc::DMA_ETHERNET_Rx : return INT_TO_IRQ_ID(0x21);
|
|
default:
|
|
ABORT_F("Heathrow: unknown DMA interrupt source %d", src_id);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void HeathrowIC::ack_int_common(uint64_t irq_id, uint8_t irq_line_state)
|
|
{
|
|
// native mode: set IRQ bits in int_events on a 0-to-1 transition
|
|
// emulated mode: set IRQ bits in int_events on all transitions
|
|
#if 0
|
|
LOG_F(INTERRUPT, "%s: native interrupt events:%08x.%08x levels:%08x.%08x change:%08x.%08x state:%d",
|
|
this->name.c_str(), uint32_t(this->int_events >> 32), uint32_t(this->int_events), uint32_t(this->int_levels >> 32),
|
|
uint32_t(this->int_levels), uint32_t(irq_id >> 32), uint32_t(irq_id), irq_line_state
|
|
);
|
|
#endif
|
|
if ((this->int_mask & MACIO_INT_MODE) ||
|
|
(irq_line_state && !(this->int_levels & irq_id))) {
|
|
this->int_events |= irq_id;
|
|
} else {
|
|
this->int_events &= ~irq_id;
|
|
}
|
|
// update IRQ line state
|
|
if (irq_line_state) {
|
|
this->int_levels |= irq_id;
|
|
} else {
|
|
this->int_levels &= ~irq_id;
|
|
}
|
|
|
|
this->signal_cpu_int();
|
|
}
|
|
|
|
void HeathrowIC::ack_int(uint64_t irq_id, uint8_t irq_line_state)
|
|
{
|
|
this->ack_int_common(irq_id, irq_line_state);
|
|
}
|
|
|
|
void HeathrowIC::ack_dma_int(uint64_t irq_id, uint8_t irq_line_state)
|
|
{
|
|
this->ack_int_common(irq_id, irq_line_state);
|
|
}
|
|
|
|
void HeathrowIC::signal_cpu_int() {
|
|
if (this->int_events & this->int_mask) {
|
|
if (!this->cpu_int_latch) {
|
|
this->cpu_int_latch = true;
|
|
ppc_assert_int();
|
|
} else {
|
|
LOG_F(5, "%s: CPU INT already latched", this->name.c_str());
|
|
}
|
|
}
|
|
}
|
|
|
|
void HeathrowIC::clear_cpu_int()
|
|
{
|
|
if (!(this->int_events & this->int_mask) && this->cpu_int_latch) {
|
|
this->cpu_int_latch = false;
|
|
ppc_release_int();
|
|
LOG_F(5, "Heathrow: CPU INT latch cleared");
|
|
}
|
|
}
|
|
|
|
static const vector<string> Heathrow_Subdevices = {
|
|
"NVRAM", "ViaCuda", "ScsiMesh", "MeshHeathrow", "Escc", "Swim3", "Ide0", "Ide1",
|
|
"BigMacHeathrow"
|
|
};
|
|
|
|
static const DeviceDescription Heathrow_Descriptor = {
|
|
HeathrowIC::create, Heathrow_Subdevices, {}
|
|
};
|
|
|
|
REGISTER_DEVICE(Heathrow, Heathrow_Descriptor);
|