Sync with ARAnyM compiler sources

BasiliskII/src/Unix/main_unix.cpp

@@ -57,7 +57,7 @@ using std::string;
 #include "sigsegv.h"
 
 #if USE_JIT
-extern void flush_icache_range(uint8 *start, uint32 size); // from compemu_support.cpp
+extern void (*flush_icache)(void); // from compemu_support.cpp
 #endif
 
 
@@ -542,7 +542,7 @@ void FlushCodeCache(void *start, uint32 size)
 {
 #if USE_JIT
     if (UseJIT)
-		flush_icache_range((uint8 *)start, size);
+		flush_icache();
 #endif
 }
 

BasiliskII/src/Unix/timer_unix.cpp

@@ -22,9 +22,9 @@
 #include "macos_util.h"
 #include "timer.h"
 
-// #ifdef USE_SDL
+#ifdef USE_SDL
-// # include <SDL.h>
+# include <SDL.h>
-// #endif
+#endif
 
 #include <errno.h>
 
@@ -341,19 +341,19 @@ void Delay_usec(uint32 usec)
 // #endif
 // #endif
 
-// SDL_mutex *idle_lock;
+SDL_mutex *idle_lock;
-// SDL_cond *idle_cond;
+SDL_cond *idle_cond;
 
 void idle_wait(void)
 {
 	//This causes events to not process randomly in JIT so commented out
-	// if (!idle_lock)
+	if (!idle_lock)
-	// 	idle_lock = SDL_CreateMutex();
+		idle_lock = SDL_CreateMutex();
-	// if (!idle_cond)
+	if (!idle_cond)
-	// 	idle_cond = SDL_CreateCond();
+		idle_cond = SDL_CreateCond();
-	// SDL_LockMutex(idle_lock);
+	SDL_LockMutex(idle_lock);
-	// SDL_CondWait(idle_cond, idle_lock);
+	SDL_CondWait(idle_cond, idle_lock);
-	// SDL_UnlockMutex(idle_lock);
+	SDL_UnlockMutex(idle_lock);
 
 // #ifdef IDLE_USES_COND_WAIT
 // 	pthread_mutex_lock(&idle_lock);
@@ -386,8 +386,8 @@ void idle_wait(void)
 void idle_resume(void)
 {
 	//This causes events to not process randomly in JIT so commented out
-	// if (idle_cond)
+	if (idle_cond)
-	// 	SDL_CondSignal(idle_cond);
+		SDL_CondSignal(idle_cond);
 // #ifdef IDLE_USES_COND_WAIT
 // 	pthread_cond_signal(&idle_cond);
 // #else

BasiliskII/src/uae_cpu/compiler/codegen_arm.h

@@ -66,22 +66,22 @@
 /* --- ENCODINGS ----------------------------------------------------------- */
 /* ========================================================================= */
 
-#define IMM32(c) ((c & 0xffffff00) == 0 ? c : \
+#define IMM32(c) (((c) & 0xffffff00) == 0 ? (c) : \
-                  (c & 0x3fffffc0) == 0 ? (0x100 | ((c >> 30) & 0x3) | ((c << 2) & 0xfc)) : \
+                  ((c) & 0x3fffffc0) == 0 ? (0x100 | (((c) >> 30) & 0x3) | ((((c) & 0x0000003f) << 2))) : \
-                  (c & 0x0ffffff0) == 0 ? (0x200 | ((c >> 28) & 0xf) | ((c << 4) & 0xf0)) : \
+                  ((c) & 0x0ffffff0) == 0 ? (0x200 | (((c) >> 28) & 0xf) | ((((c) & 0x0000000f) << 4))) : \
-                  (c & 0x03fffffc) == 0 ? (0x300 | ((c >> 26) & 0x3f) | ((c << 6) & 0xc0) ) : \
+                  ((c) & 0x03fffffc) == 0 ? (0x300 | (((c) >> 26) & 0x3f) | ((((c) & 0x00000003) << 6)) ) : \
-                  (c & 0x00ffffff) == 0 ? (0x400 | ((c >> 24) & 0xff)) : \
+                  ((c) & 0x00ffffff) == 0 ? (0x400 | (((c) >> 24) & 0xff)) : \
-                  (c & 0xc03fffff) == 0 ? (0x500 | (c >> 22)) : \
+                  ((c) & 0xc03fffff) == 0 ? (0x500 | ((c) >> 22)) : \
-                  (c & 0xf00fffff) == 0 ? (0x600 | (c >> 20)) : \
+                  ((c) & 0xf00fffff) == 0 ? (0x600 | ((c) >> 20)) : \
-                  (c & 0xfc03ffff) == 0 ? (0x700 | (c >> 18)) : \
+                  ((c) & 0xfc03ffff) == 0 ? (0x700 | ((c) >> 18)) : \
-                  (c & 0xff00ffff) == 0 ? (0x800 | (c >> 16)) : \
+                  ((c) & 0xff00ffff) == 0 ? (0x800 | ((c) >> 16)) : \
-                  (c & 0xffc03fff) == 0 ? (0x900 | (c >> 14)) : \
+                  ((c) & 0xffc03fff) == 0 ? (0x900 | ((c) >> 14)) : \
-                  (c & 0xfff00fff) == 0 ? (0xa00 | (c >> 12)) : \
+                  ((c) & 0xfff00fff) == 0 ? (0xa00 | ((c) >> 12)) : \
-                  (c & 0xfffc03ff) == 0 ? (0xb00 | (c >> 10)) : \
+                  ((c) & 0xfffc03ff) == 0 ? (0xb00 | ((c) >> 10)) : \
-                  (c & 0xffff00ff) == 0 ? (0xc00 | (c >> 8)) : \
+                  ((c) & 0xffff00ff) == 0 ? (0xc00 | ((c) >> 8)) : \
-                  (c & 0xffffc03f) == 0 ? (0xd00 | (c >> 6)) : \
+                  ((c) & 0xffffc03f) == 0 ? (0xd00 | ((c) >> 6)) : \
-                  (c & 0xfffff00f) == 0 ? (0xe00 | (c >> 4)) : \
+                  ((c) & 0xfffff00f) == 0 ? (0xe00 | ((c) >> 4)) : \
-                  (c & 0xfffffc03) == 0 ? (0xf00 | (c >> 2)) : \
+                  ((c) & 0xfffffc03) == 0 ? (0xf00 | ((c) >> 2)) : \
                         0\
                  )
 
@@ -102,7 +102,7 @@
 #define SHIFT_RRX(Rm) ((Rm) | 0x60)
 #define SHIFT_PK(Rm,s) ((Rm) | ((s) << 7))
 
-// Load/Store addressings
+/* Load/Store addressings */
 #define ADR_ADD(v) ((1 << 23) | (v))
 #define ADR_SUB(v) (v)
 
@@ -138,16 +138,16 @@
 #define ADD2_REG(Rm)	ADR_ADD(Rm)
 #define SUB2_REG(Rm)	ADR_SUB(Rm)
 
-// MOV, MVN
+/* MOV, MVN */
 #define _OP1(cc,op,s,Rd,shift) _W(((cc) << 28) | ((op) << 21) | ((s) << 20) | ((Rd) << 12) | (shift))
 
-// CMP, CMN, TST, TEQ
+/* CMP, CMN, TST, TEQ */
 #define _OP2(cc,op,Rn,shift) _W(((cc) << 28) | ((op) << 21) | (1 << 20) | ((Rn) << 16) | (shift))
 
-// ADD, SUB, RSB, ADC, SBC, RSC, AND, BIC, EOR, ORR
+/* ADD, SUB, RSB, ADC, SBC, RSC, AND, BIC, EOR, ORR */
 #define _OP3(cc,op,s,Rd,Rn,shift) _W(((cc) << 28) | ((op) << 21) | ((s) << 20) | ((Rn) << 16) | ((Rd) << 12) | (shift))
 
-// LDR, STR
+/* LDR, STR */
 #define _LS1(cc,l,b,Rd,Rn,a) _W(((cc) << 28) | (0x01 << 26) | ((l) << 20) | ((b) << 22) | ((Rn) << 16) | ((Rd) << 12) | (a))
 #define _LS2(cc,p,l,s,h,Rd,Rn,a) _W(((cc) << 28) | ((p) << 24) | ((l) << 20) | ((Rn) << 16) | ((Rd) << 12) | ((s) << 6) | ((h) << 5) | 0x90 | _LS2_ADDR((a)))
 
@@ -211,9 +211,9 @@ enum {
 /* Data processing instructions */
 
 /* Opcodes Type 1 */
-// MOVcc rd,#i
+/* MOVcc rd,#i */
 #define CC_MOV_ri8(cc,Rd,i)                 _OP1(cc,_MOV,0,Rd,UNSHIFTED_IMM8(i))
-// MOVcc Rd,#i ROR #s
+/* MOVcc Rd,#i ROR #s */
 #define CC_MOV_ri8RORi(cc,Rd,i,s)           _OP1(cc,_MOV,0,Rd,SHIFT_IMM8_ROR(i,s))
 #define CC_MOV_ri(cc,Rd,i)                  _OP1(cc,_MOV,0,Rd,SHIFT_IMM(i))
 #define CC_MOV_rr(cc,Rd,Rm)                 _OP1(cc,_MOV,0,Rd,SHIFT_REG(Rm))
@@ -227,9 +227,9 @@ enum {
 #define CC_MOV_rrRORr(cc,Rd,Rm,Rs)          _OP1(cc,_MOV,0,Rd,SHIFT_ROR_r(Rm,Rs))
 #define CC_MOV_rrRRX(cc,Rd,Rm)              _OP1(cc,_MOV,0,Rd,SHIFT_RRX(Rm))
 
-// MOV rd,#i
+/* MOV rd,#i */
 #define MOV_ri8(Rd,i)                       CC_MOV_ri8(NATIVE_CC_AL,Rd,i)
-// MOV Rd,#i ROR #s
+/* MOV Rd,#i ROR #s */
 #define MOV_ri8RORi(Rd,i,s)                 CC_MOV_ri8RORi(NATIVE_CC_AL,Rd,i,s)
 #define MOV_ri(Rd,i)                        CC_MOV_ri(NATIVE_CC_AL,Rd,i)
 #define MOV_rr(Rd,Rm)                       CC_MOV_rr(NATIVE_CC_AL,Rd,Rm)
@@ -267,9 +267,9 @@ enum {
 #define MOVS_rrRORr(Rd,Rm,Rs)               CC_MOVS_rrRORr(NATIVE_CC_AL,Rd,Rm,Rs)
 #define MOVS_rrRRX(Rd,Rm)                   CC_MOVS_rrRRX(NATIVE_CC_AL,Rd,Rm)
 
-// MVNcc rd,#i
+/* MVNcc rd,#i */
 #define CC_MVN_ri8(cc,Rd,i)                 _OP1(cc,_MVN,0,Rd,UNSHIFTED_IMM8(i))
-// MVNcc Rd,#i ROR #s
+/* MVNcc Rd,#i ROR #s */
 #define CC_MVN_ri8RORi(cc,Rd,i,s)           _OP1(cc,_MVN,0,Rd,SHIFT_IMM8_ROR(i,s))
 #define CC_MVN_ri(cc,Rd,i)              	_OP1(cc,_MVN,0,Rd,SHIFT_IMM(i))
 #define CC_MVN_rr(cc,Rd,Rm)             	_OP1(cc,_MVN,0,Rd,SHIFT_REG(Rm))
@@ -283,9 +283,9 @@ enum {
 #define CC_MVN_rrRORr(cc,Rd,Rm,Rs)      	_OP1(cc,_MVN,0,Rd,SHIFT_ROR_r(Rm,Rs))
 #define CC_MVN_rrRRX(cc,Rd,Rm)           	_OP1(cc,_MVN,0,Rd,SHIFT_RRX(Rm))
 
-// MVN rd,#i
+/* MVN rd,#i */
 #define MVN_ri8(Rd,i)                       CC_MVN_ri8(NATIVE_CC_AL,Rd,i)
-// MVN Rd,#i ROR #s
+/* MVN Rd,#i ROR #s */
 #define MVN_ri8RORi(Rd,i,s)                 CC_MVN_ri8RORi(NATIVE_CC_AL,Rd,i,s)
 #define MVN_ri(Rd,i)                        CC_MVN_ri(NATIVE_CC_AL,Rd,i)
 #define MVN_rr(Rd,Rm)                       CC_MVN_rr(NATIVE_CC_AL,Rd,Rm)
@@ -811,9 +811,9 @@ enum {
 #define RSCS_rrrRORr(Rd,Rn,Rm,Rs)       	CC_RSCS_rrrRORr(NATIVE_CC_AL,Rd,Rn,Rm,Rs)
 #define RSCS_rrrRRX(Rd,Rn,Rm)           	CC_RSCS_rrrRRX(NATIVE_CC_AL,Rd,Rn,Rm)
 
-// ORRcc Rd,Rn,#i
+/* ORRcc Rd,Rn,#i */
 #define CC_ORR_rri8(cc,Rd,Rn,i)          	_OP3(cc,_ORR,0,Rd,Rn,UNSHIFTED_IMM8(i))
-// ORRcc Rd,Rn,#i ROR #s
+/* ORRcc Rd,Rn,#i ROR #s */
 #define CC_ORR_rri8RORi(cc,Rd,Rn,i,s)      	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_IMM8_ROR(i,s))
 
 #define CC_ORR_rri(cc,Rd,Rn,i)          	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_IMM(i))
@@ -828,9 +828,9 @@ enum {
 #define CC_ORR_rrrRORr(cc,Rd,Rn,Rm,Rs)  	_OP3(cc,_ORR,0,Rd,Rn,SHIFT_ROR_r(Rm,Rs))
 #define CC_ORR_rrrRRX(cc,Rd,Rn,Rm)     		_OP3(cc,_ORR,0,Rd,Rn,SHIFT_RRX(Rm))
 
-// ORR Rd,Rn,#i
+/* ORR Rd,Rn,#i */
 #define ORR_rri8(Rd,Rn,i)          			CC_ORR_rri8(NATIVE_CC_AL,Rd,Rn,i)
-// ORR Rd,Rn,#i ROR #s
+/* ORR Rd,Rn,#i ROR #s */
 #define ORR_rri8RORi(Rd,Rn,i,s)      		CC_ORR_rri8RORi(NATIVE_CC_AL,Rd,Rn,i,s)
 
 #define ORR_rri(Rd,Rn,i)                	CC_ORR_rri(NATIVE_CC_AL,Rd,Rn,i)

BasiliskII/src/uae_cpu/compiler/codegen_x86.h

@@ -402,22 +402,54 @@ typedef unsigned int	_ul;
 /* --- Memory subformats - urgh! ------------------------------------------- */
 
 /* _r_D() is RIP addressing mode if X86_TARGET_64BIT, use _r_DSIB() instead */
-#define _r_D(	R, D	  )	(_Mrm(_b00,_rN(R),_b101 )		             ,_L((long)(D)))
+#define _r_D(	R, D	  )	(_Mrm(_b00,_rN(R),_b101 )		             ,_L((uae_u32)(D)))
-#define _r_DSIB(R, D      )	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(1),_b100 ,_b101 ),_L((long)(D)))
+#define _r_DSIB(R, D      )	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(1),_b100 ,_b101 ),_L((uae_u32)(D)))
 #define _r_0B(	R,   B    )	(_Mrm(_b00,_rN(R),_rA(B))			                   )
 #define _r_0BIS(R,   B,I,S)	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B))              )
-#define _r_1B(	R, D,B    )	(_Mrm(_b01,_rN(R),_rA(B))		             ,_B((long)(D)))
+#define _r_1B(	R, D,B    )	(_Mrm(_b01,_rN(R),_rA(B))		             ,_B((uae_u32)(D)))
-#define _r_1BIS(R, D,B,I,S)	(_Mrm(_b01,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_B((long)(D)))
+#define _r_1BIS(R, D,B,I,S)	(_Mrm(_b01,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_B((uae_u32)(D)))
-#define _r_4B(	R, D,B    )	(_Mrm(_b10,_rN(R),_rA(B))		             ,_L((long)(D)))
+#define _r_4B(	R, D,B    )	(_Mrm(_b10,_rN(R),_rA(B))		             ,_L((uae_u32)(D)))
-#define _r_4IS( R, D,I,S)	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_b101 ),_L((long)(D)))
+#define _r_4IS( R, D,I,S)	(_Mrm(_b00,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_b101 ),_L((uae_u32)(D)))
-#define _r_4BIS(R, D,B,I,S)	(_Mrm(_b10,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_L((long)(D)))
+#define _r_4BIS(R, D,B,I,S)	(_Mrm(_b10,_rN(R),_b100 ),_SIB(_SCL(S),_rA(I),_rA(B)),_L((uae_u32)(D)))
 
 #define _r_DB(  R, D,B    )	((_s0P(D) && (!_rbp13P(B)) ? _r_0B  (R,  B    ) : (_s8P(D) ? _r_1B(  R,D,B    ) : _r_4B(  R,D,B    ))))
 #define _r_DBIS(R, D,B,I,S)	((_s0P(D) && (!_rbp13P(B)) ? _r_0BIS(R,  B,I,S) : (_s8P(D) ? _r_1BIS(R,D,B,I,S) : _r_4BIS(R,D,B,I,S))))
 
 /* Use RIP-addressing in 64-bit mode, if possible */
-#define _x86_RIP_addressing_possible(D,O)	(X86_RIP_RELATIVE_ADDR && \
+#define _x86_RIP_addressing_possible(D,O)	(X86_RIP_RELATIVE_ADDR && x86_RIP_addressing_possible(D, O))
-						((uintptr)x86_get_target() + 4 + (O) - (D) <= 0xffffffff))
+
+static inline int x86_RIP_addressing_possible(uintptr addr, uintptr offset)
+{
+#if X86_TARGET_64BIT
+	/*
+	 * address of the next instruction.
+	 * The opcode has already been emmitted,
+	 * so this is the size of an 32bit displacement +
+	 * the size of any immediate value that is part of the instruction (offset),
+	 */
+	uintptr dst = (uintptr)get_target() + 4 + offset;
+	intptr disp = dst - addr;
+	int ok = disp >= -0x80000000LL && disp <= 0x7fffffffLL;
+	/* fprintf(stderr, "x86_RIP_addressing_possible: %llx - %llx %16llx = %d\n", (unsigned long long)dst, (unsigned long long)addr, (long long)disp, ok); */
+	return ok;
+#else
+	UNUSED(addr);
+	UNUSED(offset);
+	return 0;
+#endif
+}
+
+
+static inline int x86_DISP32_addressing_possible(uintptr addr)
+{
+#if X86_TARGET_64BIT
+	return addr <= 0xFFFFFFFFULL;
+#else
+	UNUSED(addr);
+	return 1;
+#endif
+}
+
 
 #define _r_X(   R, D,B,I,S,O)	(_r0P(I) ? (_r0P(B)    ? (!X86_TARGET_64BIT ? _r_D(R,D) : \
 					                 (_x86_RIP_addressing_possible(D, O) ? \

BasiliskII/src/uae_cpu/compiler/compemu.h

@@ -35,11 +35,6 @@
 // #include "sysconfig.h"
 #include "newcpu.h"
 
-#ifdef __x86_64__
-#define CPU_64_BIT 1
-#define CPU_x86_64 1
-#endif
-
 #ifdef UAE
 #ifdef CPU_64_BIT
 typedef uae_u64 uintptr;
@@ -135,11 +130,19 @@ union cacheline {
 			  for jump targets */
 
 #define INDIVIDUAL_INST 0
+#ifdef WINUAE_ARANYM
 #define FLAG_X    0x0010
 #define FLAG_N    0x0008
 #define FLAG_Z    0x0004
 #define FLAG_V    0x0002
 #define FLAG_C    0x0001
+#else
+#define FLAG_C    0x0010
+#define FLAG_V    0x0008
+#define FLAG_Z    0x0004
+#define FLAG_N    0x0002
+#define FLAG_X    0x0001
+#endif
 #define FLAG_CZNV (FLAG_C | FLAG_Z | FLAG_N | FLAG_V)
 #define FLAG_ALL  (FLAG_C | FLAG_Z | FLAG_N | FLAG_V | FLAG_X)
 #define FLAG_ZNV  (FLAG_Z | FLAG_N | FLAG_V)
@@ -165,27 +168,74 @@ extern void compiler_init(void);
 extern void compiler_exit(void);
 extern bool compiler_use_jit(void);
 #endif
-extern void init_comp(void);
 extern void flush(int save_regs);
-extern void small_flush(int save_regs);
 extern void set_target(uae_u8* t);
 extern uae_u8* get_target(void);
-extern void freescratch(void);
+#ifdef UAE
 extern void build_comp(void);
+#endif
 extern void set_cache_state(int enabled);
 extern int get_cache_state(void);
 extern uae_u32 get_jitted_size(void);
 #ifdef JIT
-#ifdef WINUAE_ARANYM
+extern void (*flush_icache)(void);
-extern void (*flush_icache)(int n);
-#else
-extern void flush_icache(int n);
-#endif
 #endif
 extern void alloc_cache(void);
 extern int check_for_cache_miss(void);
 
 /* JIT FPU compilation */
+struct jit_disable_opcodes {
+	bool fbcc;
+	bool fdbcc;
+	bool fscc;
+	bool ftrapcc;
+	bool fsave;
+	bool frestore;
+	bool fmove;
+	bool fmovem;
+	bool fmovec;  /* for move control register */
+	bool fmovecr; /* for move from constant rom */
+	bool fint;
+	bool fsinh;
+	bool fintrz;
+	bool fsqrt;
+	bool flognp1;
+	bool fetoxm1;
+	bool ftanh;
+	bool fatan;
+	bool fasin;
+	bool fatanh;
+	bool fsin;
+	bool ftan;
+	bool fetox;
+	bool ftwotox;
+	bool ftentox;
+	bool flogn;
+	bool flog10;
+	bool flog2;
+	bool fabs;
+	bool fcosh;
+	bool fneg;
+	bool facos;
+	bool fcos;
+	bool fgetexp;
+	bool fgetman;
+	bool fdiv;
+	bool fmod;
+	bool fadd;
+	bool fmul;
+	bool fsgldiv;
+	bool frem;
+	bool fscale;
+	bool fsglmul;
+	bool fsub;
+	bool fsincos;
+	bool fcmp;
+	bool ftst;
+};
+extern struct jit_disable_opcodes jit_disable;
+
+
 extern void comp_fpp_opp (uae_u32 opcode, uae_u16 extra);
 extern void comp_fbcc_opp (uae_u32 opcode);
 extern void comp_fscc_opp (uae_u32 opcode, uae_u16 extra);
@@ -320,18 +370,20 @@ extern int touchcnt;
 #define RW4 uae_u32
 #define MEMR uae_u32
 #define MEMW uae_u32
-#define MEMRW uae_u32
+#define MEMRW    uae_u32
+#define MEMPTR   uintptr
+#define MEMPTRR  MEMPTR
+#define MEMPTRW  MEMPTR
+#define MEMPTRRW MEMPTR
 
 #define FW   uae_u32
 #define FR   uae_u32
 #define FRW  uae_u32
 
 #define MIDFUNC(nargs,func,args) void func args
-#define MENDFUNC(nargs,func,args)
 #define COMPCALL(func) func
 
 #define LOWFUNC(flags,mem,nargs,func,args) static inline void func args
-#define LENDFUNC(flags,mem,nargs,func,args)
 
 /* What we expose to the outside */
 #define DECLARE_MIDFUNC(func) extern void func
@@ -456,8 +508,7 @@ void do_nothing(void);
 
 #else
 
-static inline void flush_icache(int) { }
+static inline void flush_icache(void) { }
-static inline void build_comp() { }
 
 #endif /* !USE_JIT */
 
@@ -520,7 +571,7 @@ void jit_abort(const TCHAR *format, ...);
 #else
 
 #ifdef WINUAE_ARANYM
-#define jit_log(format, ...) write_log(format"\n", ##__VA_ARGS__)
+#define jit_log(format, ...) D(bug(format, ##__VA_ARGS__))
 #define jit_log2(format, ...) D2(bug(format, ##__VA_ARGS__))
 void jit_abort(const char *format,...) __attribute__((format(printf, 1, 2))) __attribute__((__noreturn__));
 #else

BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.cpp

@@ -61,13 +61,11 @@ MIDFUNC(0,live_flags,(void))
 	live.flags_in_flags=VALID;
 	live.flags_are_important=1;
 }
-MENDFUNC(0,live_flags,(void))
 
 MIDFUNC(0,dont_care_flags,(void))
 {
 	live.flags_are_important=0;
 }
-MENDFUNC(0,dont_care_flags,(void))
 
 MIDFUNC(0,duplicate_carry,(void))
 {
@@ -76,7 +74,6 @@ MIDFUNC(0,duplicate_carry,(void))
 	COMPCALL(setcc_m)((uintptr)live.state[FLAGX].mem,NATIVE_CC_CS);
 	log_vwrite(FLAGX);
 }
-MENDFUNC(0,duplicate_carry,(void))
 
 MIDFUNC(0,restore_carry,(void))
 {
@@ -100,25 +97,21 @@ MIDFUNC(0,restore_carry,(void))
 	}
 #endif
 }
-MENDFUNC(0,restore_carry,(void))
 
 MIDFUNC(0,start_needflags,(void))
 {
 	needflags=1;
 }
-MENDFUNC(0,start_needflags,(void))
 
 MIDFUNC(0,end_needflags,(void))
 {
 	needflags=0;
 }
-MENDFUNC(0,end_needflags,(void))
 
 MIDFUNC(0,make_flags_live,(void))
 {
 	make_flags_live_internal();
 }
-MENDFUNC(0,make_flags_live,(void))
 
 MIDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */
 {
@@ -130,7 +123,6 @@ MIDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */
 	raw_bt_l_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,bt_l_ri,(RR4 r, IMM i)) /* This is defined as only affecting C */
 
 MIDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */
 {
@@ -141,7 +133,6 @@ MIDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */
 	unlock2(r);
 	unlock2(b);
 }
-MENDFUNC(2,bt_l_rr,(RR4 r, RR4 b)) /* This is defined as only affecting C */
 
 MIDFUNC(2,btc_l_rr,(RW4 r, RR4 b))
 {
@@ -152,7 +143,6 @@ MIDFUNC(2,btc_l_rr,(RW4 r, RR4 b))
 	unlock2(r);
 	unlock2(b);
 }
-MENDFUNC(2,btc_l_rr,(RW4 r, RR4 b))
 
 MIDFUNC(2,btr_l_rr,(RW4 r, RR4 b))
 {
@@ -163,7 +153,6 @@ MIDFUNC(2,btr_l_rr,(RW4 r, RR4 b))
 	unlock2(r);
 	unlock2(b);
 }
-MENDFUNC(2,btr_l_rr,(RW4 r, RR4 b))
 
 MIDFUNC(2,bts_l_rr,(RW4 r, RR4 b))
 {
@@ -174,7 +163,6 @@ MIDFUNC(2,bts_l_rr,(RW4 r, RR4 b))
 	unlock2(r);
 	unlock2(b);
 }
-MENDFUNC(2,bts_l_rr,(RW4 r, RR4 b))
 
 MIDFUNC(2,mov_l_rm,(W4 d, IMM s))
 {
@@ -183,7 +171,6 @@ MIDFUNC(2,mov_l_rm,(W4 d, IMM s))
 	raw_mov_l_rm(d,s);
 	unlock2(d);
 }
-MENDFUNC(2,mov_l_rm,(W4 d, IMM s))
 
 MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor))
 {
@@ -194,28 +181,24 @@ MIDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor))
 	unlock2(index);
 	unlock2(d);
 }
-MENDFUNC(4,mov_l_rm_indexed,(W4 d, IMM base, RR4 index, IMM factor))
 
 MIDFUNC(2,mov_l_mi,(IMM d, IMM s))
 {
 	CLOBBER_MOV;
 	raw_mov_l_mi(d,s);
 }
-MENDFUNC(2,mov_l_mi,(IMM d, IMM s))
 
 MIDFUNC(2,mov_w_mi,(IMM d, IMM s))
 {
 	CLOBBER_MOV;
 	raw_mov_w_mi(d,s);
 }
-MENDFUNC(2,mov_w_mi,(IMM d, IMM s))
 
 MIDFUNC(2,mov_b_mi,(IMM d, IMM s))
 {
 	CLOBBER_MOV;
 	raw_mov_b_mi(d,s);
 }
-MENDFUNC(2,mov_b_mi,(IMM d, IMM s))
 
 MIDFUNC(2,rol_b_ri,(RW1 r, IMM i))
 {
@@ -226,7 +209,6 @@ MIDFUNC(2,rol_b_ri,(RW1 r, IMM i))
 	raw_rol_b_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,rol_b_ri,(RW1 r, IMM i))
 
 MIDFUNC(2,rol_w_ri,(RW2 r, IMM i))
 {
@@ -237,7 +219,6 @@ MIDFUNC(2,rol_w_ri,(RW2 r, IMM i))
 	raw_rol_w_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,rol_w_ri,(RW2 r, IMM i))
 
 MIDFUNC(2,rol_l_ri,(RW4 r, IMM i))
 {
@@ -248,7 +229,6 @@ MIDFUNC(2,rol_l_ri,(RW4 r, IMM i))
 	raw_rol_l_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,rol_l_ri,(RW4 r, IMM i))
 
 MIDFUNC(2,rol_l_rr,(RW4 d, RR1 r))
 {
@@ -263,7 +243,6 @@ MIDFUNC(2,rol_l_rr,(RW4 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,rol_l_rr,(RW4 d, RR1 r))
 
 MIDFUNC(2,rol_w_rr,(RW2 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -279,7 +258,6 @@ MIDFUNC(2,rol_w_rr,(RW2 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,rol_w_rr,(RW2 d, RR1 r))
 
 MIDFUNC(2,rol_b_rr,(RW1 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -295,7 +273,6 @@ MIDFUNC(2,rol_b_rr,(RW1 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,rol_b_rr,(RW1 d, RR1 r))
 
 MIDFUNC(2,shll_l_rr,(RW4 d, RR1 r))
 {
@@ -310,7 +287,6 @@ MIDFUNC(2,shll_l_rr,(RW4 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shll_l_rr,(RW4 d, RR1 r))
 
 MIDFUNC(2,shll_w_rr,(RW2 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -326,7 +302,6 @@ MIDFUNC(2,shll_w_rr,(RW2 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shll_w_rr,(RW2 d, RR1 r))
 
 MIDFUNC(2,shll_b_rr,(RW1 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -342,7 +317,6 @@ MIDFUNC(2,shll_b_rr,(RW1 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shll_b_rr,(RW1 d, RR1 r))
 
 MIDFUNC(2,ror_b_ri,(RR1 r, IMM i))
 {
@@ -353,7 +327,6 @@ MIDFUNC(2,ror_b_ri,(RR1 r, IMM i))
 	raw_ror_b_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,ror_b_ri,(RR1 r, IMM i))
 
 MIDFUNC(2,ror_w_ri,(RR2 r, IMM i))
 {
@@ -364,7 +337,6 @@ MIDFUNC(2,ror_w_ri,(RR2 r, IMM i))
 	raw_ror_w_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,ror_w_ri,(RR2 r, IMM i))
 
 MIDFUNC(2,ror_l_ri,(RR4 r, IMM i))
 {
@@ -375,7 +347,6 @@ MIDFUNC(2,ror_l_ri,(RR4 r, IMM i))
 	raw_ror_l_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,ror_l_ri,(RR4 r, IMM i))
 
 MIDFUNC(2,ror_l_rr,(RR4 d, RR1 r))
 {
@@ -390,7 +361,6 @@ MIDFUNC(2,ror_l_rr,(RR4 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,ror_l_rr,(RR4 d, RR1 r))
 
 MIDFUNC(2,ror_w_rr,(RR2 d, RR1 r))
 {
@@ -405,7 +375,6 @@ MIDFUNC(2,ror_w_rr,(RR2 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,ror_w_rr,(RR2 d, RR1 r))
 
 MIDFUNC(2,ror_b_rr,(RR1 d, RR1 r))
 {
@@ -421,7 +390,6 @@ MIDFUNC(2,ror_b_rr,(RR1 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,ror_b_rr,(RR1 d, RR1 r))
 
 MIDFUNC(2,shrl_l_rr,(RW4 d, RR1 r))
 {
@@ -436,7 +404,6 @@ MIDFUNC(2,shrl_l_rr,(RW4 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shrl_l_rr,(RW4 d, RR1 r))
 
 MIDFUNC(2,shrl_w_rr,(RW2 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -452,7 +419,6 @@ MIDFUNC(2,shrl_w_rr,(RW2 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shrl_w_rr,(RW2 d, RR1 r))
 
 MIDFUNC(2,shrl_b_rr,(RW1 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -469,7 +435,6 @@ MIDFUNC(2,shrl_b_rr,(RW1 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shrl_b_rr,(RW1 d, RR1 r))
 
 MIDFUNC(2,shll_l_ri,(RW4 r, IMM i))
 {
@@ -484,7 +449,6 @@ MIDFUNC(2,shll_l_ri,(RW4 r, IMM i))
 	raw_shll_l_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shll_l_ri,(RW4 r, IMM i))
 
 MIDFUNC(2,shll_w_ri,(RW2 r, IMM i))
 {
@@ -495,7 +459,6 @@ MIDFUNC(2,shll_w_ri,(RW2 r, IMM i))
 	raw_shll_w_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shll_w_ri,(RW2 r, IMM i))
 
 MIDFUNC(2,shll_b_ri,(RW1 r, IMM i))
 {
@@ -506,7 +469,6 @@ MIDFUNC(2,shll_b_ri,(RW1 r, IMM i))
 	raw_shll_b_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shll_b_ri,(RW1 r, IMM i))
 
 MIDFUNC(2,shrl_l_ri,(RW4 r, IMM i))
 {
@@ -521,7 +483,6 @@ MIDFUNC(2,shrl_l_ri,(RW4 r, IMM i))
 	raw_shrl_l_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shrl_l_ri,(RW4 r, IMM i))
 
 MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i))
 {
@@ -532,7 +493,6 @@ MIDFUNC(2,shrl_w_ri,(RW2 r, IMM i))
 	raw_shrl_w_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shrl_w_ri,(RW2 r, IMM i))
 
 MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i))
 {
@@ -543,7 +503,6 @@ MIDFUNC(2,shrl_b_ri,(RW1 r, IMM i))
 	raw_shrl_b_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shrl_b_ri,(RW1 r, IMM i))
 
 MIDFUNC(2,shra_l_ri,(RW4 r, IMM i))
 {
@@ -554,7 +513,6 @@ MIDFUNC(2,shra_l_ri,(RW4 r, IMM i))
 	raw_shra_l_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shra_l_ri,(RW4 r, IMM i))
 
 MIDFUNC(2,shra_w_ri,(RW2 r, IMM i))
 {
@@ -565,7 +523,6 @@ MIDFUNC(2,shra_w_ri,(RW2 r, IMM i))
 	raw_shra_w_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shra_w_ri,(RW2 r, IMM i))
 
 MIDFUNC(2,shra_b_ri,(RW1 r, IMM i))
 {
@@ -576,7 +533,6 @@ MIDFUNC(2,shra_b_ri,(RW1 r, IMM i))
 	raw_shra_b_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,shra_b_ri,(RW1 r, IMM i))
 
 MIDFUNC(2,shra_l_rr,(RW4 d, RR1 r))
 {
@@ -591,7 +547,6 @@ MIDFUNC(2,shra_l_rr,(RW4 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shra_l_rr,(RW4 d, RR1 r))
 
 MIDFUNC(2,shra_w_rr,(RW2 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -607,7 +562,6 @@ MIDFUNC(2,shra_w_rr,(RW2 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shra_w_rr,(RW2 d, RR1 r))
 
 MIDFUNC(2,shra_b_rr,(RW1 d, RR1 r))
 { /* Can only do this with r==1, i.e. cl */
@@ -624,7 +578,6 @@ MIDFUNC(2,shra_b_rr,(RW1 d, RR1 r))
 	unlock2(r);
 	unlock2(d);
 }
-MENDFUNC(2,shra_b_rr,(RW1 d, RR1 r))
 
 MIDFUNC(2,setcc,(W1 d, IMM cc))
 {
@@ -633,14 +586,12 @@ MIDFUNC(2,setcc,(W1 d, IMM cc))
 	raw_setcc(d,cc);
 	unlock2(d);
 }
-MENDFUNC(2,setcc,(W1 d, IMM cc))
 
 MIDFUNC(2,setcc_m,(IMM d, IMM cc))
 {
 	CLOBBER_SETCC;
 	raw_setcc_m(d,cc);
 }
-MENDFUNC(2,setcc_m,(IMM d, IMM cc))
 
 MIDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc))
 {
@@ -653,7 +604,6 @@ MIDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc))
 	unlock2(s);
 	unlock2(d);
 }
-MENDFUNC(3,cmov_l_rr,(RW4 d, RR4 s, IMM cc))
 
 MIDFUNC(2,bsf_l_rr,(W4 d, W4 s))
 {
@@ -664,7 +614,6 @@ MIDFUNC(2,bsf_l_rr,(W4 d, W4 s))
 	unlock2(s);
 	unlock2(d);
 }
-MENDFUNC(2,bsf_l_rr,(W4 d, W4 s))
 
 /* Set the Z flag depending on the value in s. Note that the
  value has to be 0 or -1 (or, more precisely, for non-zero
@@ -678,7 +627,6 @@ MIDFUNC(2,simulate_bsf,(W4 tmp, RW4 s))
 	unlock2(tmp);
 	unlock2(s);
 }
-MENDFUNC(2,simulate_bsf,(W4 tmp, RW4 s))
 
 MIDFUNC(2,imul_32_32,(RW4 d, RR4 s))
 {
@@ -689,7 +637,6 @@ MIDFUNC(2,imul_32_32,(RW4 d, RR4 s))
 	unlock2(s);
 	unlock2(d);
 }
-MENDFUNC(2,imul_32_32,(RW4 d, RR4 s))
 
 MIDFUNC(2,imul_64_32,(RW4 d, RW4 s))
 {
@@ -700,7 +647,6 @@ MIDFUNC(2,imul_64_32,(RW4 d, RW4 s))
 	unlock2(s);
 	unlock2(d);
 }
-MENDFUNC(2,imul_64_32,(RW4 d, RW4 s))
 
 MIDFUNC(2,mul_64_32,(RW4 d, RW4 s))
 {
@@ -711,7 +657,6 @@ MIDFUNC(2,mul_64_32,(RW4 d, RW4 s))
 	unlock2(s);
 	unlock2(d);
 }
-MENDFUNC(2,mul_64_32,(RW4 d, RW4 s))
 
 MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
 {
@@ -741,7 +686,6 @@ MIDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
 		unlock2(s);
 	}
 }
-MENDFUNC(2,sign_extend_16_rr,(W4 d, RR2 s))
 
 MIDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s))
 {
@@ -773,7 +717,6 @@ MIDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s))
 		unlock2(s);
 	}
 }
-MENDFUNC(2,sign_extend_8_rr,(W4 d, RR1 s))
 
 MIDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s))
 {
@@ -803,7 +746,6 @@ MIDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s))
 		unlock2(s);
 	}
 }
-MENDFUNC(2,zero_extend_16_rr,(W4 d, RR2 s))
 
 MIDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s))
 {
@@ -834,7 +776,6 @@ MIDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s))
 		unlock2(s);
 	}
 }
-MENDFUNC(2,zero_extend_8_rr,(W4 d, RR1 s))
 
 MIDFUNC(2,mov_b_rr,(W1 d, RR1 s))
 {
@@ -852,7 +793,6 @@ MIDFUNC(2,mov_b_rr,(W1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,mov_b_rr,(W1 d, RR1 s))
 
 MIDFUNC(2,mov_w_rr,(W2 d, RR2 s))
 {
@@ -870,7 +810,6 @@ MIDFUNC(2,mov_w_rr,(W2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,mov_w_rr,(W2 d, RR2 s))
 
 /* read the long at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset))
@@ -887,7 +826,6 @@ MIDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_l_rR,(W4 d, RR4 s, IMM offset))
 
 /* read the word at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset))
@@ -904,7 +842,6 @@ MIDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_w_rR,(W2 d, RR4 s, IMM offset))
 
 /* read the long at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset))
@@ -923,7 +860,6 @@ MIDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_l_brR,(W4 d, RR4 s, IMM offset))
 
 /* read the word at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset))
@@ -943,7 +879,6 @@ MIDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_w_brR,(W2 d, RR4 s, IMM offset))
 
 /* read the word at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset))
@@ -963,7 +898,6 @@ MIDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_b_brR,(W1 d, RR4 s, IMM offset))
 
 MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset))
 {
@@ -979,7 +913,6 @@ MIDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset))
 	raw_mov_l_Ri(d,i,offset);
 	unlock2(d);
 }
-MENDFUNC(3,mov_l_Ri,(RR4 d, IMM i, IMM offset))
 
 MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset))
 {
@@ -995,7 +928,6 @@ MIDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset))
 	raw_mov_w_Ri(d,i,offset);
 	unlock2(d);
 }
-MENDFUNC(3,mov_w_Ri,(RR4 d, IMM i, IMM offset))
 
 /* Warning! OFFSET is byte sized only! */
 MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset))
@@ -1017,7 +949,6 @@ MIDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_l_Rr,(RR4 d, RR4 s, IMM offset))
 
 MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset))
 {
@@ -1037,7 +968,6 @@ MIDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_w_Rr,(RR4 d, RR2 s, IMM offset))
 
 MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
 {
@@ -1058,7 +988,6 @@ MIDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,lea_l_brr,(W4 d, RR4 s, IMM offset))
 
 MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
 {
@@ -1076,7 +1005,6 @@ MIDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
 	unlock2(index);
 	unlock2(s);
 }
-MENDFUNC(5,lea_l_brr_indexed,(W4 d, RR4 s, RR4 index, IMM factor, IMM offset))
 
 MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
 {
@@ -1090,7 +1018,6 @@ MIDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
 	unlock2(index);
 	unlock2(s);
 }
-MENDFUNC(4,lea_l_rr_indexed,(W4 d, RR4 s, RR4 index, IMM factor))
 
 /* write d to the long at the address contained in s+offset */
 MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset))
@@ -1110,7 +1037,6 @@ MIDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_l_bRr,(RR4 d, RR4 s, IMM offset))
 
 /* write the word at the address contained in s+offset and store in d */
 MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset))
@@ -1130,7 +1056,6 @@ MIDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_w_bRr,(RR4 d, RR2 s, IMM offset))
 
 MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset))
 {
@@ -1148,7 +1073,6 @@ MIDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(3,mov_b_bRr,(RR4 d, RR1 s, IMM offset))
 
 MIDFUNC(1,mid_bswap_32,(RW4 r))
 {
@@ -1164,7 +1088,6 @@ MIDFUNC(1,mid_bswap_32,(RW4 r))
 	raw_bswap_32(r);
 	unlock2(r);
 }
-MENDFUNC(1,mid_bswap_32,(RW4 r))
 
 MIDFUNC(1,mid_bswap_16,(RW2 r))
 {
@@ -1181,7 +1104,6 @@ MIDFUNC(1,mid_bswap_16,(RW2 r))
 	raw_bswap_16(r);
 	unlock2(r);
 }
-MENDFUNC(1,mid_bswap_16,(RW2 r))
 
 MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
 {
@@ -1210,7 +1132,6 @@ MIDFUNC(2,mov_l_rr,(W4 d, RR4 s))
 	D2(panicbug("Added %d to nreg %d(%d), now holds %d regs", d,s,live.state[d].realind,live.nat[s].nholds));
 	unlock2(s);
 }
-MENDFUNC(2,mov_l_rr,(W4 d, RR4 s))
 
 MIDFUNC(2,mov_l_mr,(IMM d, RR4 s))
 {
@@ -1224,7 +1145,6 @@ MIDFUNC(2,mov_l_mr,(IMM d, RR4 s))
 	raw_mov_l_mr(d,s);
 	unlock2(s);
 }
-MENDFUNC(2,mov_l_mr,(IMM d, RR4 s))
 
 MIDFUNC(2,mov_w_mr,(IMM d, RR2 s))
 {
@@ -1238,7 +1158,6 @@ MIDFUNC(2,mov_w_mr,(IMM d, RR2 s))
 	raw_mov_w_mr(d,s);
 	unlock2(s);
 }
-MENDFUNC(2,mov_w_mr,(IMM d, RR2 s))
 
 MIDFUNC(2,mov_w_rm,(W2 d, IMM s))
 {
@@ -1248,7 +1167,6 @@ MIDFUNC(2,mov_w_rm,(W2 d, IMM s))
 	raw_mov_w_rm(d,s);
 	unlock2(d);
 }
-MENDFUNC(2,mov_w_rm,(W2 d, IMM s))
 
 MIDFUNC(2,mov_b_mr,(IMM d, RR1 s))
 {
@@ -1263,7 +1181,6 @@ MIDFUNC(2,mov_b_mr,(IMM d, RR1 s))
 	raw_mov_b_mr(d,s);
 	unlock2(s);
 }
-MENDFUNC(2,mov_b_mr,(IMM d, RR1 s))
 
 MIDFUNC(2,mov_b_rm,(W1 d, IMM s))
 {
@@ -1273,14 +1190,12 @@ MIDFUNC(2,mov_b_rm,(W1 d, IMM s))
 	raw_mov_b_rm(d,s);
 	unlock2(d);
 }
-MENDFUNC(2,mov_b_rm,(W1 d, IMM s))
 
 MIDFUNC(2,mov_l_ri,(W4 d, IMM s))
 {
 	set_const(d,s);
 	return;
 }
-MENDFUNC(2,mov_l_ri,(W4 d, IMM s))
 
 MIDFUNC(2,mov_w_ri,(W2 d, IMM s))
 {
@@ -1290,7 +1205,6 @@ MIDFUNC(2,mov_w_ri,(W2 d, IMM s))
 	raw_mov_w_ri(d,s);
 	unlock2(d);
 }
-MENDFUNC(2,mov_w_ri,(W2 d, IMM s))
 
 MIDFUNC(2,mov_b_ri,(W1 d, IMM s))
 {
@@ -1300,7 +1214,6 @@ MIDFUNC(2,mov_b_ri,(W1 d, IMM s))
 	raw_mov_b_ri(d,s);
 	unlock2(d);
 }
-MENDFUNC(2,mov_b_ri,(W1 d, IMM s))
 
 MIDFUNC(2,test_l_ri,(RR4 d, IMM i))
 {
@@ -1310,7 +1223,6 @@ MIDFUNC(2,test_l_ri,(RR4 d, IMM i))
 	raw_test_l_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,test_l_ri,(RR4 d, IMM i))
 
 MIDFUNC(2,test_l_rr,(RR4 d, RR4 s))
 {
@@ -1322,7 +1234,6 @@ MIDFUNC(2,test_l_rr,(RR4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,test_l_rr,(RR4 d, RR4 s))
 
 MIDFUNC(2,test_w_rr,(RR2 d, RR2 s))
 {
@@ -1334,7 +1245,6 @@ MIDFUNC(2,test_w_rr,(RR2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,test_w_rr,(RR2 d, RR2 s))
 
 MIDFUNC(2,test_b_rr,(RR1 d, RR1 s))
 {
@@ -1346,7 +1256,6 @@ MIDFUNC(2,test_b_rr,(RR1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,test_b_rr,(RR1 d, RR1 s))
 
 MIDFUNC(2,and_l_ri,(RW4 d, IMM i))
 {
@@ -1361,7 +1270,6 @@ MIDFUNC(2,and_l_ri,(RW4 d, IMM i))
 	raw_and_l_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,and_l_ri,(RW4 d, IMM i))
 
 MIDFUNC(2,and_l,(RW4 d, RR4 s))
 {
@@ -1373,7 +1281,6 @@ MIDFUNC(2,and_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,and_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,and_w,(RW2 d, RR2 s))
 {
@@ -1385,7 +1292,6 @@ MIDFUNC(2,and_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,and_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,and_b,(RW1 d, RR1 s))
 {
@@ -1397,7 +1303,6 @@ MIDFUNC(2,and_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,and_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,or_l_ri,(RW4 d, IMM i))
 {
@@ -1411,7 +1316,6 @@ MIDFUNC(2,or_l_ri,(RW4 d, IMM i))
 	raw_or_l_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,or_l_ri,(RW4 d, IMM i))
 
 MIDFUNC(2,or_l,(RW4 d, RR4 s))
 {
@@ -1427,7 +1331,6 @@ MIDFUNC(2,or_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,or_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,or_w,(RW2 d, RR2 s))
 {
@@ -1439,7 +1342,6 @@ MIDFUNC(2,or_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,or_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,or_b,(RW1 d, RR1 s))
 {
@@ -1451,7 +1353,6 @@ MIDFUNC(2,or_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,or_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,adc_l,(RW4 d, RR4 s))
 {
@@ -1464,7 +1365,6 @@ MIDFUNC(2,adc_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,adc_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,adc_w,(RW2 d, RR2 s))
 {
@@ -1476,7 +1376,6 @@ MIDFUNC(2,adc_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,adc_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,adc_b,(RW1 d, RR1 s))
 {
@@ -1488,7 +1387,6 @@ MIDFUNC(2,adc_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,adc_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,add_l,(RW4 d, RR4 s))
 {
@@ -1506,7 +1404,6 @@ MIDFUNC(2,add_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,add_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,add_w,(RW2 d, RR2 s))
 {
@@ -1523,7 +1420,6 @@ MIDFUNC(2,add_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,add_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,add_b,(RW1 d, RR1 s))
 {
@@ -1540,7 +1436,6 @@ MIDFUNC(2,add_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,add_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,sub_l_ri,(RW4 d, IMM i))
 {
@@ -1563,7 +1458,6 @@ MIDFUNC(2,sub_l_ri,(RW4 d, IMM i))
 	raw_sub_l_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,sub_l_ri,(RW4 d, IMM i))
 
 MIDFUNC(2,sub_w_ri,(RW2 d, IMM i))
 {
@@ -1576,7 +1470,6 @@ MIDFUNC(2,sub_w_ri,(RW2 d, IMM i))
 	raw_sub_w_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,sub_w_ri,(RW2 d, IMM i))
 
 MIDFUNC(2,sub_b_ri,(RW1 d, IMM i))
 {
@@ -1590,7 +1483,6 @@ MIDFUNC(2,sub_b_ri,(RW1 d, IMM i))
 
 	unlock2(d);
 }
-MENDFUNC(2,sub_b_ri,(RW1 d, IMM i))
 
 MIDFUNC(2,add_l_ri,(RW4 d, IMM i))
 {
@@ -1611,7 +1503,6 @@ MIDFUNC(2,add_l_ri,(RW4 d, IMM i))
 	raw_add_l_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,add_l_ri,(RW4 d, IMM i))
 
 MIDFUNC(2,add_w_ri,(RW2 d, IMM i))
 {
@@ -1624,7 +1515,6 @@ MIDFUNC(2,add_w_ri,(RW2 d, IMM i))
 	raw_add_w_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,add_w_ri,(RW2 d, IMM i))
 
 MIDFUNC(2,add_b_ri,(RW1 d, IMM i))
 {
@@ -1638,7 +1528,6 @@ MIDFUNC(2,add_b_ri,(RW1 d, IMM i))
 
 	unlock2(d);
 }
-MENDFUNC(2,add_b_ri,(RW1 d, IMM i))
 
 MIDFUNC(2,sbb_l,(RW4 d, RR4 s))
 {
@@ -1650,7 +1539,6 @@ MIDFUNC(2,sbb_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,sbb_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,sbb_w,(RW2 d, RR2 s))
 {
@@ -1662,7 +1550,6 @@ MIDFUNC(2,sbb_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,sbb_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,sbb_b,(RW1 d, RR1 s))
 {
@@ -1674,7 +1561,6 @@ MIDFUNC(2,sbb_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,sbb_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,sub_l,(RW4 d, RR4 s))
 {
@@ -1691,7 +1577,6 @@ MIDFUNC(2,sub_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,sub_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,sub_w,(RW2 d, RR2 s))
 {
@@ -1708,7 +1593,6 @@ MIDFUNC(2,sub_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,sub_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,sub_b,(RW1 d, RR1 s))
 {
@@ -1725,7 +1609,6 @@ MIDFUNC(2,sub_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,sub_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,cmp_l,(RR4 d, RR4 s))
 {
@@ -1737,7 +1620,6 @@ MIDFUNC(2,cmp_l,(RR4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,cmp_l,(RR4 d, RR4 s))
 
 MIDFUNC(2,cmp_w,(RR2 d, RR2 s))
 {
@@ -1749,7 +1631,6 @@ MIDFUNC(2,cmp_w,(RR2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,cmp_w,(RR2 d, RR2 s))
 
 MIDFUNC(2,cmp_b,(RR1 d, RR1 s))
 {
@@ -1761,7 +1642,6 @@ MIDFUNC(2,cmp_b,(RR1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,cmp_b,(RR1 d, RR1 s))
 
 MIDFUNC(2,xor_l,(RW4 d, RR4 s))
 {
@@ -1773,7 +1653,6 @@ MIDFUNC(2,xor_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,xor_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,xor_w,(RW2 d, RR2 s))
 {
@@ -1785,7 +1664,6 @@ MIDFUNC(2,xor_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,xor_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,xor_b,(RW1 d, RR1 s))
 {
@@ -1797,7 +1675,6 @@ MIDFUNC(2,xor_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,xor_b,(RW1 d, RR1 s))
 
 MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
 {
@@ -1812,7 +1689,6 @@ MIDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
 	prepare_for_call_2();
 	compemu_raw_call_r(r);
 }
-MENDFUNC(5,call_r_02,(RR4 r, RR4 in1, RR4 in2, IMM isize1, IMM isize2))
 
 MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
 {
@@ -1849,13 +1725,11 @@ MIDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
 	live.state[out1].dirtysize=osize;
 	set_status(out1,DIRTY);
 }
-MENDFUNC(5,call_r_11,(W4 out1, RR4 r, RR4 in1, IMM osize, IMM isize))
 
 MIDFUNC(0,nop,(void))
 {
 	raw_emit_nop();
 }
-MENDFUNC(0,nop,(void))
 
 /* forget_about() takes a mid-layer register */
 MIDFUNC(1,forget_about,(W4 r))
@@ -1865,7 +1739,6 @@ MIDFUNC(1,forget_about,(W4 r))
 	live.state[r].val=0;
 	set_status(r,UNDEF);
 }
-MENDFUNC(1,forget_about,(W4 r))
 
 MIDFUNC(1,f_forget_about,(FW r))
 {
@@ -1873,7 +1746,6 @@ MIDFUNC(1,f_forget_about,(FW r))
 	f_disassociate(r);
 	live.fate[r].status=UNDEF;
 }
-MENDFUNC(1,f_forget_about,(FW r))
 
 // ARM optimized functions
 
@@ -1892,7 +1764,6 @@ MIDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_ADD_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i))
 {
@@ -1911,7 +1782,6 @@ MIDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i))
 	raw_ADD_l_rr(d,REG_WORK1);
 	unlock2(d);
 }
-MENDFUNC(2,arm_ADD_l_ri,(RW4 d, IMM i))
 
 MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
 {
@@ -1929,7 +1799,6 @@ MIDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
 	raw_ADD_l_rri(d,d,i);
 	unlock2(d);
 }
-MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
 
 MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i))
 {
@@ -1947,7 +1816,6 @@ MIDFUNC(2,arm_SUB_l_ri8,(RW4 d, IMM i))
 	raw_SUB_l_rri(d,d,i);
 	unlock2(d);
 }
-MENDFUNC(2,arm_ADD_l_ri8,(RW4 d, IMM i))
 
 MIDFUNC(2,arm_AND_l,(RW4 d, RR4 s))
 {
@@ -1958,7 +1826,6 @@ MIDFUNC(2,arm_AND_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_AND_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,arm_AND_w,(RW2 d, RR2 s))
 {
@@ -1969,7 +1836,6 @@ MIDFUNC(2,arm_AND_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_AND_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,arm_AND_b,(RW1 d, RR1 s))
 {
@@ -1980,7 +1846,6 @@ MIDFUNC(2,arm_AND_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_AND_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,arm_AND_l_ri8,(RW4 d, IMM i))
 {
@@ -1994,7 +1859,6 @@ MIDFUNC(2,arm_AND_l_ri8,(RW4 d, IMM i))
 	raw_AND_l_ri(d,i);
 	unlock2(d);
 }
-MENDFUNC(2,arm_AND_l_ri8,(RW4 d, IMM i))
 
 MIDFUNC(2,arm_EOR_b,(RW1 d, RR1 s))
 {
@@ -2005,7 +1869,6 @@ MIDFUNC(2,arm_EOR_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_EOR_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,arm_EOR_l,(RW4 d, RR4 s))
 {
@@ -2016,7 +1879,6 @@ MIDFUNC(2,arm_EOR_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_EOR_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,arm_EOR_w,(RW2 d, RR2 s))
 {
@@ -2027,7 +1889,6 @@ MIDFUNC(2,arm_EOR_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_EOR_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,arm_ORR_b,(RW1 d, RR1 s))
 {
@@ -2038,7 +1899,6 @@ MIDFUNC(2,arm_ORR_b,(RW1 d, RR1 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_ORR_b,(RW1 d, RR1 s))
 
 MIDFUNC(2,arm_ORR_l,(RW4 d, RR4 s))
 {
@@ -2053,7 +1913,6 @@ MIDFUNC(2,arm_ORR_l,(RW4 d, RR4 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_ORR_l,(RW4 d, RR4 s))
 
 MIDFUNC(2,arm_ORR_w,(RW2 d, RR2 s))
 {
@@ -2064,7 +1923,6 @@ MIDFUNC(2,arm_ORR_w,(RW2 d, RR2 s))
 	unlock2(d);
 	unlock2(s);
 }
-MENDFUNC(2,arm_ORR_w,(RW2 d, RR2 s))
 
 MIDFUNC(2,arm_ROR_l_ri8,(RW4 r, IMM i))
 {
@@ -2075,7 +1933,6 @@ MIDFUNC(2,arm_ROR_l_ri8,(RW4 r, IMM i))
 	raw_ROR_l_ri(r,i);
 	unlock2(r);
 }
-MENDFUNC(2,arm_ROR_l_ri8,(RW4 r, IMM i))
 
 // Other
 static inline void flush_cpu_icache(void *start, void *stop)

BasiliskII/src/uae_cpu/compiler/compemu_midfunc_arm.h

@@ -64,6 +64,7 @@ DECLARE_MIDFUNC(rol_w_ri(RW2 r, IMM i));
 DECLARE_MIDFUNC(rol_l_rr(RW4 d, RR1 r));
 DECLARE_MIDFUNC(rol_w_rr(RW2 d, RR1 r));
 DECLARE_MIDFUNC(rol_b_rr(RW1 d, RR1 r));
+DECLARE_MIDFUNC(rol_l_ri(RW4 r, IMM i));
 DECLARE_MIDFUNC(shll_l_rr(RW4 d, RR1 r));
 DECLARE_MIDFUNC(shll_w_rr(RW2 d, RR1 r));
 DECLARE_MIDFUNC(shll_b_rr(RW1 d, RR1 r));
@@ -98,6 +99,7 @@ DECLARE_MIDFUNC(sign_extend_16_rr(W4 d, RR2 s));
 DECLARE_MIDFUNC(sign_extend_8_rr(W4 d, RR1 s));
 DECLARE_MIDFUNC(zero_extend_16_rr(W4 d, RR2 s));
 DECLARE_MIDFUNC(zero_extend_8_rr(W4 d, RR1 s));
+DECLARE_MIDFUNC(simulate_bsf(W4 tmp, RW4 s));
 DECLARE_MIDFUNC(imul_64_32(RW4 d, RW4 s));
 DECLARE_MIDFUNC(mul_64_32(RW4 d, RW4 s));
 DECLARE_MIDFUNC(imul_32_32(RW4 d, RR4 s));

BasiliskII/src/uae_cpu/compiler/compemu_midfunc_x86.h

@@ -185,6 +185,7 @@ DECLARE_MIDFUNC(xor_b(RW1 d, RR1 s));
 DECLARE_MIDFUNC(live_flags(void));
 DECLARE_MIDFUNC(dont_care_flags(void));
 DECLARE_MIDFUNC(duplicate_carry(void));
+DECLARE_MIDFUNC(setcc_for_cntzero(RR4 d, RR4 data, int size));
 DECLARE_MIDFUNC(restore_carry(void));
 DECLARE_MIDFUNC(start_needflags(void));
 DECLARE_MIDFUNC(end_needflags(void));
@@ -201,17 +202,17 @@ DECLARE_MIDFUNC(fmov_log2_e(FW r));
 DECLARE_MIDFUNC(fmov_loge_2(FW r));
 DECLARE_MIDFUNC(fmov_1(FW r));
 DECLARE_MIDFUNC(fmov_0(FW r));
-DECLARE_MIDFUNC(fmov_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmov_rm(FW r, MEMPTRR m));
-DECLARE_MIDFUNC(fmov_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmov_mr(MEMPTRW m, FR r));
-DECLARE_MIDFUNC(fmovi_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmovi_rm(FW r, MEMPTRR m));
-DECLARE_MIDFUNC(fmovi_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmovi_mr(MEMPTRW m, FR r));
-DECLARE_MIDFUNC(fmovi_mrb(MEMW m, FR r, double *bounds));
+DECLARE_MIDFUNC(fmovi_mrb(MEMPTRW m, FR r, double *bounds));
-DECLARE_MIDFUNC(fmovs_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmovs_rm(FW r, MEMPTRR m));
-DECLARE_MIDFUNC(fmovs_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmovs_mr(MEMPTRW m, FR r));
 DECLARE_MIDFUNC(fcuts_r(FRW r));
 DECLARE_MIDFUNC(fcut_r(FRW r));
-DECLARE_MIDFUNC(fmov_ext_mr(MEMW m, FR r));
+DECLARE_MIDFUNC(fmov_ext_mr(MEMPTRW m, FR r));
-DECLARE_MIDFUNC(fmov_ext_rm(FW r, MEMR m));
+DECLARE_MIDFUNC(fmov_ext_rm(FW r, MEMPTRR m));
 DECLARE_MIDFUNC(fmov_rr(FW d, FR s));
 DECLARE_MIDFUNC(fldcw_m_indexed(RR4 index, IMM base));
 DECLARE_MIDFUNC(ftst_r(FR r));

BasiliskII/src/uae_cpu/compiler/compemu_support.cpp

@@ -43,12 +43,6 @@
 #error "Only [LS]AHF scheme to [gs]et flags is supported with the JIT Compiler"
 #endif
 
-//TODO: detect i386 and arm platforms
-
-#ifdef __x86_64__
-#define CPU_x86_64 1
-#endif
-
 /* NOTE: support for AMD64 assumes translation cache and other code
  * buffers are allocated into a 32-bit address space because (i) B2/JIT
  * code is not 64-bit clean and (ii) it's faster to resolve branches
@@ -72,7 +66,7 @@
 #ifdef UAE
 #include "options.h"
 #include "events.h"
-#include "memory.h"
+#include "uae/memory.h"
 #include "custom.h"
 #else
 #include "cpu_emulation.h"
@@ -88,11 +82,15 @@
 #include "comptbl.h"
 #ifdef UAE
 #include "compemu.h"
+#ifdef FSUAE
+#include "codegen_udis86.h"
+#endif
 #else
 #include "compiler/compemu.h"
 #include "fpu/fpu.h"
 #include "fpu/flags.h"
 // #include "parameters.h"
+static void build_comp(void);
 #endif
 // #include "verify.h"
 
@@ -100,10 +98,16 @@
 // 	uae_log("JIT: " format "\n", ##__VA_ARGS__);
 #define D2 D
 
-
 #ifdef UAE
+#ifdef FSUAE
+#include "uae/fs.h"
+#endif
 #include "uae/log.h"
 
+#if defined(__pie__) || defined (__PIE__)
+#error Position-independent code (PIE) cannot be used with JIT
+#endif
+
 #include "uae/vm.h"
 #define VM_PAGE_READ UAE_VM_READ
 #define VM_PAGE_WRITE UAE_VM_WRITE
@@ -149,6 +153,15 @@ static inline int distrust_check(int value)
 	return 1;
 #else
 	int distrust = value;
+#ifdef FSUAE
+	switch (value) {
+	case 0: distrust = 0; break;
+	case 1: distrust = 1; break;
+	case 2: distrust = ((start_pc & 0xF80000) == 0xF80000); break;
+	case 3: distrust = !have_done_picasso; break;
+	default: abort();
+	}
+#endif
 	return distrust;
 #endif
 }
@@ -237,7 +250,7 @@ static clock_t emul_end_time	= 0;
 #endif
 
 #ifdef PROFILE_UNTRANSLATED_INSNS
-static const int untranslated_top_ten = 20;
+static const int untranslated_top_ten = 50;
 static uae_u32 raw_cputbl_count[65536] = { 0, };
 static uae_u16 opcode_nums[65536];
 
@@ -266,8 +279,10 @@ extern bool quit_program;
 // gb-- Extra data for Basilisk II/JIT
 #ifdef JIT_DEBUG
 static bool		JITDebug			= false;	// Enable runtime disassemblers through mon?
+// #define JITDebug bx_options.jit.jitdebug		// Enable runtime disassemblers through mon?
 #else
 const bool		JITDebug			= false;
+// #define JITDebug false			// Don't use JIT debug mode at all
 #endif
 #if USE_INLINING
 #ifdef UAE
@@ -283,6 +298,7 @@ const uae_u32 MIN_CACHE_SIZE = 1024; // Minimal translation cache size (1 MB)
 static uae_u32 cache_size = 0; // Size of total cache allocated for compiled blocks
 static uae_u32		current_cache_size	= 0;		// Cache grows upwards: how much has been consumed already
 static bool		lazy_flush		= true;	// Flag: lazy translation cache invalidation
+// Flag: compile FPU instructions ?
 #ifdef UAE
 #ifdef USE_JIT_FPU
 #define avoid_fpu (!currprefs.compfpu)
@@ -291,6 +307,11 @@ static bool		lazy_flush		= true;	// Flag: lazy translation cache invalidation
 #endif
 #else
 static bool avoid_fpu = true; // Flag: compile FPU instructions ?
+// #ifdef USE_JIT_FPU
+// #define avoid_fpu (!bx_options.jit.jitfpu)
+// #else
+// #define avoid_fpu (true)
+// #endif
 #endif
 static bool		have_cmov		= false;	// target has CMOV instructions ?
 static bool		have_rat_stall		= true;	// target has partial register stalls ?
@@ -370,10 +391,9 @@ static uintptr taken_pc_p;
 static int     branch_cc;
 static int redo_current_block;
 
+#ifdef UAE
 int segvcount=0;
-int soft_flush_count=0;
+#endif
-int hard_flush_count=0;
-int checksum_count=0;
 static uae_u8* current_compile_p=NULL;
 static uae_u8* max_compile_start;
 static uae_u8* compiled_code=NULL;
@@ -395,7 +415,7 @@ static void* popall_check_checksum=NULL;
  * lists that we maintain for each hash result.
  */
 static cacheline cache_tags[TAGSIZE];
-int letit=0;
+static int cache_enabled=0;
 static blockinfo* hold_bi[MAX_HOLD_BI];
 static blockinfo* active;
 static blockinfo* dormant;
@@ -420,12 +440,10 @@ extern const struct cputbl op_smalltbl_4_nf[];
 extern const struct cputbl op_smalltbl_5_nf[];
 #endif
 
-#ifdef WINUAE_ARANYM
+static void flush_icache_hard(void);
-static void flush_icache_hard(int n);
+static void flush_icache_lazy(void);
-static void flush_icache_lazy(int n);
+static void flush_icache_none(void);
-static void flush_icache_none(int n);
+void (*flush_icache)(void) = flush_icache_none;
-void (*flush_icache)(int n) = flush_icache_none;
-#endif
 
 static bigstate live;
 static smallstate empty_ss;
@@ -452,7 +470,7 @@ uae_u32 m68k_pc_offset;
  * side effects they would have on the flags are not important. This
  * variable indicates whether we need the side effects or not
  */
-uae_u32 needflags=0;
+static uae_u32 needflags=0;
 
 /* Flag handling is complicated.
  *
@@ -500,7 +518,7 @@ static inline blockinfo* get_blockinfo_addr(void* addr)
 /*******************************************************************
  * Disassembler support                                            *
  *******************************************************************/
-		
+
 #define TARGET_M68K		0
 #define TARGET_POWERPC	1
 #define TARGET_X86		2
@@ -531,11 +549,11 @@ static void disasm_block(int disasm_target, const uint8 *start, size_t length)
 #if defined(HAVE_DISASM_M68K)
 		{
 			char buf[256];
-			
+
 			disasm_info.memory_vma = ((memptr)((uintptr_t)(start) - MEMBaseDiff));
 			while (length > 0)
 			{
-				int isize = m68k_disasm_to_buf(&disasm_info, buf);
+				int isize = m68k_disasm_to_buf(&disasm_info, buf, 1);
 				bug("%s", buf);
 				if (isize < 0)
 					break;
@@ -552,10 +570,10 @@ static void disasm_block(int disasm_target, const uint8 *start, size_t length)
 		{
 			const uint8 *end = start + length;
 			char buf[256];
-			
+
 			while (start < end)
 			{
-				start = x86_disasm(start, buf);
+				start = x86_disasm(start, buf, 1);
 				bug("%s", buf);
 			}
 		}
@@ -566,10 +584,10 @@ static void disasm_block(int disasm_target, const uint8 *start, size_t length)
 		{
 			const uint8 *end = start + length;
 			char buf[256];
-			
+
 			while (start < end)
 			{
-				start = arm_disasm(start, buf);
+				start = arm_disasm(start, buf, 1);
 				bug("%s", buf);
 			}
 		}
@@ -2640,8 +2658,10 @@ static scratch_t scratch;
  * Support functions exposed to newcpu                              *
  ********************************************************************/
 
-#define str_on_off(b) b ? "on" : "off"
+static inline const char *str_on_off(bool b)
-
+{
+	return b ? "on" : "off";
+}
 
 #ifdef UAE
 static
@@ -2673,8 +2693,6 @@ void compiler_init(void)
 	cache_size = PrefsFindInt32("jitcachesize");
 	jit_log("<JIT compiler> : requested translation cache size : %d KB", cache_size);
 
-	// Initialize target CPU (check for features, e.g. CMOV, rat stalls)
-	raw_init_cpu();
 	setzflg_uses_bsf = target_check_bsf();
 	jit_log("<JIT compiler> : target processor has CMOV instructions : %s", have_cmov ? "yes" : "no");
 	jit_log("<JIT compiler> : target processor can suffer from partial register stalls : %s", have_rat_stall ? "yes" : "no");
@@ -2700,6 +2718,8 @@ void compiler_init(void)
 	jit_log("<JIT compiler> : separate blockinfo allocation : %s", str_on_off(USE_SEPARATE_BIA));
 
 	// Build compiler tables
+	read_table68k();
+	do_merges();
 	build_comp();
 #endif
 
@@ -2728,7 +2748,7 @@ void compiler_exit(void)
 #else
 #if DEBUG
 #if defined(USE_DATA_BUFFER)
-	jit_log("data_wasted = %d bytes", data_wasted);
+	jit_log("data_wasted = %ld bytes", data_wasted);
 #endif
 #endif
 
@@ -2759,7 +2779,7 @@ void compiler_exit(void)
 		opcode_nums[i] = i;
 		untranslated_count += raw_cputbl_count[i];
 	}
-	jit_log("Sorting out untranslated instructions count...");
+	bug("Sorting out untranslated instructions count...");
 	qsort(opcode_nums, 65536, sizeof(uae_u16), untranslated_compfn);
 	jit_log("Rank  Opc      Count Name");
 	for (int i = 0; i < untranslated_top_ten; i++) {
@@ -2771,7 +2791,7 @@ void compiler_exit(void)
 		dp = table68k + opcode_nums[i];
 		for (lookup = lookuptab; lookup->mnemo != (instrmnem)dp->mnemo; lookup++)
 			;
-		jit_log("%03d: %04x %10u %s", i, opcode_nums[i], count, lookup->name);
+		bug("%03d: %04x %10u %s", i, opcode_nums[i], count, lookup->name);
 	}
 #endif
 
@@ -2793,6 +2813,8 @@ void compiler_exit(void)
 		   100.0*double(cum_reg_count)/double(tot_reg_count));
 	}
 #endif
+
+	// exit_table68k();
 }
 
 #ifdef UAE
@@ -2813,7 +2835,7 @@ bool compiler_use_jit(void)
 }
 #endif
 
-void init_comp(void)
+static void init_comp(void)
 {
 	int i;
 	uae_s8* cb=can_byte;
@@ -3015,14 +3037,18 @@ static void flush_keepflags(void)
 }
 #endif
 
-void freescratch(void)
+static void freescratch(void)
 {
 	int i;
 	for (i=0;i<N_REGS;i++)
 #if defined(CPU_arm)
 		if (live.nat[i].locked && i != REG_WORK1 && i != REG_WORK2)
 #else
-		if (live.nat[i].locked && i!=ESP_INDEX)
+		if (live.nat[i].locked && i != ESP_INDEX
+#if defined(UAE) && defined(CPU_x86_64)
+			&& i != R12_INDEX
+#endif
+			)
 #endif
 		{
 			jit_log("Warning! %d is locked",i);
@@ -3479,14 +3505,14 @@ void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp)
 
 void set_cache_state(int enabled)
 {
-	if (enabled!=letit)
+	if (enabled!=cache_enabled)
-		flush_icache_hard(77);
+		flush_icache_hard();
-	letit=enabled;
+	cache_enabled=enabled;
 }
 
 int get_cache_state(void)
 {
-	return letit;
+	return cache_enabled;
 }
 
 uae_u32 get_jitted_size(void)
@@ -3498,54 +3524,9 @@ uae_u32 get_jitted_size(void)
 
 static uint8 *do_alloc_code(uint32 size, int depth)
 {
-#if defined(__linux__) && 0
-	/*
-	  This is a really awful hack that is known to work on Linux at
-	  least.
-	  
-	  The trick here is to make sure the allocated cache is nearby
-	  code segment, and more precisely in the positive half of a
-	  32-bit address space. i.e. addr < 0x80000000. Actually, it
-	  turned out that a 32-bit binary run on AMD64 yields a cache
-	  allocated around 0xa0000000, thus causing some troubles when
-	  translating addresses from m68k to x86.
-	*/
-	const int CODE_ALLOC_MAX_ATTEMPTS = 10;
-	const int CODE_ALLOC_BOUNDARIES   = 128 * 1024; // 128 KB
-
-	static uint8 * code_base = NULL;
-	if (code_base == NULL) {
-		uintptr page_size = getpagesize();
-		uintptr boundaries = CODE_ALLOC_BOUNDARIES;
-		if (boundaries < page_size)
-			boundaries = page_size;
-		code_base = (uint8 *)sbrk(0);
-		for (int attempts = 0; attempts < CODE_ALLOC_MAX_ATTEMPTS; attempts++) {
-			if (vm_acquire_fixed(code_base, size) == 0) {
-				uint8 *code = code_base;
-				code_base += size;
-				return code;
-			}
-			code_base += boundaries;
-		}
-		return NULL;
-	}
-
-	if (vm_acquire_fixed(code_base, size) == 0) {
-		uint8 *code = code_base;
-		code_base += size;
-		return code;
-	}
-
-	if (depth >= CODE_ALLOC_MAX_ATTEMPTS)
-		return NULL;
-
-	return do_alloc_code(size, depth + 1);
-#else
 	UNUSED(depth);
 	uint8 *code = (uint8 *)vm_acquire(size, VM_MAP_DEFAULT | VM_MAP_32BIT);
 	return code == VM_MAP_FAILED ? NULL : code;
-#endif
 }
 
 static inline uint8 *alloc_code(uint32 size)
@@ -3559,7 +3540,7 @@ static inline uint8 *alloc_code(uint32 size)
 void alloc_cache(void)
 {
 	if (compiled_code) {
-		flush_icache_hard(6);
+		flush_icache_hard();
 		vm_release(compiled_code, cache_size * 1024);
 		compiled_code = 0;
 	}
@@ -3719,8 +3700,6 @@ static inline int block_check_checksum(blockinfo* bi)
 	if (bi->status!=BI_NEED_CHECK)
 		return 1;  /* This block is in a checked state */
 
-	checksum_count++;
-
 	if (bi->c1 || bi->c2)
 		calc_checksum(bi,&c1,&c2);
 	else {
@@ -3885,7 +3864,10 @@ static inline void create_popalls(void)
 	r=REG_PC_TMP;
 	compemu_raw_mov_l_rm(r, uae_p32(&regs.pc_p));
 	compemu_raw_and_l_ri(r,TAGMASK);
-	assert(sizeof(cache_tags[0]) == sizeof(void *));
+	{
+		assert(sizeof(cache_tags[0]) == sizeof(void *));
+		// verify(sizeof(cache_tags[0]) == sizeof(void *));
+	}
 	compemu_raw_jmp_m_indexed(uae_p32(cache_tags), r, sizeof(void *));
 
 	/* now the exit points */
@@ -4020,12 +4002,98 @@ static int read_opcode(const char *p)
 	return opcode;
 }
 
+
+#ifdef USE_JIT_FPU
+static struct {
+	const char *name;
+	bool *const disabled;
+} const jit_opcodes[] = {
+	{ "fbcc", &jit_disable.fbcc },
+	{ "fdbcc", &jit_disable.fdbcc },
+	{ "fscc", &jit_disable.fscc },
+	{ "ftrapcc", &jit_disable.ftrapcc },
+	{ "fsave", &jit_disable.fsave },
+	{ "frestore", &jit_disable.frestore },
+	{ "fmove", &jit_disable.fmove },
+	{ "fmovec", &jit_disable.fmovec },
+	{ "fmovem", &jit_disable.fmovem },
+	{ "fmovecr", &jit_disable.fmovecr },
+	{ "fint", &jit_disable.fint },
+	{ "fsinh", &jit_disable.fsinh },
+	{ "fintrz", &jit_disable.fintrz },
+	{ "fsqrt", &jit_disable.fsqrt },
+	{ "flognp1", &jit_disable.flognp1 },
+	{ "fetoxm1", &jit_disable.fetoxm1 },
+	{ "ftanh", &jit_disable.ftanh },
+	{ "fatan", &jit_disable.fatan },
+	{ "fasin", &jit_disable.fasin },
+	{ "fatanh", &jit_disable.fatanh },
+	{ "fsin", &jit_disable.fsin },
+	{ "ftan", &jit_disable.ftan },
+	{ "fetox", &jit_disable.fetox },
+	{ "ftwotox", &jit_disable.ftwotox },
+	{ "ftentox", &jit_disable.ftentox },
+	{ "flogn", &jit_disable.flogn },
+	{ "flog10", &jit_disable.flog10 },
+	{ "flog2", &jit_disable.flog2 },
+	{ "fabs", &jit_disable.fabs },
+	{ "fcosh", &jit_disable.fcosh },
+	{ "fneg", &jit_disable.fneg },
+	{ "facos", &jit_disable.facos },
+	{ "fcos", &jit_disable.fcos },
+	{ "fgetexp", &jit_disable.fgetexp },
+	{ "fgetman", &jit_disable.fgetman },
+	{ "fdiv", &jit_disable.fdiv },
+	{ "fmod", &jit_disable.fmod },
+	{ "fadd", &jit_disable.fadd },
+	{ "fmul", &jit_disable.fmul },
+	{ "fsgldiv", &jit_disable.fsgldiv },
+	{ "frem", &jit_disable.frem },
+	{ "fscale", &jit_disable.fscale },
+	{ "fsglmul", &jit_disable.fsglmul },
+	{ "fsub", &jit_disable.fsub },
+	{ "fsincos", &jit_disable.fsincos },
+	{ "fcmp", &jit_disable.fcmp },
+	{ "ftst", &jit_disable.ftst },
+};
+
+static bool read_fpu_opcode(const char **pp)
+{
+	const char *p = *pp;
+	const char *end;
+	size_t len;
+	unsigned int i;
+	
+	end = p;
+	while (*end != '\0' && *end != ',')
+		end++;
+	len = end - p;
+	if (*end != '\0')
+		end++;
+	for (i = 0; i < (sizeof(jit_opcodes) / sizeof(jit_opcodes[0])); i++)
+	{
+		if (len == strlen(jit_opcodes[i].name) && strncasecmp(jit_opcodes[i].name, p, len) == 0)
+		{
+			*jit_opcodes[i].disabled = true;
+			jit_log("<JIT compiler> : disabled %s", jit_opcodes[i].name);
+			*pp = end;
+			return true;
+		}
+	}
+	return false;
+}
+#endif
+
 static bool merge_blacklist()
 {
 #ifdef UAE
 	const char *blacklist = "";
 #else
 	const char *blacklist = PrefsFindString("jitblacklist");
+#endif
+#ifdef USE_JIT_FPU
+	for (unsigned int i = 0; i < (sizeof(jit_opcodes) / sizeof(jit_opcodes[0])); i++)
+		*jit_opcodes[i].disabled = false;
 #endif
 	if (blacklist[0] != '\0') {
 		const char *p = blacklist;
@@ -4035,7 +4103,14 @@ static bool merge_blacklist()
 
 			int opcode1 = read_opcode(p);
 			if (opcode1 < 0)
+			{
+#ifdef USE_JIT_FPU
+				if (read_fpu_opcode(&p))
+					continue;
+#endif
+				bug("<JIT compiler> : invalid opcode %s", p);
 				return false;
+			}
 			p += 4;
 
 			int opcode2 = opcode1;
@@ -4043,7 +4118,10 @@ static bool merge_blacklist()
 				p++;
 				opcode2 = read_opcode(p);
 				if (opcode2 < 0)
+				{
+					bug("<JIT compiler> : invalid opcode %s", p);
 					return false;
+				}
 				p += 4;
 			}
 
@@ -4066,6 +4144,12 @@ static bool merge_blacklist()
 
 void build_comp(void)
 {
+#ifdef FSUAE
+	if (!g_fs_uae_jit_compiler) {
+		jit_log("JIT: JIT compiler is not enabled");
+		return;
+	}
+#endif
 	int i;
 	unsigned long opcode;
 	const struct comptbl* tbl=op_smalltbl_0_comp_ff;
@@ -4084,6 +4168,8 @@ void build_comp(void)
 		: op_smalltbl_5_nf);
 #endif
 #endif
+	// Initialize target CPU (check for features, e.g. CMOV, rat stalls)
+	raw_init_cpu();
 
 #ifdef NATMEM_OFFSET
 #ifdef UAE
@@ -4220,7 +4306,7 @@ void build_comp(void)
 	{
 		jit_log("<JIT compiler> : blacklist merge failure!");
 	}
-	
+
 	count=0;
 	for (opcode = 0; opcode < 65536; opcode++) {
 		if (compfunctbl[cft_map(opcode)])
@@ -4258,21 +4344,19 @@ void build_comp(void)
 }
 
 
-static void flush_icache_none(int)
+static void flush_icache_none(void)
 {
 	/* Nothing to do.  */
 }
 
-static void flush_icache_hard(int n)
+void flush_icache_hard(void)
 {
 	blockinfo* bi, *dbi;
 
-	hard_flush_count++;
 #ifndef UAE
 	jit_log("JIT: Flush Icache_hard(%d/%x/%p), %u KB",
 		n,regs.pc,regs.pc_p,current_cache_size/1024);
 #endif
-	UNUSED(n);
 	bi=active;
 	while(bi) {
 		cache_tags[cacheline(bi->pc_p)].handler=(cpuop_func*)popall_execute_normal;
@@ -4309,22 +4393,11 @@ static void flush_icache_hard(int n)
    we simply mark everything as "needs to be checked".
 */
 
-#ifdef WINUAE_ARANYM
+static inline void flush_icache_lazy(void)
-static inline void flush_icache_lazy(int)
-#else
-void flush_icache(int n)
-#endif
 {
 	blockinfo* bi;
 	blockinfo* bi2;
 
-#ifdef UAE
-	if (currprefs.comp_hardflush) {
-		flush_icache_hard(n);
-		return;
-	}
-#endif
-	soft_flush_count++;
 	if (!active)
 		return;
 
@@ -4359,51 +4432,15 @@ void flush_icache(int n)
 	active=NULL;
 }
 
-#ifdef UAE
-static
-#endif
-// void flush_icache_range(uae_u32 start, uae_u32 length)
-// {
-// 	if (!active)
-// 		return;
 
-// #if LAZY_FLUSH_ICACHE_RANGE
+#if 0
-// 	uae_u8 *start_p = get_real_address(start);
+static void flush_icache_range(uae_u32 start, uae_u32 length)
-// 	blockinfo *bi = active;
-// 	while (bi) {
-// #if USE_CHECKSUM_INFO
-// 		bool invalidate = false;
-// 		for (checksum_info *csi = bi->csi; csi && !invalidate; csi = csi->next)
-// 			invalidate = (((start_p - csi->start_p) < csi->length) ||
-// 						  ((csi->start_p - start_p) < length));
-// #else
-// 		// Assume system is consistent and would invalidate the right range
-// 		const bool invalidate = (bi->pc_p - start_p) < length;
-// #endif
-// 		if (invalidate) {
-// 			uae_u32 cl = cacheline(bi->pc_p);
-// 			if (bi == cache_tags[cl + 1].bi)
-// 					cache_tags[cl].handler = (cpuop_func *)popall_execute_normal;
-// 			bi->handler_to_use = (cpuop_func *)popall_execute_normal;
-// 			set_dhtu(bi, bi->direct_pen);
-// 			bi->status = BI_NEED_RECOMP;
-// 		}
-// 		bi = bi->next;
-// 	}
-// 	return;
-// #else
-// 		UNUSED(start);
-// 		UNUSED(length);
-// #endif
-// 	flush_icache(-1);
-// }
-
-void flush_icache_range(uae_u8 *start_p, uae_u32 length)
 {
 	if (!active)
 		return;
 
 #if LAZY_FLUSH_ICACHE_RANGE
+	uae_u8 *start_p = get_real_address(start);
 	blockinfo *bi = active;
 	while (bi) {
 #if USE_CHECKSUM_INFO
@@ -4427,18 +4464,13 @@ void flush_icache_range(uae_u8 *start_p, uae_u32 length)
 	}
 	return;
 #else
-		// UNUSED(start);
+		UNUSED(start);
-		// UNUSED(length);
+		UNUSED(length);
 #endif
-	flush_icache(-1);
+	flush_icache();
 }
+#endif
 
-/*
-static void catastrophe(void)
-{
-	jit_abort("catastprophe");
-}
-*/
 
 int failure;
 
@@ -4465,45 +4497,45 @@ void compiler_dumpstate(void)
 	if (!JITDebug)
 		return;
 	
-	bug("### Host addresses");
+	jit_log("### Host addresses");
-	bug("MEM_BASE    : %lx", (unsigned long)MEMBaseDiff);
+	jit_log("MEM_BASE    : %lx", (unsigned long)MEMBaseDiff);
-	bug("PC_P        : %p", &regs.pc_p);
+	jit_log("PC_P        : %p", &regs.pc_p);
-	bug("SPCFLAGS    : %p", &regs.spcflags);
+	jit_log("SPCFLAGS    : %p", &regs.spcflags);
-	bug("D0-D7       : %p-%p", &regs.regs[0], &regs.regs[7]);
+	jit_log("D0-D7       : %p-%p", &regs.regs[0], &regs.regs[7]);
-	bug("A0-A7       : %p-%p", &regs.regs[8], &regs.regs[15]);
+	jit_log("A0-A7       : %p-%p", &regs.regs[8], &regs.regs[15]);
-	bug(" ");
+	jit_log(" ");
 	
-	bug("### M68k processor state");
+	jit_log("### M68k processor state");
 	m68k_dumpstate(stderr, 0);
-	bug(" ");
+	jit_log(" ");
 	
-	bug("### Block in Atari address space");
+	jit_log("### Block in Atari address space");
-	bug("M68K block   : %p",
+	jit_log("M68K block   : %p",
 			  (void *)(uintptr)last_regs_pc_p);
 	if (last_regs_pc_p != 0) {
-		bug("Native block : %p (%d bytes)",
+		jit_log("Native block : %p (%d bytes)",
 			  (void *)last_compiled_block_addr,
 			  get_blockinfo_addr(last_regs_pc_p)->direct_handler_size);
 	}
-	bug(" ");
+	jit_log(" ");
 }
 #endif
 
 #ifdef UAE
 void compile_block(cpu_history *pc_hist, int blocklen, int totcycles)
 {
-	if (letit && compiled_code && currprefs.cpu_model >= 68020) {
+	if (cache_enabled && compiled_code && currprefs.cpu_model >= 68020) {
 #else
 static void compile_block(cpu_history* pc_hist, int blocklen)
 {
-	if (letit && compiled_code) {
+	if (cache_enabled && compiled_code) {
 #endif
 #ifdef PROFILE_COMPILE_TIME
 		compile_count++;
 		clock_t start_time = clock();
 #endif
 #ifdef JIT_DEBUG
-		bool disasm_block = true;
+		bool disasm_block = false;
 #endif
 
 		/* OK, here we need to 'compile' a block */
@@ -4527,7 +4559,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 
 		redo_current_block=0;
 		if (current_compile_p >= MAX_COMPILE_PTR)
-			flush_icache_hard(7);
+			flush_icache_hard();
 
 		alloc_blockinfos();
 
@@ -4643,12 +4675,12 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #ifdef USE_CPU_EMUL_SERVICES
 			compemu_raw_sub_l_mi((uintptr)&emulated_ticks,blocklen);
 			compemu_raw_jcc_b_oponly(NATIVE_CC_GT);
-			uae_s8 *branchadd=(uae_s8*)get_target();
+			uae_u8 *branchadd=get_target();
 			skip_byte();
 			raw_dec_sp(STACK_SHADOW_SPACE);
 			compemu_raw_call((uintptr)cpu_do_check_ticks);
 			raw_inc_sp(STACK_SHADOW_SPACE);
-			*branchadd=(uintptr)get_target()-((uintptr)branchadd+1);
+			*branchadd=get_target()-(branchadd+1);
 #endif
 
 #ifdef JIT_DEBUG
@@ -4690,7 +4722,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 					prepare_for_call_1();
 					prepare_for_call_2();
 					raw_mov_l_ri(REG_PAR1, ((uintptr)(pc_hist[i].location)) - MEMBaseDiff);
-					raw_mov_w_ri(REG_PAR2, opcode);
+					raw_mov_w_ri(REG_PAR2, cft_map(opcode));
 					raw_dec_sp(STACK_SHADOW_SPACE);
 					compemu_raw_call((uintptr)m68k_record_step);
 					raw_inc_sp(STACK_SHADOW_SPACE);
@@ -4706,11 +4738,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 					}
 					was_comp=1;
 					
+#ifdef WINUAE_ARANYM
 					bool isnop = do_get_mem_word(pc_hist[i].location) == 0x4e71 ||
 						((i + 1) < blocklen && do_get_mem_word(pc_hist[i+1].location) == 0x4e71);
 					
 					if (isnop)
 						compemu_raw_mov_l_mi((uintptr)&regs.fault_pc, ((uintptr)(pc_hist[i].location)) - MEMBaseDiff);
+#endif
 
 					comptbl[opcode](opcode);
 					freescratch();
@@ -4724,6 +4758,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 					flush(1);
 					was_comp=0;
 #endif
+#ifdef WINUAE_ARANYM
 					/*
 					 * workaround for buserror handling: on a "nop", write registers back
 					 */
@@ -4733,6 +4768,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 						nop();
 						was_comp=0;
 					}
+#endif
 				}
 
 				if (failure) {
@@ -4758,7 +4794,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #endif
 
 					if (i < blocklen - 1) {
-						uae_s8* branchadd;
+						uae_u8* branchadd;
 
 						/* if (SPCFLAGS_TEST(SPCFLAG_STOP)) popall_do_nothing() */
 						compemu_raw_mov_l_rm(0,(uintptr)specflags);
@@ -4767,13 +4803,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 						data_check_end(8, 64);  // just a pessimistic guess...
 #endif
 						compemu_raw_jz_b_oponly();
-						branchadd=(uae_s8*)get_target();
+						branchadd=get_target();
 						skip_byte();
 #ifdef UAE
 						raw_sub_l_mi(uae_p32(&countdown),scaled_cycles(totcycles));
 #endif
 						compemu_raw_jmp((uintptr)popall_do_nothing);
-						*branchadd=(uintptr)get_target()-(uintptr)branchadd-1;
+						*branchadd=get_target()-branchadd-1;
 					}
 				}
 			}
@@ -4804,7 +4840,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 			}
 #endif
 			log_flush();
-	
+
 			if (next_pc_p) { /* A branch was registered */
 				uintptr t1=next_pc_p;
 				uintptr t2=taken_pc_p;
@@ -4900,7 +4936,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 
 					tbi = get_blockinfo_addr_new((void*) v, 1);
 					match_states(tbi);
-	
+
 #ifdef UAE
 					raw_sub_l_mi(uae_p32(&countdown),scaled_cycles(totcycles));
 					raw_jcc_l_oponly(NATIVE_CC_PL);
@@ -4936,10 +4972,10 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 		if (callers_need_recompile(&live,&(bi->env))) {
 			mark_callers_recompile(bi);
 		}
-	
+
 		big_to_small_state(&live,&(bi->env));
 #endif
-	
+
 #if USE_CHECKSUM_INFO
 		remove_from_list(bi);
 		if (trace_in_rom) {
@@ -4974,7 +5010,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 		}
 #endif
 
-		current_cache_size += get_target() - (uae_u8 *)current_compile_p;
+		current_cache_size += get_target() - current_compile_p;
 
 #ifdef JIT_DEBUG
 		bi->direct_handler_size = get_target() - (uae_u8 *)current_block_start_target;
@@ -4983,9 +5019,13 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 			uaecptr block_addr = start_pc + ((char *)pc_hist[0].location - (char *)start_pc_p);
 			jit_log("M68K block @ 0x%08x (%d insns)", block_addr, blocklen);
 			uae_u32 block_size = ((uae_u8 *)pc_hist[blocklen - 1].location - (uae_u8 *)pc_hist[0].location) + 1;
+#ifdef WINUAE_ARANYM
 			disasm_m68k_block((const uae_u8 *)pc_hist[0].location, block_size);
+#endif
 			jit_log("Compiled block @ %p", pc_hist[0].location);
+#ifdef WINUAE_ARANYM
 			disasm_native_block((const uae_u8 *)current_block_start_target, bi->direct_handler_size);
+#endif
 			UNUSED(block_addr);
 		}
 #endif
@@ -5022,7 +5062,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 
 		/* We will flush soon, anyway, so let's do it now */
 		if (current_compile_p >= MAX_COMPILE_PTR)
-			flush_icache_hard(7);
+			flush_icache_hard();
 
 		bi->status=BI_ACTIVE;
 		if (redo_current_block)
@@ -5037,7 +5077,7 @@ static void compile_block(cpu_history* pc_hist, int blocklen)
 #endif
 	}
 
-#ifndef UAE
+#ifdef USE_CPU_EMUL_SERVICES
 	/* Account for compilation time */
 	cpu_do_check_ticks();
 #endif
@@ -5060,7 +5100,7 @@ void exec_nostats(void)
 	for (;;)  { 
 		uae_u32 opcode = GET_OPCODE;
 #if FLIGHT_RECORDER
-		m68k_record_step(m68k_getpc(), opcode);
+		m68k_record_step(m68k_getpc(), cft_map(opcode));
 #endif
 		(*cpufunctbl[opcode])(opcode);
 		cpu_check_ticks();
@@ -5090,7 +5130,7 @@ void execute_normal(void)
 			pc_hist[blocklen++].location = (uae_u16 *)regs.pc_p;
 			uae_u32 opcode = GET_OPCODE;
 #if FLIGHT_RECORDER
-			m68k_record_step(m68k_getpc(), opcode);
+			m68k_record_step(m68k_getpc(), cft_map(opcode));
 #endif
 			(*cpufunctbl[opcode])(opcode);
 			cpu_check_ticks();
@@ -5131,11 +5171,15 @@ void m68k_compile_execute (void)
 setjmpagain:
 	TRY(prb) {
 		for (;;) {
-			if (quit_program == 1) {
+			if (quit_program > 0) {
+				if (quit_program == 1) {
 #if FLIGHT_RECORDER
-				dump_flight_recorder();
+					dump_flight_recorder();
 #endif
-				break;
+					break;
+				}
+				quit_program = 0;
+				m68k_reset ();
 			}
 			m68k_do_compile_execute();
 		}
@@ -5148,7 +5192,7 @@ setjmpagain:
 			regs.fault_pc,
 			regs.mmu_fault_addr, get_long (regs.vbr + 4*prb),
 			regs.regs[15]);
-		flush_icache(0);
+		flush_icache();
 		Exception(prb, 0);
 		goto setjmpagain;
 	}

BasiliskII/src/uae_cpu/compiler/gencomp.c

@@ -93,11 +93,16 @@
 #define DISABLE_I_FSCC
 #define DISABLE_I_MOVE16
 */
+
 #endif /* UAE */
 
 #ifdef UAE
 #define JIT_PATH "jit/"
+#ifdef FSUAE
+#define GEN_PATH "gen/"
+#else
 #define GEN_PATH "jit/"
+#endif
 #define RETURN "return 0;"
 #define RETTYPE "uae_u32"
 #define NEXT_CPU_LEVEL 5
@@ -107,7 +112,6 @@
 #define RETURN "return;"
 #define RETTYPE "void"
 #define NEXT_CPU_LEVEL 4
-#define ua(s) s
 #endif
 
 #define BOOL_TYPE		"int"
@@ -738,8 +742,9 @@ static void genmov16(uae_u32 opcode, struct instr *curi)
 		  "\tadd_l_ri(dst,4);\n"
 		  "\treadlong(src,tmp,scratchie);\n"
 		  "\twritelong_clobber(dst,tmp,scratchie);\n");
-	comprintf("\t} else {\n");
+	comprintf("\t} else\n");
 #endif
+	start_brace();
 	comprintf("\tint tmp=scratchie;\n");
 	comprintf("\tscratchie+=4;\n"
 		"\tget_n_addr(src,src,scratchie);\n"
@@ -755,9 +760,7 @@ static void genmov16(uae_u32 opcode, struct instr *curi)
 		"\tmov_l_Rr(dst,tmp+2,8);\n"
 		"\tforget_about(tmp+2);\n"
 		"\tmov_l_Rr(dst,tmp+3,12);\n");
-#ifdef UAE
+	close_brace();
-	comprintf("\t}\n");
-#endif
 }
 
 static void
@@ -1304,11 +1307,11 @@ genflags (flagtypes type, wordsizes size, const char *value, const char *src, co
 		break;
 	    }
 	    comprintf("\tlive_flags();\n");
-	    comprintf("\tif (needed_flags&FLAG_Z) {\n"
+	    comprintf("\tif (needed_flags&FLAG_Z) {\n");
-		      "\tcmov_l_rr(zero,one,%d);\n"
+	    comprintf("\tcmov_l_rr(zero,one,%d);\n", NATIVE_CC_NE);
-		      "\tset_zero(zero, one);\n" /* No longer need one */
+	    comprintf("\tset_zero(zero, one);\n"); /* No longer need one */
-		      "\tlive_flags();\n"
+	    comprintf("\tlive_flags();\n");
-		      "\t}\n",NATIVE_CC_NE);
+	    comprintf("\t}\n");
 	    comprintf("\tend_needflags();\n");
 	    duplicate_carry();
 	    comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
@@ -2181,158 +2184,63 @@ gen_opcode (unsigned int opcode)
 
 	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	if (curi->smode!=immi) {
-	    if (!noflags) {
-		uses_cmov;
-		start_brace();
-		comprintf("\tint highmask;\n"
-			  "\tint width;\n"
-			  "\tint cdata=scratchie++;\n"
-			  "\tint tmpcnt=scratchie++;\n"
-			  "\tint highshift=scratchie++;\n");
-		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
-			  "\tand_l_ri(tmpcnt,63);\n"
-			  "\tmov_l_ri(cdata,0);\n"
-			  "\tcmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE);
-		/* cdata is now either data (for shift count!=0) or
-		   0 (for shift count==0) */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshra_b_rr(data,cnt);\n"
-					 "\thighmask=0x38;\n"
-					 "\twidth=8;\n");
-		 break;
-		 case sz_word: comprintf("\tshra_w_rr(data,cnt);\n"
-					 "\thighmask=0x30;\n"
-					 "\twidth=16;\n");
-		 break;
-		 case sz_long: comprintf("\tshra_l_rr(data,cnt);\n"
-					 "\thighmask=0x20;\n"
-					 "\twidth=32;\n");
-		 break;
-		 default: assert(0);
-		}
-		comprintf("test_l_ri(cnt,highmask);\n"
-			  "mov_l_ri(highshift,0);\n"
-			  "mov_l_ri(scratchie,width/2);\n"
-			  "cmov_l_rr(highshift,scratchie,%d);\n", NATIVE_CC_NE);
-		/* The x86 masks out bits, so we now make sure that things
-		   really get shifted as much as planned */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
-		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
-		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
-		 default: assert(0);
-		}
-		/* And again */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
-		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
-		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
-		 default: assert(0);
-		}
 
-		/* Result of shift is now in data. Now we need to determine
+	start_brace();
-		   the carry by shifting cdata one less */
+	if (!noflags)
-		comprintf("\tsub_l_ri(tmpcnt,1);\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshra_b_rr(cdata,tmpcnt);\n");break;
-		 case sz_word: comprintf("\tshra_w_rr(cdata,tmpcnt);\n");break;
-		 case sz_long: comprintf("\tshra_l_rr(cdata,tmpcnt);\n");break;
-		 default: assert(0);
-		}
-		/* If the shift count was higher than the width, we need
-		   to pick up the sign from data */
-		comprintf("test_l_ri(tmpcnt,highmask);\n"
-			  "cmov_l_rr(cdata,data,%d);\n", NATIVE_CC_NE);
-		/* And create the flags */
 		comprintf("\tstart_needflags();\n");
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+	if (curi->smode!=immi) {
-		switch(curi->size) {
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
-		}
-		comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
-	    else {
 		uses_cmov;
 		start_brace();
-		comprintf("\tint highmask;\n"
+		comprintf("\tint zero = scratchie++;\n");
-			  "\tint width;\n"
+		comprintf("\tint minus1 = scratchie++;\n");
-			  "\tint highshift=scratchie++;\n");
+		comprintf("\tand_l_ri(cnt,63);\n");
+		comprintf("\tmov_l_ri(zero, 0);\n");
+		comprintf("\tmov_l_ri(minus1, -1);\n");
 		switch(curi->size) {
-		 case sz_byte: comprintf("\tshra_b_rr(data,cnt);\n"
+		 case sz_byte:
-					 "\thighmask=0x38;\n"
+		 	comprintf("\ttest_b_rr(data,data);\n");
-					 "\twidth=8;\n");
+		 	comprintf("\tcmov_l_rr(zero, minus1, NATIVE_CC_MI);\n");
-		 break;
+		 	comprintf("\ttest_l_ri(cnt, 0x38);\n");
-		 case sz_word: comprintf("\tshra_w_rr(data,cnt);\n"
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
-					 "\thighmask=0x30;\n"
+		 	comprintf("\tshra_b_rr(data,cnt);\n");
-					 "\twidth=16;\n");
+		 	break;
-		 break;
+		 case sz_word:
-		 case sz_long: comprintf("\tshra_l_rr(data,cnt);\n"
+		 	comprintf("\ttest_w_rr(data,data);\n");
-					 "\thighmask=0x20;\n"
+		 	comprintf("\tcmov_l_rr(zero, minus1, NATIVE_CC_MI);\n");
-					 "\twidth=32;\n");
+		 	comprintf("\ttest_l_ri(cnt, 0x30);\n");
-		 break;
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
+		 	comprintf("\tshra_w_rr(data,cnt);\n");
+		 	break;
+		 case sz_long:
+		 	comprintf("\ttest_l_rr(data,data);\n");
+		 	comprintf("\tcmov_l_rr(zero, minus1, NATIVE_CC_MI);\n");
+		 	comprintf("\ttest_l_ri(cnt, 0x20);\n");
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
+		 	comprintf("\tshra_l_rr(data,cnt);\n");
+		 	break;
 		 default: assert(0);
 		}
-		comprintf("test_l_ri(cnt,highmask);\n"
+		/* Result of shift is now in data. */
-			  "mov_l_ri(highshift,0);\n"
-			  "mov_l_ri(scratchie,width/2);\n"
-			  "cmov_l_rr(highshift,scratchie,%d);\n",NATIVE_CC_NE);
-		/* The x86 masks out bits, so we now make sure that things
-		   really get shifted as much as planned */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
-		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
-		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
-		 default: assert(0);
-		}
-		/* And again */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshra_b_rr(data,highshift);\n");break;
-		 case sz_word: comprintf("\tshra_w_rr(data,highshift);\n");break;
-		 case sz_long: comprintf("\tshra_l_rr(data,highshift);\n");break;
-		 default: assert(0);
-		}
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
 	}
 	else {
-	    start_brace();
-	    comprintf("\tint tmp=scratchie++;\n"
-		      "\tint bp;\n"
-		      "\tmov_l_rr(tmp,data);\n");
 	    switch(curi->size) {
-	     case sz_byte: comprintf("\tshra_b_ri(data,srcreg);\n"
+	     case sz_byte: comprintf("\tshra_b_ri(data,srcreg);\n"); break;
-				     "\tbp=srcreg-1;\n"); break;
+	     case sz_word: comprintf("\tshra_w_ri(data,srcreg);\n"); break;
-	     case sz_word: comprintf("\tshra_w_ri(data,srcreg);\n"
+	     case sz_long: comprintf("\tshra_l_ri(data,srcreg);\n"); break;
-				     "\tbp=srcreg-1;\n"); break;
-	     case sz_long: comprintf("\tshra_l_ri(data,srcreg);\n"
-				     "\tbp=srcreg-1;\n"); break;
 	     default: assert(0);
 	    }
-
-	    if (!noflags) {
-		comprintf("\tstart_needflags();\n");
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
-		}
-		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-	    }
-	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	}
+	/* And create the flags */
+	if (!noflags) {
+		comprintf("\tlive_flags();\n");
+		comprintf("\tend_needflags();\n");
+		if (curi->smode!=immi)
+			comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4);
+		else
+			comprintf("\tduplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	}
+	genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	break;
 
      case i_ASL:
@@ -2359,129 +2267,54 @@ gen_opcode (unsigned int opcode)
 
 	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	if (curi->smode!=immi) {
-	    if (!noflags) {
-		uses_cmov;
-		start_brace();
-		comprintf("\tint highmask;\n"
-			  "\tint cdata=scratchie++;\n"
-			  "\tint tmpcnt=scratchie++;\n");
-		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
-			  "\tand_l_ri(tmpcnt,63);\n"
-			  "\tmov_l_ri(cdata,0);\n"
-			  "\tcmov_l_rr(cdata,data,%d);\n",NATIVE_CC_NE);
-		/* cdata is now either data (for shift count!=0) or
-		   0 (for shift count==0) */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
-					 "\thighmask=0x38;\n");
-		 break;
-		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
-					 "\thighmask=0x30;\n");
-		 break;
-		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
-					 "\thighmask=0x20;\n");
-		 break;
-		 default: assert(0);
-		}
-		comprintf("test_l_ri(cnt,highmask);\n"
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ);
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
-		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
-		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
-		 default: assert(0);
-		}
-		/* Result of shift is now in data. Now we need to determine
-		   the carry by shifting cdata one less */
-		comprintf("\tsub_l_ri(tmpcnt,1);\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshll_b_rr(cdata,tmpcnt);\n");break;
-		 case sz_word: comprintf("\tshll_w_rr(cdata,tmpcnt);\n");break;
-		 case sz_long: comprintf("\tshll_l_rr(cdata,tmpcnt);\n");break;
-		 default: assert(0);
-		}
-		comprintf("test_l_ri(tmpcnt,highmask);\n"
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(cdata,scratchie,%d);\n",NATIVE_CC_NE);
-		/* And create the flags */
-		comprintf("\tstart_needflags();\n");
 
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+	if (!noflags)
-		switch(curi->size) {
+		comprintf("\tstart_needflags();\n");
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n");
+	if (curi->smode!=immi) {
-		    comprintf("\t bt_l_ri(cdata,7);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n");
-		    comprintf("\t bt_l_ri(cdata,15);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n");
-		    comprintf("\t bt_l_ri(cdata,31);\n"); break;
-		}
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
-	    else {
 		uses_cmov;
 		start_brace();
-		comprintf("\tint highmask;\n");
+		comprintf("\tint zero = scratchie++;\n");
+		comprintf("\tand_l_ri(cnt,63);\n");
+		comprintf("\tmov_l_ri(zero, 0);\n");
 		switch(curi->size) {
-		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
+		 case sz_byte:
-					 "\thighmask=0x38;\n");
+		 	comprintf("\ttest_l_ri(cnt, 0x38);\n");
-		    break;
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
-		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
+		 	comprintf("\tshll_b_rr(data,cnt);\n");
-					 "\thighmask=0x30;\n");
+		 	break;
-		    break;
+		 case sz_word:
-		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
+		 	comprintf("\ttest_l_ri(cnt, 0x30);\n");
-					 "\thighmask=0x20;\n");
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
-		    break;
+		 	comprintf("\tshll_w_rr(data,cnt);\n");
+		 	break;
+		 case sz_long:
+		 	comprintf("\ttest_l_ri(cnt, 0x20);\n");
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
+		 	comprintf("\tshll_l_rr(data,cnt);\n");
+		 	break;
 		 default: assert(0);
 		}
-		comprintf("test_l_ri(cnt,highmask);\n"
+		/* Result of shift is now in data. */
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ);
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
-		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
-		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
-		 default: assert(0);
-		}
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
 	}
 	else {
-	    start_brace();
-	    comprintf("\tint tmp=scratchie++;\n"
-		      "\tint bp;\n"
-		      "\tmov_l_rr(tmp,data);\n");
 	    switch(curi->size) {
-	     case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"
+	     case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"); break;
-				     "\tbp=8-srcreg;\n"); break;
+	     case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"); break;
-	     case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"
+	     case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"); break;
-				     "\tbp=16-srcreg;\n"); break;
-	     case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"
-				     "\tbp=32-srcreg;\n"); break;
 	     default: assert(0);
 	    }
-
-	    if (!noflags) {
-		comprintf("\tstart_needflags();\n");
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
-		}
-		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-	    }
-	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	}
+	/* And create the flags */
+	if (!noflags) {
+		comprintf("\tlive_flags();\n");
+		comprintf("\tend_needflags();\n");
+		if (curi->smode!=immi)
+			comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4);
+		else
+			comprintf("\tduplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	}
+	genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	break;
 
 	 case i_LSR:
@@ -2500,126 +2333,55 @@ gen_opcode (unsigned int opcode)
 
 	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	if (curi->smode!=immi) {
+
-	    if (!noflags) {
+	start_brace();
-		uses_cmov;
+	if (!noflags)
-		start_brace();
-		comprintf("\tint highmask;\n"
-			  "\tint cdata=scratchie++;\n"
-			  "\tint tmpcnt=scratchie++;\n");
-		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
-			  "\tand_l_ri(tmpcnt,63);\n"
-			  "\tmov_l_ri(cdata,0);\n"
-			  "\tcmov_l_rr(cdata,data,%d);\n",NATIVE_CC_NE);
-		/* cdata is now either data (for shift count!=0) or
-		   0 (for shift count==0) */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshrl_b_rr(data,cnt);\n"
-					 "\thighmask=0x38;\n");
-		 break;
-		 case sz_word: comprintf("\tshrl_w_rr(data,cnt);\n"
-					 "\thighmask=0x30;\n");
-		 break;
-		 case sz_long: comprintf("\tshrl_l_rr(data,cnt);\n"
-					 "\thighmask=0x20;\n");
-		 break;
-		 default: assert(0);
-		}
-		comprintf("test_l_ri(cnt,highmask);\n"
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ);
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
-		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
-		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
-		 default: assert(0);
-		}
-		/* Result of shift is now in data. Now we need to determine
-		   the carry by shifting cdata one less */
-		comprintf("\tsub_l_ri(tmpcnt,1);\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshrl_b_rr(cdata,tmpcnt);\n");break;
-		 case sz_word: comprintf("\tshrl_w_rr(cdata,tmpcnt);\n");break;
-		 case sz_long: comprintf("\tshrl_l_rr(cdata,tmpcnt);\n");break;
-		 default: assert(0);
-		}
-		comprintf("test_l_ri(tmpcnt,highmask);\n"
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(cdata,scratchie,%d);\n",NATIVE_CC_NE);
-		/* And create the flags */
 		comprintf("\tstart_needflags();\n");
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+	if (curi->smode!=immi) {
-		switch(curi->size) {
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
-		}
-		comprintf("\t bt_l_ri(cdata,0);\n"); /* Set C */
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
-	    else {
 		uses_cmov;
 		start_brace();
-		comprintf("\tint highmask;\n");
+		comprintf("\tint zero = scratchie++;\n");
+		comprintf("\tand_l_ri(cnt,63);\n");
+		comprintf("\tmov_l_ri(zero, 0);\n");
 		switch(curi->size) {
-		 case sz_byte: comprintf("\tshrl_b_rr(data,cnt);\n"
+		 case sz_byte:
-					 "\thighmask=0x38;\n");
+		 	comprintf("\ttest_l_ri(cnt, 0x38);\n");
-		    break;
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
-		 case sz_word: comprintf("\tshrl_w_rr(data,cnt);\n"
+		 	comprintf("\tshrl_b_rr(data,cnt);\n");
-					 "\thighmask=0x30;\n");
+		 	break;
-		    break;
+		 case sz_word:
-		 case sz_long: comprintf("\tshrl_l_rr(data,cnt);\n"
+		 	comprintf("\ttest_l_ri(cnt, 0x30);\n");
-					 "\thighmask=0x20;\n");
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
-		    break;
+		 	comprintf("\tshrl_w_rr(data,cnt);\n");
+		 	break;
+		 case sz_long:
+		 	comprintf("\ttest_l_ri(cnt, 0x20);\n");
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
+		 	comprintf("\tshrl_l_rr(data, cnt);\n");
+		 	break;
 		 default: assert(0);
 		}
-		comprintf("test_l_ri(cnt,highmask);\n"
+		/* Result of shift is now in data. */
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ);
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
-		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
-		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
-		 default: assert(0);
-		}
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
 	}
 	else {
-	    start_brace();
-	    comprintf("\tint tmp=scratchie++;\n"
-		      "\tint bp;\n"
-		      "\tmov_l_rr(tmp,data);\n");
 	    switch(curi->size) {
-	     case sz_byte: comprintf("\tshrl_b_ri(data,srcreg);\n"
+	     case sz_byte: comprintf("\tshrl_b_ri(data,srcreg);\n"); break;
-				     "\tbp=srcreg-1;\n"); break;
+	     case sz_word: comprintf("\tshrl_w_ri(data,srcreg);\n"); break;
-	     case sz_word: comprintf("\tshrl_w_ri(data,srcreg);\n"
+	     case sz_long: comprintf("\tshrl_l_ri(data,srcreg);\n"); break;
-				     "\tbp=srcreg-1;\n"); break;
-	     case sz_long: comprintf("\tshrl_l_ri(data,srcreg);\n"
-				     "\tbp=srcreg-1;\n"); break;
 	     default: assert(0);
 	    }
-
-	    if (!noflags) {
-		comprintf("\tstart_needflags();\n");
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
-		}
-		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-	    }
-	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	}
+	/* And create the flags */
+	if (!noflags) {
+		comprintf("\tlive_flags();\n");
+		comprintf("\tend_needflags();\n");
+		if (curi->smode!=immi)
+			comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4);
+		else
+			comprintf("\tduplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	}
+	genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	break;
 
 	 case i_LSL:
@@ -2638,128 +2400,55 @@ gen_opcode (unsigned int opcode)
 
 	genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0);
-	if (curi->smode!=immi) {
+
-	    if (!noflags) {
+	start_brace();
-		uses_cmov;
+	if (!noflags)
-		start_brace();
-		comprintf("\tint highmask;\n"
-			  "\tint cdata=scratchie++;\n"
-			  "\tint tmpcnt=scratchie++;\n");
-		comprintf("\tmov_l_rr(tmpcnt,cnt);\n"
-			  "\tand_l_ri(tmpcnt,63);\n"
-			  "\tmov_l_ri(cdata,0);\n"
-			  "\tcmov_l_rr(cdata,data,%d);\n",NATIVE_CC_NE);
-		/* cdata is now either data (for shift count!=0) or
-		   0 (for shift count==0) */
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
-					 "\thighmask=0x38;\n");
-		 break;
-		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
-					 "\thighmask=0x30;\n");
-		 break;
-		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
-					 "\thighmask=0x20;\n");
-		 break;
-		 default: assert(0);
-		}
-		comprintf("test_l_ri(cnt,highmask);\n"
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ);
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
-		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
-		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
-		 default: assert(0);
-		}
-		/* Result of shift is now in data. Now we need to determine
-		   the carry by shifting cdata one less */
-		comprintf("\tsub_l_ri(tmpcnt,1);\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tshll_b_rr(cdata,tmpcnt);\n");break;
-		 case sz_word: comprintf("\tshll_w_rr(cdata,tmpcnt);\n");break;
-		 case sz_long: comprintf("\tshll_l_rr(cdata,tmpcnt);\n");break;
-		 default: assert(0);
-		}
-		comprintf("test_l_ri(tmpcnt,highmask);\n"
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(cdata,scratchie,%d);\n",NATIVE_CC_NE);
-		/* And create the flags */
 		comprintf("\tstart_needflags();\n");
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
+	if (curi->smode!=immi) {
-		switch(curi->size) {
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n");
-		    comprintf("\t bt_l_ri(cdata,7);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n");
-		    comprintf("\t bt_l_ri(cdata,15);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n");
-		    comprintf("\t bt_l_ri(cdata,31);\n"); break;
-		}
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
-	    else {
 		uses_cmov;
 		start_brace();
-		comprintf("\tint highmask;\n");
+		comprintf("\tint zero = scratchie++;\n");
+		comprintf("\tand_l_ri(cnt,63);\n");
+		comprintf("\tmov_l_ri(zero, 0);\n");
 		switch(curi->size) {
-		 case sz_byte: comprintf("\tshll_b_rr(data,cnt);\n"
+		 case sz_byte:
-					 "\thighmask=0x38;\n");
+		 	comprintf("\ttest_l_ri(cnt, 0x38);\n");
-		    break;
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
-		 case sz_word: comprintf("\tshll_w_rr(data,cnt);\n"
+		 	comprintf("\tshll_b_rr(data,cnt);\n");
-					 "\thighmask=0x30;\n");
+		 	break;
-		    break;
+		 case sz_word:
-		 case sz_long: comprintf("\tshll_l_rr(data,cnt);\n"
+		 	comprintf("\ttest_l_ri(cnt, 0x30);\n");
-					 "\thighmask=0x20;\n");
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
-		    break;
+		 	comprintf("\tshll_w_rr(data,cnt);\n");
+		 	break;
+		 case sz_long:
+		 	comprintf("\ttest_l_ri(cnt, 0x20);\n");
+		 	comprintf("\tcmov_l_rr(data, zero, NATIVE_CC_NE);\n");
+		 	comprintf("\tshll_l_rr(data,cnt);\n");
+		 	break;
 		 default: assert(0);
 		}
-		comprintf("test_l_ri(cnt,highmask);\n"
+		/* Result of shift is now in data. */
-			  "mov_l_ri(scratchie,0);\n"
-			  "cmov_l_rr(scratchie,data,%d);\n",NATIVE_CC_EQ);
-		switch(curi->size) {
-		 case sz_byte: comprintf("\tmov_b_rr(data,scratchie);\n");break;
-		 case sz_word: comprintf("\tmov_w_rr(data,scratchie);\n");break;
-		 case sz_long: comprintf("\tmov_l_rr(data,scratchie);\n");break;
-		 default: assert(0);
-		}
-		genastore ("data", curi->dmode, "dstreg", curi->size, "data");
-	    }
 	}
 	else {
-	    start_brace();
-	    comprintf("\tint tmp=scratchie++;\n"
-		      "\tint bp;\n"
-		      "\tmov_l_rr(tmp,data);\n");
 	    switch(curi->size) {
-	     case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"
+	     case sz_byte: comprintf("\tshll_b_ri(data,srcreg);\n"); break;
-				     "\tbp=8-srcreg;\n"); break;
+	     case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"); break;
-	     case sz_word: comprintf("\tshll_w_ri(data,srcreg);\n"
+	     case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"); break;
-				     "\tbp=16-srcreg;\n"); break;
-	     case sz_long: comprintf("\tshll_l_ri(data,srcreg);\n"
-				     "\tbp=32-srcreg;\n"); break;
 	     default: assert(0);
 	    }
-
-	    if (!noflags) {
-		comprintf("\tstart_needflags();\n");
-		comprintf("\tif (needed_flags & FLAG_ZNV)\n");
-		switch(curi->size) {
-		 case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
-		 case sz_word: comprintf("\t  test_w_rr(data,data);\n"); break;
-		 case sz_long: comprintf("\t  test_l_rr(data,data);\n"); break;
-		}
-		comprintf("\t bt_l_ri(tmp,bp);\n"); /* Set C */
-		comprintf("\t live_flags();\n");
-		comprintf("\t end_needflags();\n");
-		comprintf("\t duplicate_carry();\n");
-		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
-	    }
-	    genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	}
+	/* And create the flags */
+	if (!noflags) {
+		comprintf("\tlive_flags();\n");
+		comprintf("\tend_needflags();\n");
+		if (curi->smode!=immi)
+			comprintf("\tsetcc_for_cntzero(cnt, data, %d);\n", curi->size == sz_byte ? 1 : curi->size == sz_word ? 2 : 4);
+		else
+			comprintf("\tduplicate_carry();\n");
+		comprintf("if (!(needed_flags & FLAG_CZNV)) dont_care_flags();\n");
+	}
+	genastore ("data", curi->dmode, "dstreg", curi->size, "data");
 	break;
 
 	 case i_ROL:
@@ -2787,6 +2476,9 @@ gen_opcode (unsigned int opcode)
 
 	if (!noflags) {
 	    comprintf("\tstart_needflags();\n");
+	    /*
+	     * x86 ROL instruction does not set ZF/SF, so we need extra checks here
+	     */
 	    comprintf("\tif (needed_flags & FLAG_ZNV)\n");
 	    switch(curi->size) {
 	     case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
@@ -2825,6 +2517,9 @@ gen_opcode (unsigned int opcode)
 
 	if (!noflags) {
 	    comprintf("\tstart_needflags();\n");
+	    /*
+	     * x86 ROR instruction does not set ZF/SF, so we need extra checks here
+	     */
 	    comprintf("\tif (needed_flags & FLAG_ZNV)\n");
 	    switch(curi->size) {
 	     case sz_byte: comprintf("\t  test_b_rr(data,data);\n"); break;
@@ -3133,7 +2828,7 @@ generate_includes (FILE * f)
 	fprintf (f, "#include \"sysdeps.h\"\n");
 #ifdef UAE
 	fprintf (f, "#include \"options.h\"\n");
-	fprintf (f, "#include \"memory.h\"\n");
+	fprintf (f, "#include \"uae/memory.h\"\n");
 #else
 	fprintf (f, "#include \"m68k.h\"\n");
 	fprintf (f, "#include \"memory.h\"\n");
@@ -3147,7 +2842,6 @@ generate_includes (FILE * f)
 static int postfix;
 
 
-#ifdef UAE
 static char *decodeEA (amodes mode, wordsizes size)
 {
 	static char buffer[80];
@@ -3221,22 +2915,13 @@ static char *decodeEA (amodes mode, wordsizes size)
 	return buffer;
 }
 
-static char *outopcode (int opcode)
+static char *outopcode (const char *name, int opcode)
 {
 	static char out[100];
 	struct instr *ins;
-	int i;
 
 	ins = &table68k[opcode];
-	for (i = 0; lookuptab[i].name[0]; i++) {
+	strcpy (out, name);
-		if (ins->mnemo == lookuptab[i].mnemo)
-			break;
-	}
-	{
-		char *s = ua (lookuptab[i].name);
-		strcpy (out, s);
-		xfree (s);
-	}
 	if (ins->smode == immi)
 		strcat (out, "Q");
 	if (ins->size == sz_byte)
@@ -3254,7 +2939,6 @@ static char *outopcode (int opcode)
 	}
 	return out;
 }
-#endif
 
 
 static void
@@ -3266,11 +2950,7 @@ generate_one_opcode (int rp, int noflags)
     int aborted=0;
     int have_srcreg=0;
     int have_dstreg=0;
-#ifdef UAE
-	char *name;
-#else
 	const char *name;
-#endif
 
     if (table68k[opcode].mnemo == i_ILLG
 	|| table68k[opcode].clev > cpu_level)
@@ -3459,34 +3139,23 @@ generate_one_opcode (int rp, int noflags)
 	else
 		strcpy(flags, "0");
 
-#ifdef UAE
+#ifdef UAE /* RETTYPE != void */
 	comprintf ("return 0;\n");
 #endif
 	comprintf ("}\n");
 
-#ifdef UAE
-	name = ua (lookuptab[i].name);
-#else
 	name = lookuptab[i].name;
-#endif
 	if (aborted) {
 	    fprintf (stblfile, "{ NULL, %u, %s }, /* %s */\n", opcode, flags, name);
 	    com_discard();
 	} else {
 		const char *tbl = noflags ? "nf" : "ff";
-#ifdef UAE
-		printf ("/* %s */\n", outopcode (opcode));
-#else
-		printf ("/* %s */\n", name);
-#endif
 		fprintf (stblfile, "{ op_%x_%d_comp_%s, %u, %s }, /* %s */\n", opcode, postfix, tbl, opcode, flags, name);
 		fprintf (headerfile, "extern compop_func op_%x_%d_comp_%s;\n", opcode, postfix, tbl);
-		printf (RETTYPE " REGPARAM2 op_%x_%d_comp_%s(uae_u32 opcode)\n{\n", opcode, postfix, tbl);
+		printf ("/* %s */\n", outopcode (name, opcode));
+		printf (RETTYPE " REGPARAM2 op_%x_%d_comp_%s(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, tbl, name);
 	    com_flush();
 	}
-#ifdef UAE
-	xfree (name);
-#endif
     }
     opcode_next_clev[rp] = next_cpu_level;
     opcode_last_postfix[rp] = postfix;
@@ -3552,7 +3221,12 @@ void cygwin_mingw_abort()
 }
 #endif
 
+#if defined(FSUAE) && defined (WINDOWS)
+#include "windows.h"
+int WINAPI WinMain(HINSTANCE hInstance, HINSTANCE hPrevInstance, LPSTR lpCmdLine, int nCmdShow)
+#else
 int main(void)
+#endif
 {
     read_table68k ();
     do_merges ();
@@ -3582,6 +3256,7 @@ int main(void)
     generate_includes (stblfile);
 
     printf("#include \"" JIT_PATH "compemu.h\"\n");
+    printf("#include \"" JIT_PATH "flags_x86.h\"\n");
 
     noflags=0;
     generate_func (noflags);

BasiliskII/src/uae_cpu/compiler/gencomp_arm.c

@@ -677,6 +677,7 @@ static void gen_move16(uae_u32 opcode, struct instr *curi) {
 	else if ((opcode & 0xfff8) == 0xf608)
 		comprintf("\tarm_ADD_l_ri8(dstreg+8,16);\n");
 
+	start_brace();
 	comprintf("\tint tmp=scratchie;\n");
 	comprintf("\tscratchie+=4;\n");
 
@@ -693,6 +694,7 @@ static void gen_move16(uae_u32 opcode, struct instr *curi) {
 			"\tmov_l_Rr(dst,tmp+2,8);\n"
 			"\tforget_about(tmp+2);\n"
 			"\tmov_l_Rr(dst,tmp+3,12);\n");
+	close_brace();
 #endif
 }
 
@@ -4632,10 +4634,10 @@ gen_opcode(unsigned long int opcode) {
 		failure;
 		break;
 
-	case i_NATFEAT_ID:
+	// case i_NATFEAT_ID:
-	case i_NATFEAT_CALL:
+	// case i_NATFEAT_CALL:
-		failure;
+	// 	failure;
-		break;
+	// 	break;
 
 	case i_MMUOP:
 		isjump;
@@ -4665,6 +4667,105 @@ static void generate_includes(FILE * f) {
 
 static int postfix;
 
+static char *decodeEA (amodes mode, wordsizes size)
+{
+	static char buffer[80];
+
+	buffer[0] = 0;
+	switch (mode){
+	case Dreg:
+		strcpy (buffer,"Dn");
+		break;
+	case Areg:
+		strcpy (buffer,"An");
+		break;
+	case Aind:
+		strcpy (buffer,"(An)");
+		break;
+	case Aipi:
+		strcpy (buffer,"(An)+");
+		break;
+	case Apdi:
+		strcpy (buffer,"-(An)");
+		break;
+	case Ad16:
+		strcpy (buffer,"(d16,An)");
+		break;
+	case Ad8r:
+		strcpy (buffer,"(d8,An,Xn)");
+		break;
+	case PC16:
+		strcpy (buffer,"(d16,PC)");
+		break;
+	case PC8r:
+		strcpy (buffer,"(d8,PC,Xn)");
+		break;
+	case absw:
+		strcpy (buffer,"(xxx).W");
+		break;
+	case absl:
+		strcpy (buffer,"(xxx).L");
+		break;
+	case imm:
+		switch (size){
+		case sz_byte:
+			strcpy (buffer,"#<data>.B");
+			break;
+		case sz_word:
+			strcpy (buffer,"#<data>.W");
+			break;
+		case sz_long:
+			strcpy (buffer,"#<data>.L");
+			break;
+		default:
+			break;
+		}
+		break;
+	case imm0:
+		strcpy (buffer,"#<data>.B");
+		break;
+	case imm1:
+		strcpy (buffer,"#<data>.W");
+		break;
+	case imm2:
+		strcpy (buffer,"#<data>.L");
+		break;
+	case immi:
+		strcpy (buffer,"#<data>");
+		break;
+
+	default:
+		break;
+	}
+	return buffer;
+}
+
+static char *outopcode (const char *name, int opcode)
+{
+	static char out[100];
+	struct instr *ins;
+
+	ins = &table68k[opcode];
+	strcpy (out, name);
+	if (ins->smode == immi)
+		strcat (out, "Q");
+	if (ins->size == sz_byte)
+		strcat (out,".B");
+	if (ins->size == sz_word)
+		strcat (out,".W");
+	if (ins->size == sz_long)
+		strcat (out,".L");
+	strcat (out," ");
+	if (ins->suse)
+		strcat (out, decodeEA (ins->smode, ins->size));
+	if (ins->duse) {
+		if (ins->suse) strcat (out,",");
+		strcat (out, decodeEA (ins->dmode, ins->size));
+	}
+	return out;
+}
+
+
 static void generate_one_opcode(int rp, int noflags) {
 	int i;
 	uae_u16 smsk, dmsk;
@@ -4858,6 +4959,7 @@ static void generate_one_opcode(int rp, int noflags) {
 					opcode, postfix, tbl, opcode, flags, name);
 			fprintf(headerfile, "extern compop_func op_%x_%d_comp_%s;\n",
 					opcode, postfix, tbl);
+			printf ("/* %s */\n", outopcode (name, opcode));
 			printf(
 					"void REGPARAM2 op_%x_%d_comp_%s(uae_u32 opcode) /* %s */\n{\n",
 					opcode, postfix, tbl, name);

BasiliskII/src/uae_cpu/gencpu.c

@@ -582,7 +582,7 @@ static void genmovemle (uae_u16 opcode)
 
 static void duplicate_carry (void)
 {
-    printf ("\tCOPY_CARRY;\n");
+    printf ("\tCOPY_CARRY();\n");
 }
 
 typedef enum {
@@ -682,7 +682,7 @@ static void genflags_normal (flagtypes type, wordsizes size, char *value, char *
 
     switch (type) {
      case flag_logical:
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	printf ("\tSET_ZFLG (%s == 0);\n", vstr);
 	printf ("\tSET_NFLG (%s < 0);\n", vstr);
 	break;
@@ -697,10 +697,10 @@ static void genflags_normal (flagtypes type, wordsizes size, char *value, char *
 	printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
 	break;
      case flag_z:
-	printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
+	printf ("\tSET_ZFLG (GET_ZFLG() & (%s == 0));\n", vstr);
 	break;
      case flag_zn:
-	printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
+	printf ("\tSET_ZFLG (GET_ZFLG() & (%s == 0));\n", vstr);
 	printf ("\tSET_NFLG (%s < 0);\n", vstr);
 	break;
      case flag_add:
@@ -926,7 +926,7 @@ static void gen_opcode (unsigned long int opcode)
 	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
 	start_brace ();
-	printf ("\tuae_u32 newv = dst - src - (GET_XFLG ? 1 : 0);\n");
+	printf ("\tuae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);\n");
 	genflags (flag_subx, curi->size, "newv", "src", "dst");
 	genflags (flag_zn, curi->size, "newv", "", "");
 	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
@@ -935,14 +935,14 @@ static void gen_opcode (unsigned long int opcode)
 	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
 	start_brace ();
-	printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
+	printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);\n");
 	printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
 	printf ("\tuae_u16 newv, tmp_newv;\n");
 	printf ("\tint bcd = 0;\n");
 	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
 	printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
-	printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
+	printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
-	printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
+	printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);\n");
 	duplicate_carry ();
 	/* Manual says bits NV are undefined though a real 68040 don't change them */
 	if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
@@ -974,7 +974,7 @@ static void gen_opcode (unsigned long int opcode)
 	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
 	start_brace ();
-	printf ("\tuae_u32 newv = dst + src + (GET_XFLG ? 1 : 0);\n");
+	printf ("\tuae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);\n");
 	genflags (flag_addx, curi->size, "newv", "src", "dst");
 	genflags (flag_zn, curi->size, "newv", "", "");
 	genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
@@ -983,7 +983,7 @@ static void gen_opcode (unsigned long int opcode)
 	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
 	genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
 	start_brace ();
-	printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
+	printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);\n");
 	printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
 	printf ("\tuae_u16 newv, tmp_newv;\n");
 	printf ("\tint cflg;\n");
@@ -1014,7 +1014,7 @@ static void gen_opcode (unsigned long int opcode)
      case i_NEGX:
 	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
 	start_brace ();
-	printf ("\tuae_u32 newv = 0 - src - (GET_XFLG ? 1 : 0);\n");
+	printf ("\tuae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);\n");
 	genflags (flag_subx, curi->size, "newv", "src", "0");
 	genflags (flag_zn, curi->size, "newv", "", "");
 	genastore ("newv", curi->smode, "srcreg", curi->size, "src");
@@ -1022,7 +1022,7 @@ static void gen_opcode (unsigned long int opcode)
      case i_NBCD:
 	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
 	start_brace ();
-	printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
+	printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);\n");
 	printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
 	printf ("\tuae_u16 newv;\n");
 	printf ("\tint cflg;\n");
@@ -1295,7 +1295,7 @@ static void gen_opcode (unsigned long int opcode)
 	break;
      case i_TRAPV:
 	sync_m68k_pc ();
-	printf ("\tif (GET_VFLG) { Exception(7,m68k_getpc()); goto %s; }\n", endlabelstr);
+	printf ("\tif (GET_VFLG()) { Exception(7,m68k_getpc()); goto %s; }\n", endlabelstr);
 	need_endlabel = 1;
 	break;
      case i_RTR:
@@ -1505,7 +1505,7 @@ static void gen_opcode (unsigned long int opcode)
 	}
 	printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
 	printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
-	printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr);
+	printf ("\tif ((extra & 0x800) && GET_CFLG()) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr);
 	need_endlabel = 1;
 	break;
 
@@ -1521,7 +1521,7 @@ static void gen_opcode (unsigned long int opcode)
 	}
 	printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
 	printf ("\t\tval = %s & (uae_u32)-(uae_s32)sign;\n", bit_mask (curi->size));
 	printf ("\t\tSET_CFLG (sign);\n");
@@ -1553,7 +1553,7 @@ static void gen_opcode (unsigned long int opcode)
 	 default: abort ();
 	}
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
 	printf ("\t\tSET_VFLG (val != 0);\n");
 	printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
@@ -1589,7 +1589,7 @@ static void gen_opcode (unsigned long int opcode)
 	 default: abort ();
 	}
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
 	printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
 		bit_size (curi->size), bit_size (curi->size) - 1);
@@ -1618,7 +1618,7 @@ static void gen_opcode (unsigned long int opcode)
 	 default: abort ();
 	}
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
 	printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
 		bit_size (curi->size));
@@ -1648,7 +1648,7 @@ static void gen_opcode (unsigned long int opcode)
 	 default: abort ();
 	}
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	if (source_is_imm1_8 (curi))
 	    printf ("{");
 	else
@@ -1675,7 +1675,7 @@ static void gen_opcode (unsigned long int opcode)
 	 default: abort ();
 	}
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	if (source_is_imm1_8 (curi))
 	    printf ("{");
 	else
@@ -1702,7 +1702,7 @@ static void gen_opcode (unsigned long int opcode)
 	 default: abort ();
 	}
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	if (source_is_imm1_8 (curi))
 	    printf ("{");
 	else {
@@ -1713,11 +1713,11 @@ static void gen_opcode (unsigned long int opcode)
 	printf ("\t{\n\tuae_u32 carry;\n");
 	printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
 	printf ("\tcarry = loval & 1;\n");
-	printf ("\tval = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1);\n");
+	printf ("\tval = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);\n");
 	printf ("\tSET_XFLG (carry);\n");
 	printf ("\tval &= %s;\n", bit_mask (curi->size));
 	printf ("\t} }\n");
-	printf ("\tSET_CFLG (GET_XFLG);\n");
+	printf ("\tSET_CFLG (GET_XFLG());\n");
 	genflags (flag_logical_noclobber, curi->size, "val", "", "");
 	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
 	break;
@@ -1732,7 +1732,7 @@ static void gen_opcode (unsigned long int opcode)
 	 default: abort ();
 	}
 	printf ("\tcnt &= 63;\n");
-	printf ("\tCLEAR_CZNV;\n");
+	printf ("\tCLEAR_CZNV();\n");
 	if (source_is_imm1_8 (curi))
 	    printf ("{");
 	else {
@@ -1741,7 +1741,7 @@ static void gen_opcode (unsigned long int opcode)
 	}
 	printf ("\tcnt--;\n");
 	printf ("\t{\n\tuae_u32 carry;\n");
-	printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
+	printf ("\tuae_u32 hival = (val << 1) | GET_XFLG();\n");
 	printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
 	printf ("\tval >>= cnt;\n");
 	printf ("\tcarry = val & 1;\n");
@@ -1750,7 +1750,7 @@ static void gen_opcode (unsigned long int opcode)
 	printf ("\tSET_XFLG (carry);\n");
 	printf ("\tval &= %s;\n", bit_mask (curi->size));
 	printf ("\t} }\n");
-	printf ("\tSET_CFLG (GET_XFLG);\n");
+	printf ("\tSET_CFLG (GET_XFLG());\n");
 	genflags (flag_logical_noclobber, curi->size, "val", "", "");
 	genastore ("val", curi->dmode, "dstreg", curi->size, "data");
 	break;
@@ -1788,7 +1788,7 @@ static void gen_opcode (unsigned long int opcode)
 	printf ("\tSET_CFLG (sign != 0);\n");
 	duplicate_carry ();
 
-	printf ("\tSET_VFLG (GET_VFLG | (sign2 != sign));\n");
+	printf ("\tSET_VFLG (GET_VFLG() | (sign2 != sign));\n");
 	genastore ("val", curi->smode, "srcreg", curi->size, "data");
 	break;
      case i_LSRW:
@@ -1866,7 +1866,7 @@ static void gen_opcode (unsigned long int opcode)
 	}
 	printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
 	printf ("\tval <<= 1;\n");
-	printf ("\tif (GET_XFLG) val |= 1;\n");
+	printf ("\tif (GET_XFLG()) val |= 1;\n");
 	genflags (flag_logical, curi->size, "val", "", "");
 	printf ("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
 	duplicate_carry ();
@@ -1883,7 +1883,7 @@ static void gen_opcode (unsigned long int opcode)
 	}
 	printf ("\tuae_u32 carry = val & 1;\n");
 	printf ("\tval >>= 1;\n");
-	printf ("\tif (GET_XFLG) val |= %s;\n", cmask (curi->size));
+	printf ("\tif (GET_XFLG()) val |= %s;\n", cmask (curi->size));
 	genflags (flag_logical, curi->size, "val", "", "");
 	printf ("SET_CFLG (carry);\n");
 	duplicate_carry ();
@@ -1912,7 +1912,7 @@ static void gen_opcode (unsigned long int opcode)
 	    printf ("\tint ru = (src >> 6) & 7;\n");
 	    printf ("\tint rc = src & 7;\n");
 	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
-	    printf ("\tif (GET_ZFLG)");
+	    printf ("\tif (GET_ZFLG())");
 	    old_brace_level = n_braces;
 	    start_brace ();
 	    genastore ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
@@ -1931,14 +1931,14 @@ static void gen_opcode (unsigned long int opcode)
 	    int old_brace_level = n_braces;
 	    printf ("\tuae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);\n");
 	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
-	    printf ("\tif (GET_ZFLG) {\n");
+	    printf ("\tif (GET_ZFLG()) {\n");
 	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
-	    printf ("\tif (GET_ZFLG) {\n");
+	    printf ("\tif (GET_ZFLG()) {\n");
 	    printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
 	    printf ("\tput_word(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
 	    printf ("\t}}\n");
 	    pop_braces (old_brace_level);
-	    printf ("\tif (! GET_ZFLG) {\n");
+	    printf ("\tif (! GET_ZFLG()) {\n");
 	    printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = (m68k_dreg(regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
 	    printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = (m68k_dreg(regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
 	    printf ("\t}\n");
@@ -1946,14 +1946,14 @@ static void gen_opcode (unsigned long int opcode)
 	    int old_brace_level = n_braces;
 	    printf ("\tuae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);\n");
 	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
-	    printf ("\tif (GET_ZFLG) {\n");
+	    printf ("\tif (GET_ZFLG()) {\n");
 	    genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
-	    printf ("\tif (GET_ZFLG) {\n");
+	    printf ("\tif (GET_ZFLG()) {\n");
 	    printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n");
 	    printf ("\tput_long(rn1, m68k_dreg(regs, (extra >> 6) & 7));\n");
 	    printf ("\t}}\n");
 	    pop_braces (old_brace_level);
-	    printf ("\tif (! GET_ZFLG) {\n");
+	    printf ("\tif (! GET_ZFLG()) {\n");
 	    printf ("\tm68k_dreg(regs, (extra >> 22) & 7) = dst1;\n");
 	    printf ("\tm68k_dreg(regs, (extra >> 6) & 7) = dst2;\n");
 	    printf ("\t}\n");
@@ -2053,7 +2053,7 @@ static void gen_opcode (unsigned long int opcode)
 	    printf ("\ttmp = ~tmp;\n");
 	    break;
 	 case i_BFEXTS:
-	    printf ("\tif (GET_NFLG) tmp |= width == 32 ? 0 : (-1 << width);\n");
+	    printf ("\tif (GET_NFLG()) tmp |= width == 32 ? 0 : (-1 << width);\n");
 	    printf ("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
 	    break;
 	 case i_BFCLR:
@@ -2185,18 +2185,40 @@ static void gen_opcode (unsigned long int opcode)
 	printf ("\tfpuop_restore(opcode);\n");
 	break;
      case i_CINVL:
+        printf("\n#ifdef USE_JIT\n");
+ 	printf ("\tif (opcode&0x80)\n"
+		"\t\tflush_icache();\n");
+	printf("#endif\n");
+	break;
      case i_CINVP:
+        printf("\n#ifdef USE_JIT\n");
+	printf ("\tif (opcode&0x80)\n"
+		"\t\tflush_icache();\n");
+	printf("#endif\n");
+	break;
      case i_CINVA:
-	/* gb-- srcreg now contains the cache field */
+        printf("\n#ifdef USE_JIT\n");
-	printf ("\tif (srcreg&0x2)\n");
+	printf ("\tif (opcode&0x80)\n"
-	printf ("\t\tflush_icache(%d);\n", 30 + ((opcode >> 3) & 3)); 
+		"\t\tflush_icache();\n");
+	printf("#endif\n");
 	break;
      case i_CPUSHL:
+        printf("\n#ifdef USE_JIT\n");
+	printf ("\tif (opcode&0x80)\n"
+		"\t\tflush_icache();\n");
+	printf("#endif\n");
+	break;
      case i_CPUSHP:
+        printf("\n#ifdef USE_JIT\n");
+	printf ("\tif (opcode&0x80)\n"
+		"\t\tflush_icache();\n");
+	printf("#endif\n");
+	break;
      case i_CPUSHA:
-	/* gb-- srcreg now contains the cache field */
+        printf("\n#ifdef USE_JIT\n");
-	printf ("\tif (srcreg&0x2)\n");
+	printf ("\tif (opcode&0x80)\n"
-	printf ("\t\tflush_icache(%d);\n", 40 + ((opcode >> 3) & 3)); 
+		"\t\tflush_icache();\n");
+	printf("#endif\n");
 	break;
      case i_MOVE16:
 	if ((opcode & 0xfff8) == 0xf620) {

BasiliskII/src/uae_cpu/m68k.h

@@ -25,67 +25,108 @@
 
 #ifdef OPTIMIZED_FLAGS
 
-#if defined(X86_ASSEMBLY) || defined(X86_64_ASSEMBLY) || defined(MSVC_INTRINSICS)
+#if (defined(CPU_i386) && defined(X86_ASSEMBLY)) || (defined(CPU_x86_64) && defined(X86_64_ASSEMBLY))
+
+# include <cstdlib>
 
 #ifndef SAHF_SETO_PROFITABLE
 
+/*
+ * Machine dependent structure for holding the 68k CCR flags
+ */
 /* PUSH/POP instructions are naturally 64-bit sized on x86-64, thus
    unsigned long hereunder is either 64-bit or 32-bit wide depending
    on the target.  */
 struct flag_struct {
-    unsigned long cznv;
+#if defined(CPU_x86_64)
-    unsigned long x;
+    uint64 cznv;
+    uint64 x;
+#else
+    uint32 cznv;
+    uint32 x;
+#endif
 };
 
-#define FLAGVAL_Z	0x40
+/*
-#define FLAGVAL_N	0x80
+ * The bits in the cznv field in the above structure are assigned to
+ * allow the easy mirroring of the x86 rFLAGS register.
+ *
+ * The 68k CZNV flags are thus assigned in cznv as:
+ *
+ * 76543210  FEDCBA98 --------- ---------
+ * SZxxxxxC  xxxxVxxx xxxxxxxxx xxxxxxxxx
+ */
 
-#define SET_ZFLG(y)	(regflags.cznv = (((uae_u32)regflags.cznv) & ~0x40) | (((y) & 1) << 6))
+#define FLAGBIT_N   7
-#define SET_CFLG(y)	(regflags.cznv = (((uae_u32)regflags.cznv) & ~1) | ((y) & 1))
+#define FLAGBIT_Z   6
-#define SET_VFLG(y)	(regflags.cznv = (((uae_u32)regflags.cznv) & ~0x800) | (((y) & 1) << 11))
+#define FLAGBIT_C   0
-#define SET_NFLG(y)	(regflags.cznv = (((uae_u32)regflags.cznv) & ~0x80) | (((y) & 1) << 7))
+#define FLAGBIT_V   11
-#define SET_XFLG(y)	(regflags.x = (y))
+#define FLAGBIT_X   0 /* must be in position 0 for duplicate_carry() to work */
 
-#define GET_ZFLG	((regflags.cznv >> 6) & 1)
+#define FLAGVAL_N   (1 << FLAGBIT_N)
-#define GET_CFLG	(regflags.cznv & 1)
+#define FLAGVAL_Z   (1 << FLAGBIT_Z)
-#define GET_VFLG	((regflags.cznv >> 11) & 1)
+#define FLAGVAL_C   (1 << FLAGBIT_C)
-#define GET_NFLG	((regflags.cznv >> 7) & 1)
+#define FLAGVAL_V   (1 << FLAGBIT_V)
-#define GET_XFLG	(regflags.x & 1)
+#define FLAGVAL_X   (1 << FLAGBIT_X)
 
-#define CLEAR_CZNV	(regflags.cznv = 0)
+#define SET_ZFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z))
-#define GET_CZNV	(regflags.cznv)
+#define SET_CFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C))
-#define IOR_CZNV(X)	(regflags.cznv |= (X))
+#define SET_VFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V))
-#define SET_CZNV(X)	(regflags.cznv = (X))
+#define SET_NFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_N) | (((y) & 1) << FLAGBIT_N))
+#define SET_XFLG(y) (regflags.x = ((y) & 1) << FLAGBIT_X)
 
-#define COPY_CARRY	(regflags.x = regflags.cznv)
+#define GET_ZFLG()	((regflags.cznv >> FLAGBIT_Z) & 1)
+#define GET_CFLG()	((regflags.cznv >> FLAGBIT_C) & 1)
+#define GET_VFLG()	((regflags.cznv >> FLAGBIT_V) & 1)
+#define GET_NFLG()	((regflags.cznv >> FLAGBIT_N) & 1)
+#define GET_XFLG()	((regflags.x    >> FLAGBIT_X) & 1)
 
-extern struct flag_struct regflags ASM_SYM ("regflags");
+#define CLEAR_CZNV()	(regflags.cznv = 0)
+#define GET_CZNV()		(regflags.cznv)
+#define IOR_CZNV(X)		(regflags.cznv |= (X))
+#define SET_CZNV(X)		(regflags.cznv = (X))
 
-static __inline__ int cctrue(int cc)
+#define COPY_CARRY()	(regflags.x = regflags.cznv >> (FLAGBIT_C - FLAGBIT_X))
+
+extern struct flag_struct regflags __asm__ ("regflags");
+
+/*
+ * Test CCR condition
+ */
+static inline int cctrue(int cc)
 {
     uae_u32 cznv = regflags.cznv;
-    switch(cc){
+
-     case 0: return 1;                       /* T */
+    switch (cc) {
-     case 1: return 0;                       /* F */
+    case 0:  return 1;                              /*              T  */
-     case 2: return (cznv & 0x41) == 0; /* !GET_CFLG && !GET_ZFLG;  HI */
+    case 1:  return 0;                              /*              F  */
-     case 3: return (cznv & 0x41) != 0; /* GET_CFLG || GET_ZFLG;    LS */
+    case 2:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0;              /* !CFLG && !ZFLG       HI */
-     case 4: return (cznv & 1) == 0;        /* !GET_CFLG;               CC */
+    case 3:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0;              /*  CFLG || ZFLG        LS */
-     case 5: return (cznv & 1) != 0;           /* GET_CFLG;                CS */
+    case 4:  return (cznv & FLAGVAL_C) == 0;                    /* !CFLG            CC */
-     case 6: return (cznv & 0x40) == 0; /* !GET_ZFLG;               NE */
+    case 5:  return (cznv & FLAGVAL_C) != 0;                    /*  CFLG            CS */
-     case 7: return (cznv & 0x40) != 0; /* GET_ZFLG;                EQ */
+    case 6:  return (cznv & FLAGVAL_Z) == 0;                    /* !ZFLG            NE */
-     case 8: return (cznv & 0x800) == 0;/* !GET_VFLG;               VC */
+    case 7:  return (cznv & FLAGVAL_Z) != 0;                    /*  ZFLG            EQ */
-     case 9: return (cznv & 0x800) != 0;/* GET_VFLG;                VS */
+    case 8:  return (cznv & FLAGVAL_V) == 0;                    /* !VFLG            VC */
-     case 10:return (cznv & 0x80) == 0; /* !GET_NFLG;               PL */
+    case 9:  return (cznv & FLAGVAL_V) != 0;                    /*  VFLG            VS */
-     case 11:return (cznv & 0x80) != 0; /* GET_NFLG;                MI */
+    case 10: return (cznv & FLAGVAL_N) == 0;                    /* !NFLG            PL */
-     case 12:return (((cznv << 4) ^ cznv) & 0x800) == 0; /* GET_NFLG == GET_VFLG;             GE */
+    case 11: return (cznv & FLAGVAL_N) != 0;                    /*  NFLG            MI */
-     case 13:return (((cznv << 4) ^ cznv) & 0x800) != 0;/* GET_NFLG != GET_VFLG;             LT */
+#if FLAGBIT_N > FLAGBIT_V
-     case 14:
+    case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0;  /*  NFLG == VFLG        GE */
-	cznv &= 0x8c0;
+    case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0;  /*  NFLG != VFLG        LT */
-	return (((cznv << 4) ^ cznv) & 0x840) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG);  GT */
+    case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* !ZFLG && (NFLG == VFLG)   GT */
-     case 15:
+         return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0;
-	cznv &= 0x8c0;
+    case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* ZFLG || (NFLG != VFLG)   LE */
-	return (((cznv << 4) ^ cznv) & 0x840) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG);   LE */
+         return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0;
+#else
+    case 12: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) == 0;  /*  NFLG == VFLG        GE */
+    case 13: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) != 0;  /*  NFLG != VFLG        LT */
+    case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* !ZFLG && (NFLG == VFLG)   GT */
+         return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) == 0;
+    case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* ZFLG || (NFLG != VFLG)   LE */
+         return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) != 0;
+#endif
     }
+    abort ();
     return 0;
 }
 
@@ -93,34 +134,34 @@ static __inline__ int cctrue(int cc)
   __asm__ __volatile__ ("andl %1,%1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv) : "r" (v) : "cc")
+			: "=rm" (regflags.cznv) : "r" (v) : "memory", "cc")
 
 #define optflag_testw(v) \
   __asm__ __volatile__ ("andw %w1,%w1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv) : "r" (v) : "cc")
+			: "=rm" (regflags.cznv) : "r" (v) : "memory", "cc")
 
 #define optflag_testb(v) \
   __asm__ __volatile__ ("andb %b1,%b1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv) : "q" (v) : "cc")
+			: "=rm" (regflags.cznv) : "q" (v) : "memory", "cc")
 
 #define optflag_addl(v, s, d) do { \
   __asm__ __volatile__ ("addl %k2,%k1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \
+			: "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \
-    COPY_CARRY; \
+    COPY_CARRY(); \
     } while (0)
 
 #define optflag_addw(v, s, d) do { \
   __asm__ __volatile__ ("addw %w2,%w1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \
+			: "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \
-    COPY_CARRY; \
+    COPY_CARRY(); \
     } while (0)
 
 #define optflag_addb(v, s, d) do { \
@@ -128,113 +169,151 @@ static __inline__ int cctrue(int cc)
 			"pushf\n\t" \
 			"pop %0\n\t" \
 			: "=r" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "cc"); \
-    COPY_CARRY; \
+    COPY_CARRY(); \
     } while (0)
 
 #define optflag_subl(v, s, d) do { \
   __asm__ __volatile__ ("subl %k2,%k1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \
+			: "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \
-    COPY_CARRY; \
+    COPY_CARRY(); \
     } while (0)
 
 #define optflag_subw(v, s, d) do { \
   __asm__ __volatile__ ("subw %w2,%w1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "cc"); \
+			: "=rm" (regflags.cznv), "=r" (v) : "rmi" (s), "1" (d) : "memory", "cc"); \
-    COPY_CARRY; \
+    COPY_CARRY(); \
     } while (0)
 
 #define optflag_subb(v, s, d) do { \
   __asm__ __volatile__ ("subb %b2,%b1\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "cc"); \
+			: "=rm" (regflags.cznv), "=q" (v) : "qmi" (s), "1" (d) : "memory", "cc"); \
-    COPY_CARRY; \
+    COPY_CARRY(); \
     } while (0)
 
 #define optflag_cmpl(s, d) \
   __asm__ __volatile__ ("cmpl %k1,%k2\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv) : "rmi" (s), "r" (d) : "cc")
+			: "=rm" (regflags.cznv) : "rmi" (s), "r" (d) : "memory", "cc")
 
 #define optflag_cmpw(s, d) \
   __asm__ __volatile__ ("cmpw %w1,%w2\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv) : "rmi" (s), "r" (d) : "cc")
+			: "=rm" (regflags.cznv) : "rmi" (s), "r" (d) : "memory", "cc")
 
 #define optflag_cmpb(s, d) \
   __asm__ __volatile__ ("cmpb %b1,%b2\n\t" \
 			"pushf\n\t" \
 			"pop %0\n\t" \
-			: "=r" (regflags.cznv) : "qmi" (s), "q" (d) : "cc")
+			: "=rm" (regflags.cznv) : "qmi" (s), "q" (d) : "memory", "cc")
 
-#else
+#else /* !SAHF_SETO_PROFITABLE */
 
+/*
+ * Machine dependent structure for holding the 68k CCR flags
+ */
 struct flag_struct {
-    uae_u32 cznv;
+	uae_u32 cznv;
-    uae_u32 x;
+	uae_u32 x;
 };
 
-#define FLAGVAL_Z	0x4000
+extern struct flag_struct regflags __asm__ ("regflags");
-#define FLAGVAL_N	0x8000
 
-#define SET_ZFLG(y)	(regflags.cznv = (regflags.cznv & ~0x4000) | (((y) & 1) << 14))
+/*
-#define SET_CFLG(y)	(regflags.cznv = (regflags.cznv & ~0x100) | (((y) & 1) << 8))
+ * The bits in the cznv field in the above structure are assigned to
-#define SET_VFLG(y)	(regflags.cznv = (regflags.cznv & ~0x1) | (((y) & 1)))
+ * allow the easy mirroring of the x86 condition flags. (For example,
-#define SET_NFLG(y)	(regflags.cznv = (regflags.cznv & ~0x8000) | (((y) & 1) << 15))
+ * from the AX register - the x86 overflow flag can be copied to AL
-#define SET_XFLG(y)	(regflags.x = (y))
+ * with a setto %AL instr and the other flags copied to AH with an
+ * lahf instr).
+ *
+ * The 68k CZNV flags are thus assigned in cznv as:
+ *
+ * <--AL-->  <--AH-->
+ * 76543210  FEDCBA98 --------- ---------
+ * xxxxxxxV  NZxxxxxC xxxxxxxxx xxxxxxxxx
+ */
 
-#define GET_ZFLG	((regflags.cznv >> 14) & 1)
+#define FLAGBIT_N   15
-#define GET_CFLG	((regflags.cznv >> 8) & 1)
+#define FLAGBIT_Z   14
-#define GET_VFLG	((regflags.cznv >> 0) & 1)
+#define FLAGBIT_C   8
-#define GET_NFLG	((regflags.cznv >> 15) & 1)
+#define FLAGBIT_V   0
-#define GET_XFLG	(regflags.x & 1)
+#define FLAGBIT_X   0 /* must be in position 0 for duplicate_carry() to work */
 
-#define CLEAR_CZNV 	(regflags.cznv = 0)
+#define FLAGVAL_N   (1 << FLAGBIT_N)
-#define GET_CZNV	(regflags.cznv)
+#define FLAGVAL_Z   (1 << FLAGBIT_Z)
-#define IOR_CZNV(X)	(regflags.cznv |= (X))
+#define FLAGVAL_C   (1 << FLAGBIT_C)
-#define SET_CZNV(X)	(regflags.cznv = (X))
+#define FLAGVAL_V   (1 << FLAGBIT_V)
+#define FLAGVAL_X   (1 << FLAGBIT_X)
 
-#define COPY_CARRY	(regflags.x = (regflags.cznv)>>8)
+#define SET_ZFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z))
+#define SET_CFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C))
+#define SET_VFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V))
+#define SET_NFLG(y) (regflags.cznv = (((uae_u32)regflags.cznv) & ~FLAGVAL_N) | (((y) & 1) << FLAGBIT_N))
+#define SET_XFLG(y) (regflags.x    = ((y) & 1) << FLAGBIT_X)
 
-extern struct flag_struct regflags ASM_SYM("regflags");
+#define GET_ZFLG()	((regflags.cznv >> FLAGBIT_Z) & 1)
+#define GET_CFLG()	((regflags.cznv >> FLAGBIT_C) & 1)
+#define GET_VFLG()	((regflags.cznv >> FLAGBIT_V) & 1)
+#define GET_NFLG()	((regflags.cznv >> FLAGBIT_N) & 1)
+#define GET_XFLG()	((regflags.x    >> FLAGBIT_X) & 1)
 
-static __inline__ int cctrue(int cc)
+#define CLEAR_CZNV()	(regflags.cznv = 0)
+#define GET_CZNV()		(regflags.cznv)
+#define IOR_CZNV(X)		(regflags.cznv |= (X))
+#define SET_CZNV(X)		(regflags.cznv = (X))
+
+#define COPY_CARRY()	(regflags.x = regflags.cznv >> (FLAGBIT_C - FLAGBIT_X))
+
+
+/*
+ * Test CCR condition
+ */
+static inline int cctrue(int cc)
 {
     uae_u32 cznv = regflags.cznv;
-    switch(cc){
+
-     case 0: return 1;                       /* T */
+    switch (cc) {
-     case 1: return 0;                       /* F */
+    case 0:  return 1;                              /*              T  */
-     case 2: return (cznv & 0x4100) == 0; /* !GET_CFLG && !GET_ZFLG;  HI */
+    case 1:  return 0;                              /*              F  */
-     case 3: return (cznv & 0x4100) != 0; /* GET_CFLG || GET_ZFLG;    LS */
+    case 2:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0;              /* !CFLG && !ZFLG       HI */
-     case 4: return (cznv & 0x100) == 0;  /* !GET_CFLG;               CC */
+    case 3:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0;              /*  CFLG || ZFLG        LS */
-     case 5: return (cznv & 0x100) != 0;  /* GET_CFLG;                CS */
+    case 4:  return (cznv & FLAGVAL_C) == 0;                    /* !CFLG            CC */
-     case 6: return (cznv & 0x4000) == 0; /* !GET_ZFLG;               NE */
+    case 5:  return (cznv & FLAGVAL_C) != 0;                    /*  CFLG            CS */
-     case 7: return (cznv & 0x4000) != 0; /* GET_ZFLG;                EQ */
+    case 6:  return (cznv & FLAGVAL_Z) == 0;                    /* !ZFLG            NE */
-     case 8: return (cznv & 0x01) == 0;   /* !GET_VFLG;               VC */
+    case 7:  return (cznv & FLAGVAL_Z) != 0;                    /*  ZFLG            EQ */
-     case 9: return (cznv & 0x01) != 0;   /* GET_VFLG;                VS */
+    case 8:  return (cznv & FLAGVAL_V) == 0;                    /* !VFLG            VC */
-     case 10:return (cznv & 0x8000) == 0; /* !GET_NFLG;               PL */
+    case 9:  return (cznv & FLAGVAL_V) != 0;                    /*  VFLG            VS */
-     case 11:return (cznv & 0x8000) != 0; /* GET_NFLG;                MI */
+    case 10: return (cznv & FLAGVAL_N) == 0;                    /* !NFLG            PL */
-     case 12:return (((cznv << 15) ^ cznv) & 0x8000) == 0; /* GET_NFLG == GET_VFLG;             GE */
+    case 11: return (cznv & FLAGVAL_N) != 0;                    /*  NFLG            MI */
-     case 13:return (((cznv << 15) ^ cznv) & 0x8000) != 0;/* GET_NFLG != GET_VFLG;             LT */
+#if FLAGBIT_N > FLAGBIT_V
-     case 14:
+    case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0;  /*  NFLG == VFLG        GE */
-	cznv &= 0xc001;
+    case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0;  /*  NFLG != VFLG        LT */
-	return (((cznv << 15) ^ cznv) & 0xc000) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG);  GT */
+    case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* !ZFLG && (NFLG == VFLG)   GT */
-     case 15:
+         return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0;
-	cznv &= 0xc001;
+    case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* ZFLG || (NFLG != VFLG)   LE */
-	return (((cznv << 15) ^ cznv) & 0xc000) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG);   LE */
+         return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0;
+#else
+    case 12: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) == 0;  /*  NFLG == VFLG        GE */
+    case 13: return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & FLAGVAL_V) != 0;  /*  NFLG != VFLG        LT */
+    case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* !ZFLG && (NFLG == VFLG)   GT */
+         return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) == 0;
+    case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* ZFLG || (NFLG != VFLG)   LE */
+         return (((cznv << (FLAGBIT_V - FLAGBIT_N)) ^ cznv) & (FLAGVAL_V | FLAGVAL_Z)) != 0;
+#endif
     }
-    abort();
+    abort ();
     return 0;
 }
 
 /* Manually emit LAHF instruction so that 64-bit assemblers can grok it */
-#if defined __x86_64__ && defined __GNUC__
+#if defined CPU_x86_64 && defined __GNUC__
 #define ASM_LAHF ".byte 0x9f"
 #else
 #define ASM_LAHF "lahf"
@@ -273,7 +352,7 @@ static __inline__ int cctrue(int cc)
 			"movb %%al,regflags\n\t" \
 			"movb %%ah,regflags+1\n\t" \
 			: "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \
-			COPY_CARRY; \
+			COPY_CARRY(); \
 	} while (0)
 
 #define optflag_addw(v, s, d) do { \
@@ -283,7 +362,7 @@ static __inline__ int cctrue(int cc)
 			"movb %%al,regflags\n\t" \
 			"movb %%ah,regflags+1\n\t" \
 			: "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \
-			COPY_CARRY; \
+			COPY_CARRY(); \
     } while (0)
 
 #define optflag_addb(v, s, d) do { \
@@ -293,7 +372,7 @@ static __inline__ int cctrue(int cc)
 			"movb %%al,regflags\n\t" \
 			"movb %%ah,regflags+1\n\t" \
 			: "=q" (v) : "qmi" (s), "0" (d) : "%eax","cc","memory"); \
-			COPY_CARRY; \
+			COPY_CARRY(); \
     } while (0)
 
 #define optflag_subl(v, s, d) do { \
@@ -303,7 +382,7 @@ static __inline__ int cctrue(int cc)
 			"movb %%al,regflags\n\t" \
 			"movb %%ah,regflags+1\n\t" \
 			: "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \
-			COPY_CARRY; \
+			COPY_CARRY(); \
     } while (0)
 
 #define optflag_subw(v, s, d) do { \
@@ -313,7 +392,7 @@ static __inline__ int cctrue(int cc)
 			"movb %%al,regflags\n\t" \
 			"movb %%ah,regflags+1\n\t" \
 			: "=r" (v) : "rmi" (s), "0" (d) : "%eax","cc","memory"); \
-			COPY_CARRY; \
+			COPY_CARRY(); \
     } while (0)
 
 #define optflag_subb(v, s, d) do { \
@@ -323,7 +402,7 @@ static __inline__ int cctrue(int cc)
 			"movb %%al,regflags\n\t" \
 			"movb %%ah,regflags+1\n\t" \
 			: "=q" (v) : "qmi" (s), "0" (d) : "%eax","cc","memory"); \
-			COPY_CARRY; \
+			COPY_CARRY(); \
     } while (0)
 
 #define optflag_cmpl(s, d) \
@@ -340,7 +419,7 @@ static __inline__ int cctrue(int cc)
 			"seto %%al\n\t" \
 			"movb %%al,regflags\n\t" \
 			"movb %%ah,regflags+1\n\t" \
-			: : "rmi" (s), "r" (d) : "%eax","cc","memory");
+			: : "rmi" (s), "r" (d) : "%eax","cc","memory")
 
 #define optflag_cmpb(s, d) \
   __asm__ __volatile__ ("cmpb %b0,%b1\n\t" \
@@ -350,10 +429,306 @@ static __inline__ int cctrue(int cc)
 			"movb %%ah,regflags+1\n\t" \
 			: : "qmi" (s), "q" (d) : "%eax","cc","memory")
 
+#endif /* SAHF_SETO_PROFITABLE */
+
+#elif defined(CPU_arm) && defined(ARM_ASSEMBLY)
+
+/*
+ * Machine dependent structure for holding the 68k CCR flags
+ */
+struct flag_struct {
+	uae_u32 nzcv;
+	uae_u32 x;
+};
+
+#define FLAGBIT_N   31
+#define FLAGBIT_Z   30
+#define FLAGBIT_C   29
+#define FLAGBIT_V   28
+#define FLAGBIT_X   FLAGBIT_C /* must be in the same position in as x flag */
+
+#define FLAGVAL_N   (1 << FLAGBIT_N)
+#define FLAGVAL_Z   (1 << FLAGBIT_Z)
+#define FLAGVAL_C   (1 << FLAGBIT_C)
+#define FLAGVAL_V   (1 << FLAGBIT_V)
+#define FLAGVAL_X   (1 << FLAGBIT_X)
+
+#define SET_NFLG(y)		(regflags.nzcv = (regflags.nzcv & ~FLAGVAL_N) | (((y) & 1) << FLAGBIT_N))
+#define SET_ZFLG(y)		(regflags.nzcv = (regflags.nzcv & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z))
+#define SET_CFLG(y)		(regflags.nzcv = (regflags.nzcv & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C))
+#define SET_VFLG(y)		(regflags.nzcv = (regflags.nzcv & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V))
+#define SET_XFLG(y)		(regflags.x = ((y) & 1) << FLAGBIT_X)
+
+#define GET_NFLG()		((regflags.nzcv >> FLAGBIT_N) & 1)
+#define GET_ZFLG()		((regflags.nzcv >> FLAGBIT_Z) & 1)
+#define GET_CFLG()		((regflags.nzcv >> FLAGBIT_C) & 1)
+#define GET_VFLG()		((regflags.nzcv >> FLAGBIT_V) & 1)
+#define GET_XFLG()		((regflags.x    >> FLAGBIT_X) & 1)
+
+#define CLEAR_CZNV()	(regflags.nzcv = 0)
+#define GET_CZNV()		(regflags.nzcv)
+#define IOR_CZNV(X)		(regflags.nzcv |= (X))
+#define SET_CZNV(X)		(regflags.nzcv = (X))
+
+#define COPY_CARRY()	(regflags.x = regflags.nzcv >> (FLAGBIT_C - FLAGBIT_X))
+
+extern struct flag_struct regflags __asm__ ("regflags");
+
+/*
+ * Test CCR condition
+ */
+static inline int cctrue(int cc)
+{
+    unsigned int nzcv = regflags.nzcv;
+    switch(cc){
+     case 0: return 1;                       /* T */
+     case 1: return 0;                       /* F */
+     case 2: return (nzcv & (FLAGVAL_C | FLAGVAL_Z)) == 0; /* !GET_CFLG && !GET_ZFLG;  HI */
+     case 3: return (nzcv & (FLAGVAL_C | FLAGVAL_Z)) != 0; /* GET_CFLG || GET_ZFLG;    LS */
+     case 4: return (nzcv & FLAGVAL_C) == 0; /* !GET_CFLG;               CC */
+     case 5: return (nzcv & FLAGVAL_C) != 0; /* GET_CFLG;                CS */
+     case 6: return (nzcv & FLAGVAL_Z) == 0; /* !GET_ZFLG;               NE */
+     case 7: return (nzcv & FLAGVAL_Z) != 0; /* GET_ZFLG;                EQ */
+     case 8: return (nzcv & FLAGVAL_V) == 0; /* !GET_VFLG;               VC */
+     case 9: return (nzcv & FLAGVAL_V) != 0; /* GET_VFLG;                VS */
+     case 10:return (nzcv & FLAGVAL_N) == 0; /* !GET_NFLG;               PL */
+     case 11:return (nzcv & FLAGVAL_N) != 0; /* GET_NFLG;                MI */
+     case 12:return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & FLAGVAL_N) == 0; /* GET_NFLG == GET_VFLG;             GE */
+     case 13:return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & FLAGVAL_N) != 0; /* GET_NFLG != GET_VFLG;             LT */
+     case 14: nzcv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);
+        return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & (FLAGVAL_N | FLAGVAL_Z)) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG);  GT */
+     case 15: nzcv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);
+        return (((nzcv << (FLAGBIT_N - FLAGBIT_V)) ^ nzcv) & (FLAGVAL_N | FLAGVAL_Z)) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG);   LE */
+    }
+    return 0;
+}
+
+#define optflag_testl(v) do {\
+  __asm__ __volatile__ ("tst %[rv],%[rv]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "bic %[nzcv],#0x30000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rv] "r" (v) \
+                        : "cc"); \
+  } while(0)
+
+#define optflag_addl(v, s, d) do { \
+  __asm__ __volatile__ ("adds %[rv],%[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_subl(v, s, d) do { \
+  __asm__ __volatile__ ("subs %[rv],%[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_cmpl(s, d) do { \
+  __asm__ __volatile__ ("cmp %[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rs] "ri" (s), [rd] "0" (d) \
+                        : "cc"); \
+  } while(0)
+
+#if defined(ARMV6_ASSEMBLY)
+
+// #pragma message "ARM/v6 Assembly optimized flags"
+
+#define optflag_testw(v) do { \
+  __asm__ __volatile__ ("sxth %[rv],%[rv]\n\t" \
+                        "tst %[rv],%[rv]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "bic %[nzcv],#0x30000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rv] "0" (v) \
+                        : "cc"); \
+        }while(0)
+
+#define optflag_testb(v) do {\
+  __asm__ __volatile__ ("sxtb %[rv],%[rv]\n\t" \
+                        "tst %[rv],%[rv]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "bic %[nzcv],#0x30000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rv] "0" (v) \
+                        : "cc"); \
+        }while(0)
+
+#define optflag_addw(v, s, d) do { \
+  __asm__ __volatile__ ("sxth %[rd],%[rd]\n\t" \
+			"sxth %[rs],%[rs]\n\t" \
+                        "adds %[rd],%[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_addb(v, s, d) do { \
+  __asm__ __volatile__ ("sxtb %[rd],%[rd]\n\t" \
+			"sxtb %[rs],%[rs]\n\t" \
+                        "adds %[rd],%[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_subw(v, s, d) do { \
+  __asm__ __volatile__ ("sxth %[rd],%[rd]\n\t" \
+			"sxth %[rs],%[rs]\n\t" \
+                        "subs %[rd],%[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_subb(v, s, d) do { \
+  __asm__ __volatile__ ("sxtb %[rd],%[rd]\n\t" \
+			"sxtb %[rs],%[rs]\n\t" \
+                        "subs %[rd],%[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_cmpw(s, d) do { \
+  __asm__ __volatile__ ("sxth %[rd],%[rd]\n\t" \
+			"sxth %[rs],%[rs]\n\t" \
+                        "cmp %[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rs] "ri" (s), [rd] "0" (d) \
+                        : "cc"); \
+  } while(0)
+
+#define optflag_cmpb(s, d) do { \
+  __asm__ __volatile__ ("sxtb %[rd],%[rd]\n\t" \
+			"sxtb %[rs],%[rs]\n\t" \
+                        "cmp %[rd],%[rs]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rs] "ri" (s), [rd] "0" (d) \
+                        : "cc"); \
+  } while(0)
+
+#else
+
+// #pragma message "ARM/generic Assembly optimized flags"
+
+#define optflag_testw(v) do { \
+  __asm__ __volatile__ ("lsl %[rv],%[rv],#16\n\t" \
+                        "tst %[rv],%[rv]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "bic %[nzcv],#0x30000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rv] "0" (v) \
+                        : "cc"); \
+	}while(0)
+
+#define optflag_testb(v) do {\
+  __asm__ __volatile__ ("lsl %[rv],%[rv],#24\n\t" \
+                        "tst %[rv],%[rv]\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "bic %[nzcv],#0x30000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rv] "0" (v) \
+                        : "cc"); \
+	}while(0)
+
+#define optflag_addw(v, s, d) do { \
+  __asm__ __volatile__ ("lsl %[rd],%[rd],#16\n\t" \
+                        "adds %[rd],%[rd],%[rs],lsl #16\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "lsr %[rv],%[rd],#16\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_addb(v, s, d) do { \
+  __asm__ __volatile__ ("lsl %[rd],%[rd],#24\n\t" \
+                        "adds %[rd],%[rd],%[rs],lsl #24\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "lsr %[rv],%[rd],#24\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_subw(v, s, d) do { \
+  __asm__ __volatile__ ("lsl %[rd],%[rd],#16\n\t" \
+                        "subs %[rd],%[rd],%[rs],lsl #16\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        "lsr %[rv],%[rd],#16\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_subb(v, s, d) do { \
+  __asm__ __volatile__ ("lsl %[rd],%[rd],#24\n\t" \
+                        "subs %[rd],%[rd],%[rs],lsl #24\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        "lsr %[rv],%[rd],#24\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv), [rv] "=r" (v) \
+                        : [rs] "ri" (s), [rd] "1" (d) \
+                        : "cc"); \
+    COPY_CARRY(); \
+    } while(0)
+
+#define optflag_cmpw(s, d) do { \
+  __asm__ __volatile__ ("lsl %[rd],%[rd],#16\n\t" \
+                        "cmp %[rd],%[rs],lsl #16\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rs] "ri" (s), [rd] "0" (d) \
+                        : "cc"); \
+  } while(0)
+
+#define optflag_cmpb(s, d) do { \
+  __asm__ __volatile__ ("lsl %[rd],%[rd],#24\n\t" \
+                        "cmp %[rd],%[rs],lsl #24\n\t" \
+                        "mrs %[nzcv],cpsr\n\t" \
+                        "eor %[nzcv],#0x20000000\n\t" \
+                        : [nzcv] "=r" (regflags.nzcv) \
+                        : [rs] "ri" (s), [rd] "0" (d) \
+                        : "cc"); \
+  } while(0)
+
 #endif
 
-#elif defined(SPARC_V8_ASSEMBLY) || defined(SPARC_V9_ASSEMBLY)
+#elif defined(CPU_sparc) && (defined(SPARC_V8_ASSEMBLY) || defined(SPARC_V9_ASSEMBLY))
 
+/*
+ * Machine dependent structure for holding the 68k CCR flags
+ */
 struct flag_struct {
     unsigned char nzvc;
     unsigned char x;
@@ -361,52 +736,62 @@ struct flag_struct {
 
 extern struct flag_struct regflags;
 
-#define FLAGVAL_Z	0x04
+#define FLAGBIT_N   3
-#define FLAGVAL_N	0x08
+#define FLAGBIT_Z   2
+#define FLAGBIT_V   1
+#define FLAGBIT_C   0
+#define FLAGBIT_X   FLAGBIT_C /* should be in the same position as the x flag */
 
-#define SET_ZFLG(y)	(regflags.nzvc = (regflags.nzvc & ~0x04) | (((y) & 1) << 2))
+#define FLAGVAL_N   (1 << FLAGBIT_N)
-#define SET_CFLG(y)	(regflags.nzvc = (regflags.nzvc & ~1) | ((y) & 1))
+#define FLAGVAL_Z   (1 << FLAGBIT_Z)
-#define SET_VFLG(y)	(regflags.nzvc = (regflags.nzvc & ~0x02) | (((y) & 1) << 1))
+#define FLAGVAL_C   (1 << FLAGBIT_C)
-#define SET_NFLG(y)	(regflags.nzvc = (regflags.nzvc & ~0x08) | (((y) & 1) << 3))
+#define FLAGVAL_V   (1 << FLAGBIT_V)
-#define SET_XFLG(y)	(regflags.x = (y))
+#define FLAGVAL_X   (1 << FLAGBIT_X)
 
-#define GET_ZFLG	((regflags.nzvc >> 2) & 1)
+#define SET_ZFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_Z) | (((y) & 1) << FLAGBIT_Z))
-#define GET_CFLG	(regflags.nzvc & 1)
+#define SET_CFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_C) | (((y) & 1) << FLAGBIT_C))
-#define GET_VFLG	((regflags.nzvc >> 1) & 1)
+#define SET_VFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_V))
-#define GET_NFLG	((regflags.nzvc >> 3) & 1)
+#define SET_NFLG(y) (regflags.nzvc = (regflags.nzvc & ~FLAGVAL_V) | (((y) & 1) << FLAGBIT_N))
-#define GET_XFLG	(regflags.x & 1)
+#define SET_XFLG(y) (regflags.x = ((y) & 1) << FLAGBIT_X)
 
-#define CLEAR_CZNV 	(regflags.nzvc = 0)
+#define GET_ZFLG()	((regflags.nzvc >> FLAGBIT_Z) & 1)
-#define GET_CZNV	(reflags.nzvc)
+#define GET_CFLG()	((regflags.nzvc >> FLAGBIT_C) & 1)
-#define IOR_CZNV(X)	(refglags.nzvc |= (X))
+#define GET_VFLG()	((regflags.nzvc >> FLAGBIT_V) & 1)
-#define SET_CZNV(X)	(regflags.nzvc = (X))
+#define GET_NFLG()	((regflags.nzvc >> FLAGBIT_N) & 1)
+#define GET_XFLG()	((regflags.x    >> FLAGBIT_X) & 1)
 
-#define COPY_CARRY (regflags.x = regflags.nzvc)
+#define CLEAR_CZNV() 	(regflags.nzvc = 0)
+#define GET_CZNV()		(regflags.nzvc)
+#define IOR_CZNV(X)		(regflags.nzvc |= (X))
+#define SET_CZNV(X)		(regflags.nzvc = (X))
 
-static __inline__ int cctrue(int cc)
+#define COPY_CARRY()	(regflags.x = regflags.nzvc >> (FLAGBIT_C - FLAGBIT_X))
+
+/*
+ * Test CCR condition
+ */
+static inline int cctrue(int cc)
 {
     uae_u32 nzvc = regflags.nzvc;
-    switch(cc){
+    switch (cc) {
-     case 0: return 1;                       /* T */
+    case 0:  return 1;                              /*              T  */
-     case 1: return 0;                       /* F */
+    case 1:  return 0;                              /*              F  */
-     case 2: return (nzvc & 0x05) == 0; /* !GET_CFLG && !GET_ZFLG;  HI */
+    case 2:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) == 0;              /* !CFLG && !ZFLG       HI */
-     case 3: return (nzvc & 0x05) != 0; /* GET_CFLG || GET_ZFLG;    LS */
+    case 3:  return (cznv & (FLAGVAL_C | FLAGVAL_Z)) != 0;              /*  CFLG || ZFLG        LS */
-     case 4: return (nzvc & 1) == 0;        /* !GET_CFLG;               CC */
+    case 4:  return (cznv & FLAGVAL_C) == 0;                    /* !CFLG            CC */
-     case 5: return (nzvc & 1) != 0;           /* GET_CFLG;                CS */
+    case 5:  return (cznv & FLAGVAL_C) != 0;                    /*  CFLG            CS */
-     case 6: return (nzvc & 0x04) == 0; /* !GET_ZFLG;               NE */
+    case 6:  return (cznv & FLAGVAL_Z) == 0;                    /* !ZFLG            NE */
-     case 7: return (nzvc & 0x04) != 0; /* GET_ZFLG;                EQ */
+    case 7:  return (cznv & FLAGVAL_Z) != 0;                    /*  ZFLG            EQ */
-     case 8: return (nzvc & 0x02) == 0;/* !GET_VFLG;               VC */
+    case 8:  return (cznv & FLAGVAL_V) == 0;                    /* !VFLG            VC */
-     case 9: return (nzvc & 0x02) != 0;/* GET_VFLG;                VS */
+    case 9:  return (cznv & FLAGVAL_V) != 0;                    /*  VFLG            VS */
-     case 10:return (nzvc & 0x08) == 0; /* !GET_NFLG;               PL */
+    case 10: return (cznv & FLAGVAL_N) == 0;                    /* !NFLG            PL */
-     case 11:return (nzvc & 0x08) != 0; /* GET_NFLG;                MI */
+    case 11: return (cznv & FLAGVAL_N) != 0;                    /*  NFLG            MI */
-     case 12:return (((nzvc << 2) ^ nzvc) & 0x08) == 0; /* GET_NFLG == GET_VFLG;             GE */
+    case 12: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) == 0;  /*  NFLG == VFLG        GE */
-     case 13:return (((nzvc << 2) ^ nzvc) & 0x08) != 0;/* GET_NFLG != GET_VFLG;             LT */
+    case 13: return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & FLAGVAL_N) != 0;  /*  NFLG != VFLG        LT */
-     case 14:
+    case 14: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* ZFLG && (NFLG == VFLG)   GT */
-	nzvc &= 0x0e;
+         return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) == 0;
-	return (((nzvc << 2) ^ nzvc) & 0x0c) == 0; /* !GET_ZFLG && (GET_NFLG == GET_VFLG);  GT */
+    case 15: cznv &= (FLAGVAL_N | FLAGVAL_Z | FLAGVAL_V);               /* ZFLG && (NFLG != VFLG)   LE */
-     case 15:
+         return (((cznv << (FLAGBIT_N - FLAGBIT_V)) ^ cznv) & (FLAGVAL_N | FLAGVAL_Z)) != 0;
-	nzvc &= 0x0e;
-	return (((nzvc << 2) ^ nzvc) & 0x0c) != 0; /* GET_ZFLG || (GET_NFLG != GET_VFLG);   LE */
     }
     return 0;
 }
@@ -1008,6 +1393,9 @@ static inline uae_u32 sparc_v9_flag_addx_32(flag_struct *flags, uae_u32 src, uae
 
 #else
 
+/*
+ * Machine independent structure for holding the 68k CCR flags
+ */
 struct flag_struct {
     unsigned int c;
     unsigned int z;
@@ -1030,22 +1418,25 @@ extern struct flag_struct regflags;
 #define SET_ZFLG(x) (ZFLG = (x))
 #define SET_XFLG(x) (XFLG = (x))
 
-#define GET_CFLG CFLG
+#define GET_CFLG() CFLG
-#define GET_NFLG NFLG
+#define GET_NFLG() NFLG
-#define GET_VFLG VFLG
+#define GET_VFLG() VFLG
-#define GET_ZFLG ZFLG
+#define GET_ZFLG() ZFLG
-#define GET_XFLG XFLG
+#define GET_XFLG() XFLG
 
-#define CLEAR_CZNV do { \
+#define CLEAR_CZNV() do { \
  SET_CFLG (0); \
  SET_ZFLG (0); \
  SET_NFLG (0); \
  SET_VFLG (0); \
 } while (0)
 
-#define COPY_CARRY (SET_XFLG (GET_CFLG))
+#define COPY_CARRY() (SET_XFLG (GET_CFLG ()))
 
-static __inline__ int cctrue(const int cc)
+/*
+ * Test CCR condition
+ */
+static inline int cctrue(const int cc)
 {
     switch(cc){
      case 0: return 1;                       /* T */

BasiliskII/src/uae_cpu/newcpu.cpp

@@ -678,8 +678,8 @@ void MakeSR (void)
 #endif
 	regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
 			   | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
-			   | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
+			   | (GET_XFLG() << 4) | (GET_NFLG() << 3) | (GET_ZFLG() << 2) | (GET_VFLG() << 1)
-			   | GET_CFLG);
+			   | GET_CFLG());
 }
 
 void MakeFromSR (void)
@@ -858,7 +858,7 @@ int m68k_move2c (int regno, uae_u32 *regp)
 #if USE_JIT
 			set_cache_state(regs.cacr & 0x8000);
 			if (*regp & 0x08) {	/* Just to be on the safe side */
-				flush_icache(1);
+				flush_icache();
 			}
 #endif
 			break;
@@ -1268,7 +1268,7 @@ void mmu_op(uae_u32 opcode, uae_u16 extra)
 		/* PFLUSH */
 		mmusr = 0;
 #ifdef USE_JIT
-		flush_icache(0);
+		flush_icache();
 #endif
 	} else if ((opcode & 0x0FD8) == 0x548) {
 		/* PTEST */
@@ -1501,7 +1501,7 @@ void m68k_dumpstate (uaecptr *nextpc)
 			regs.usp,regs.isp,regs.msp,regs.vbr);
 	printf ("T=%d%d S=%d M=%d X=%ld N=%ld Z=%ld V=%ld C=%ld IMASK=%d\n",
 			regs.t1, regs.t0, regs.s, regs.m,
-			GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
+			GET_XFLG(), GET_NFLG(), GET_ZFLG(), GET_VFLG(), GET_CFLG(), regs.intmask);
 
 	fpu_dump_registers();
 	fpu_dump_flags();

BasiliskII/src/uae_cpu/noflags.h

@@ -62,13 +62,13 @@ static __inline__ void SET_CFLG_ALWAYS(uae_u32 x)
 #define SET_XFLG(y) do {uae_u32 dummy=(y); } while (0)
 
 #undef CLEAR_CZNV
-#define CLEAR_CZNV
+#define CLEAR_CZNV() do {} while (0)
 #undef IOR_CZNV
 #define IOR_CZNV(y) do {uae_u32 dummy=(y); } while (0)
 #undef SET_CZNV
 #define SET_CZNV(y) do {uae_u32 dummy=(y); } while (0)
 #undef COPY_CARRY
-#define COPY_CARRY 
+#define COPY_CARRY() do {} while (0)
 
 #ifdef  optflag_testl
 #undef  optflag_testl