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Add gen_spcflags_{init,set,clear} + load/store of GPRs to T2.

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This commit is contained in:
gbeauche 2004-01-24 11:20:33 +00:00
parent 6a4463b8fb
commit 48d844a40a
3 changed files with 27 additions and 1 deletions
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20
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen-ops.cpp
View File

@ -36,6 +36,7 @@ register struct powerpc_cpu *CPU asm(REG_CPU);
register uint32 A0 asm(REG_A0); register uint32 A0 asm(REG_A0);
register uint32 T0 asm(REG_T0); register uint32 T0 asm(REG_T0);
register uint32 T1 asm(REG_T1); register uint32 T1 asm(REG_T1);
register uint32 T2 asm(REG_T2);
// Semantic action templates // Semantic action templates
#define DYNGEN_OPS #define DYNGEN_OPS
@ -61,6 +62,7 @@ struct powerpc_dyngen_helper {
static inline void record(int crf, int32 v) { CPU->record_cr(crf, v); } static inline void record(int crf, int32 v) { CPU->record_cr(crf, v); }
static inline powerpc_cr_register & cr() { return CPU->cr(); } static inline powerpc_cr_register & cr() { return CPU->cr(); }
static inline powerpc_xer_register & xer() { return CPU->xer(); } static inline powerpc_xer_register & xer() { return CPU->xer(); }
static inline powerpc_spcflags & spcflags() { return CPU->spcflags(); }
}; };
@ -80,7 +82,8 @@ void OPPROTO op_store_##REG##_GPR##N(void) \
#define DEFINE_REG(N) \ #define DEFINE_REG(N) \
DEFINE_OP(A0,N); \ DEFINE_OP(A0,N); \
DEFINE_OP(T0,N); \ DEFINE_OP(T0,N); \
DEFINE_OP(T1,N); DEFINE_OP(T1,N); \
DEFINE_OP(T2,N);
DEFINE_REG(0); DEFINE_REG(0);
DEFINE_REG(1); DEFINE_REG(1);
@ -298,6 +301,21 @@ void OPPROTO op_load_A0_LR(void)
A0 = powerpc_dyngen_helper::get_lr() & -4; A0 = powerpc_dyngen_helper::get_lr() & -4;
} }
void OPPROTO op_spcflags_init(void)
{
powerpc_dyngen_helper::spcflags().set(PARAM1);
}
void OPPROTO op_spcflags_set(void)
{
powerpc_dyngen_helper::spcflags().set(PARAM1);
}
void OPPROTO op_spcflags_clear(void)
{
powerpc_dyngen_helper::spcflags().clear(PARAM1);
}
/** /**
* Branch instructions * Branch instructions

2
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.cpp
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@ -113,9 +113,11 @@ void powerpc_dyngen::gen_##OP##_##REG##_##REGT(int i) \
DEFINE_INSN(load, A0, GPR); DEFINE_INSN(load, A0, GPR);
DEFINE_INSN(load, T0, GPR); DEFINE_INSN(load, T0, GPR);
DEFINE_INSN(load, T1, GPR); DEFINE_INSN(load, T1, GPR);
DEFINE_INSN(load, T2, GPR);
DEFINE_INSN(store, A0, GPR); DEFINE_INSN(store, A0, GPR);
DEFINE_INSN(store, T0, GPR); DEFINE_INSN(store, T0, GPR);
DEFINE_INSN(store, T1, GPR); DEFINE_INSN(store, T1, GPR);
DEFINE_INSN(store, T2, GPR);
// Condition register bitfield // Condition register bitfield
DEFINE_INSN(load, T0, crb); DEFINE_INSN(load, T0, crb);

6
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-dyngen.hpp
View File

@ -51,9 +51,11 @@ public:
void gen_load_A0_GPR(int i); void gen_load_A0_GPR(int i);
void gen_load_T0_GPR(int i); void gen_load_T0_GPR(int i);
void gen_load_T1_GPR(int i); void gen_load_T1_GPR(int i);
void gen_load_T2_GPR(int i);
void gen_store_A0_GPR(int i); void gen_store_A0_GPR(int i);
void gen_store_T0_GPR(int i); void gen_store_T0_GPR(int i);
void gen_store_T1_GPR(int i); void gen_store_T1_GPR(int i);
void gen_store_T2_GPR(int i);
// Raw aliases // Raw aliases
#define DEFINE_ALIAS_RAW(NAME, PRE, POST, ARGLIST, ARGS) \ #define DEFINE_ALIAS_RAW(NAME, PRE, POST, ARGLIST, ARGS) \
@ -102,6 +104,10 @@ public:
DEFINE_ALIAS(load_A0_LR,0); DEFINE_ALIAS(load_A0_LR,0);
DEFINE_ALIAS(store_im_LR,1); DEFINE_ALIAS(store_im_LR,1);
DEFINE_ALIAS(spcflags_init,1);
DEFINE_ALIAS(spcflags_set,1);
DEFINE_ALIAS(spcflags_clear,1);
// Control Flow // Control Flow
DEFINE_ALIAS(decrement_ctr_T0,0); DEFINE_ALIAS(decrement_ctr_T0,0);
DEFINE_ALIAS(branch_A0_if_T0,1); DEFINE_ALIAS(branch_A0_if_T0,1);