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https://github.com/kanjitalk755/macemu.git
synced 2024-07-05 09:28:57 +00:00
- merge 680x0 emulation core with uae 0.8.17
This commit is contained in:
gbeauche
parent
bcc6b4b0ac
commit
f93d1b483d
@ -910,22 +910,20 @@ static void gen_opcode (unsigned long int opcode)
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genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
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break;
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case i_SBCD:
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/* Let's hope this works... */
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genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
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genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
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start_brace ();
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printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
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printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
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printf ("\tuae_u16 newv;\n");
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printf ("\tint cflg;\n");
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printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
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printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
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printf ("\tcflg = (newv_hi & 0x1F0) > 0x90;\n");
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printf ("\tSET_CFLG (cflg);\n");
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printf ("\tuae_u16 newv, tmp_newv;\n");
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printf ("\tint bcd = 0;\n");
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printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
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printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
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printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
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printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
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duplicate_carry ();
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printf ("\tif (cflg) newv -= 0x60;\n");
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genflags (flag_zn, curi->size, "newv", "", "");
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genflags (flag_sv, curi->size, "newv", "src", "dst");
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printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
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genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
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break;
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case i_ADD:
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@ -957,16 +955,16 @@ static void gen_opcode (unsigned long int opcode)
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start_brace ();
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printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
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printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
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printf ("\tuae_u16 newv;\n");
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printf ("\tuae_u16 newv, tmp_newv;\n");
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printf ("\tint cflg;\n");
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printf ("\tif (newv_lo > 9) { newv_lo +=6; }\n");
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printf ("\tnewv = newv_hi + newv_lo;");
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printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
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printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
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printf ("\tif (newv_lo > 9) { newv += 6; }\n");
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printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
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printf ("\tif (cflg) newv += 0x60;\n");
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printf ("\tSET_CFLG (cflg);\n");
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duplicate_carry ();
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printf ("\tif (cflg) newv += 0x60;\n");
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genflags (flag_zn, curi->size, "newv", "", "");
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genflags (flag_sv, curi->size, "newv", "src", "dst");
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printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
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genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
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break;
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case i_NEG:
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@ -990,12 +988,12 @@ static void gen_opcode (unsigned long int opcode)
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printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
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printf ("\tuae_u16 newv;\n");
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printf ("\tint cflg;\n");
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printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
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printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
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printf ("\tcflg = cflg = (newv_hi & 0x1F0) > 0x90;\n");
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printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
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printf ("\tnewv = newv_hi + newv_lo;");
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printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
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printf ("\tif (cflg) newv -= 0x60;\n");
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printf ("\tSET_CFLG (cflg);\n");
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duplicate_carry();
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printf ("\tif (cflg) newv -= 0x60;\n");
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genflags (flag_zn, curi->size, "newv", "", "");
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genastore ("newv", curi->smode, "srcreg", curi->size, "src");
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break;
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@ -339,7 +339,6 @@ static void build_insn (int insn)
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case 'A':
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srcmode = Areg;
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switch (opcstr[pos++]) {
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case 'l': srcmode = absl; break;
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case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break;
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case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break;
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default: abort();
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@ -349,6 +348,9 @@ static void build_insn (int insn)
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case 'P': srcmode = Aipi; pos++; break;
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}
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break;
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case 'L':
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srcmode = absl;
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break;
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case '#':
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switch (opcstr[pos++]) {
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case 'z': srcmode = imm; break;
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@ -395,7 +397,7 @@ static void build_insn (int insn)
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}
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break;
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case 'p': srcmode = immi; srcreg = bitval[bitp];
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if (CPU_EMU_SIZE < 5) { // gb-- what is CPU_EMU_SIZE used for ??
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if (CPU_EMU_SIZE < 5) {
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/* 0..3 */
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srcgather = 1;
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srctype = 7;
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@ -526,20 +528,27 @@ static void build_insn (int insn)
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case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
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default: abort();
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}
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if (dstpos < 0 || dstpos >= 32)
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abort();
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break;
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case 'A':
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destmode = Areg;
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switch (opcstr[pos++]) {
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case 'l': destmode = absl; break;
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case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break;
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case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break;
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case 'x': destreg = 0; dstgather = 0; dstpos = 0; break;
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default: abort();
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}
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if (dstpos < 0 || dstpos >= 32)
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abort();
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switch (opcstr[pos]) {
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case 'p': destmode = Apdi; pos++; break;
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case 'P': destmode = Aipi; pos++; break;
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}
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break;
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case 'L':
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destmode = absl;
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break;
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case '#':
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switch (opcstr[pos++]) {
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case 'z': destmode = imm; break;
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@ -25,7 +25,7 @@
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%
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% Arp: --> -(Ar)
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% ArP: --> (Ar)+
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% Al : --> (xxx).L
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% L: (xxx).L
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%
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% Fields on a line:
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% 16 chars bitpattern :
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@ -146,18 +146,14 @@
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0100 1110 11ss sSSS:00://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd]
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0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
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% This variant of ADDQ is word and long sized only
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0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W #j,d[Areg]
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0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L #j,d[Areg]
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0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z #j,d[!Areg]
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% This variant of SUBQ is word and long sized only
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0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W #j,d[Areg]
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0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L #j,d[Areg]
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0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z #j,d[!Areg]
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0101 cccc 1100 1rrr:00:-----:+++++:31: DBcc.W Dr,#1
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0101 cccc 11dd dDDD:00:-----:+++++:20: Scc.B d[!Areg]
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0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W Dr,#1
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0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B d[!Areg]
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0101 cccc 1111 1010:20:?????:?????:10: TRAPcc #1
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0101 cccc 1111 1011:20:?????:?????:10: TRAPcc #2
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0101 cccc 1111 1100:20:?????:?????:00: TRAPcc
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@ -168,9 +164,9 @@
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0110 0001 0000 0000:00://///://///:40: BSR.W #1
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0110 0001 IIII IIII:00://///://///:40: BSR.B #i
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0110 0001 1111 1111:00://///://///:40: BSR.L #2
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0110 CCCC 0000 0000:00:-----:+++++:40: Bcc.W #1
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0110 CCCC IIII IIII:00:-----:+++++:40: Bcc.B #i
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0110 CCCC 1111 1111:00:-----:+++++:40: Bcc.L #2
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0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W #1
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0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B #i
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0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L #2
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0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L #i,Dr
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@ -256,8 +252,9 @@
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1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar
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1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar
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1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p
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1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,ARP
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1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],Al
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1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Areg-Aipi]
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1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],Al
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1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 Al,d[Aipi-Aind]
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% destination register number is encoded in the following word
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1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,AxP
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1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],L
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1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Areg-Aipi]
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1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],L
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1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Aipi-Aind]
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