Commit Graph

14 Commits

Author SHA1 Message Date
kanjitalk755
5862662bc9 fix for Linux and Windows 2021-05-06 12:16:03 +09:00
kanjitalk755
e42b8f6076 rename new uae_cpu 2021-05-06 11:38:37 +09:00
uyjulian
03fc337242
uae_cpu is based upon ARAnyM sources 2019-09-02 14:40:01 -05:00
uyjulian
77e20bda2a
Back to BasiliskII uae_cpu but with ARAnyM JIT 2018-04-22 20:39:37 -05:00
uyjulian
1758ef58b5
Port of CPU code from ARAnyM (currently hangs) 2018-04-15 20:23:12 -05:00
uyjulian
1bf6e93461
Downgraded emulated UAE cpu 2018-04-15 17:33:50 -05:00
James Touton
8b4dc6ea81 gencpu builds cleanly on MSVC.
Fixed nasty bitfield issue where MSVC enums are signed, so a two-bit bitfield set to 2 is later read as -2.
2015-08-06 01:25:15 -07:00
gbeauche
b3f62598b7 More human readable instruction names (from e-uae). 2007-06-29 16:32:05 +00:00
nigel
21c4e9da5b Building on GCC 2 causes errors:
../uae_cpu/gencpu.c: In function `void gen_opcode(long unsigned int)':
../uae_cpu/gencpu.c:874: conversion from `unsigned int' to `enum wordsizes'
../uae_cpu/gencpu.c:875: conversion from `unsigned int' to `enum amodes'
due to mismatching of types in struct instr and types in function prototypes.
However, this only started happening recently and I don't know why :-(
2003-04-01 05:26:07 +00:00
gbeauche
94a9038826 - Remove dead code in readcpu.cpp concerning CONST_JUMP control flow.
- Replace unused fl_compiled with fl_const_jump
- Implement block inlining enabled with USE_INLINING && USE_CHECKSUM_INFO.
  However, this is currently disabled as it doesn't give much and exhibits
  even more a cache/code generation problem with FPU JIT compiled code.
- Actual checksum values are now integral part of a blockinfo regardless
  of USE_CHECKSUM_INFO is set or not. Reduce number of elements in that
  structure and speeds up a little calculation of checksum of chained blocks.
- Don't care about show_checksum() for now.
2002-10-02 15:55:10 +00:00
gbeauche
7972082c56 - Merge with Basilisk II/JIT cpu core, interpretive part for now
- Clean use of USE_PREFETCH_BUFFER macro and dependent bits
2002-09-01 15:17:13 +00:00
gbeauche
7535a1042f Additions:
- MOVE16 (Ay)+,(xxx).L
- MOVE16 (xxx).L,(Ay)+
- MOVE16 (Ay),(xxx).L
- MOVE16 (xxx).L,(Ay)

Fixes:
- MOVE16 (Ax)+,(Ay)+ where x == y: address register shall be incremented
  only once
- CINV, CPUSH: 'p' field matches correctly the instruction 'cache field'
2001-03-19 13:11:40 +00:00
cebix
c31d1bd2af - added some 68040 instructions: CINV, CPUSH, MOVE16 (Ax)+,(Ay)+, MOVEC regs,
and FPU state frames; enough to boot MacOS
- CPU type can be selected in GTK prefs editor
1999-10-28 15:33:26 +00:00
cebix
8e491572ca Imported sources 1999-10-03 14:16:26 +00:00