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moa/emulator/cpus/m68k/tests/execute_tests.rs

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Split clocks into `femtos` crate
2024-02-24 21:02:09 +00:00
use femtos::{Instant, Frequency};
Fixed some tests
2024-03-16 06:01:41 +00:00
use emulator_hal::bus::BusAccess;
use emulator_hal::step::Step;
use emulator_hal_memory::MemoryBlock;
Split clocks into `femtos` crate
2024-02-24 21:02:09 +00:00
Fixed some tests
2024-03-16 06:01:41 +00:00
use moa_m68k::{M68k, M68kType, M68kAddress};
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
use moa_m68k::state::M68kState;
Refactored to separate out the BusPort, to eventually replace it
2024-03-04 06:57:27 +00:00
use moa_m68k::execute::{M68kCycle, M68kCycleExecutor};
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
use moa_m68k::instructions::{Instruction, Target, Size, Sign, Direction, Condition};
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
Fixed some tests
2024-03-16 06:01:41 +00:00
const INIT_STACK: M68kAddress = 0x00002000;
const INIT_ADDR: M68kAddress = 0x00000010;
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
const MEM_ADDR: u32 = 0x00001234;
struct TestState {
pc: u32,
ssp: u32,
usp: u32,
d0: u32,
d1: u32,
a0: u32,
a1: u32,
sr: u16,
mem: u32,
}
struct TestCase {
name: &'static str,
ins: Instruction,
data: &'static [u16],
cputype: M68kType,
init: TestState,
fini: TestState,
}
Fixed some tests
2024-03-16 06:01:41 +00:00
#[allow(clippy::uninit_vec)]
Refactoring m68k to use a temporary cycle struct I'm trying to extract the memory/bus interface, and pass it in at the start of each cycle instead of having the BusPort permanently embedded, which will allow migrating to emulator-hal. The functional way would be argument drilling; passing an extra argument to each function in the entire execution core. The problem is that it's messy, so a solution that is still functional is to implement all of the execution logic on a newtype that contains a reference to the mutable state and the owned cycle data, and at the end of the cycle, decompose the M68kCycleGuard that holds the reference, and keep the cycle data for debugging purposes.
2024-03-03 07:48:19 +00:00
fn run_execute_test<F>(cputype: M68kType, mut test_func: F)
where
Implemented Inspect and Debug traits from emulator-hal (#5) * Implemented Inspect and Debug traits from emulator-hal * Updated emulator-hal submodule * Updated Cargo.lock * Fixed missing feature flag and clippy * Fixed tests
2024-03-21 04:00:33 +00:00
F: FnMut(M68kCycleExecutor<&mut MemoryBlock<u32, Instant>, Instant>),
Refactoring m68k to use a temporary cycle struct I'm trying to extract the memory/bus interface, and pass it in at the start of each cycle instead of having the BusPort permanently embedded, which will allow migrating to emulator-hal. The functional way would be argument drilling; passing an extra argument to each function in the entire execution core. The problem is that it's messy, so a solution that is still functional is to implement all of the execution logic on a newtype that contains a reference to the mutable state and the owned cycle data, and at the end of the cycle, decompose the M68kCycleGuard that holds the reference, and keep the cycle data for debugging purposes.
2024-03-03 07:48:19 +00:00
{
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
// Insert basic initialization
Fixed some tests
2024-03-16 06:01:41 +00:00
let len = 0x10_0000;
let mut data = Vec::with_capacity(len);
Added github actions for PRs (#3) * Added github actions for PRs * Added some rustfmt::skip attributes * Applied formatting * Added rustfmt component in action * Configured to use rustfmt version 2 which fixes some comment formatting * Removed ready_for_review condition for github actions Since it has the synchronize condition, it will update after each commit, whether in draft or not, so I think this should be alright
2024-03-17 18:03:52 +00:00
unsafe {
data.set_len(len);
}
Fixed some tests
2024-03-16 06:01:41 +00:00
let mut memory = MemoryBlock::from(data);
memory.write_beu32(Instant::START, 0, INIT_STACK).unwrap();
memory.write_beu32(Instant::START, 4, INIT_ADDR).unwrap();
let mut cpu = M68k::from_type(cputype, Frequency::from_mhz(10));
cpu.step(Instant::START, &mut memory).unwrap();
let cycle = M68kCycle::new(&cpu, Instant::START);
let executor = cycle.begin(&mut cpu, &mut memory);
assert_eq!(executor.state.pc, INIT_ADDR);
assert_eq!(executor.state.ssp, INIT_STACK);
Fixed m68k tests after refactor
2024-03-03 21:26:15 +00:00
assert_eq!(executor.cycle.decoder.instruction, Instruction::NOP);
Fixed some tests
2024-03-16 06:01:41 +00:00
test_func(executor)
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
}
fn build_state(state: &TestState) -> M68kState {
let mut new_state = M68kState::default();
new_state.pc = state.pc;
new_state.ssp = state.ssp;
new_state.usp = state.usp;
new_state.d_reg[0] = state.d0;
new_state.d_reg[1] = state.d1;
new_state.a_reg[0] = state.a0;
new_state.a_reg[1] = state.a1;
new_state.sr = state.sr;
new_state
}
Modified for Instant as associated type in emulator-hal (#6) * Modified for Instant as associated type in emulator-hal * Updated emulator-hal to latest
2024-03-23 01:51:17 +00:00
fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(bus: &mut Bus, data: &[u16]) {
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
for i in 0..data.len() {
bus.write_beu16(Instant::START, (i << 1) as u32, data[i]).unwrap();
Added github actions for PRs (#3) * Added github actions for PRs * Added some rustfmt::skip attributes * Applied formatting * Added rustfmt component in action * Configured to use rustfmt version 2 which fixes some comment formatting * Removed ready_for_review condition for github actions Since it has the synchronize condition, it will update after each commit, whether in draft or not, so I think this should be alright
2024-03-17 18:03:52 +00:00
}
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
}
fn run_test(case: &TestCase) {
Fixed some tests
2024-03-16 06:01:41 +00:00
run_execute_test(case.cputype, |mut executor| {
Refactoring m68k to use a temporary cycle struct I'm trying to extract the memory/bus interface, and pass it in at the start of each cycle instead of having the BusPort permanently embedded, which will allow migrating to emulator-hal. The functional way would be argument drilling; passing an extra argument to each function in the entire execution core. The problem is that it's messy, so a solution that is still functional is to implement all of the execution logic on a newtype that contains a reference to the mutable state and the owned cycle data, and at the end of the cycle, decompose the M68kCycleGuard that holds the reference, and keep the cycle data for debugging purposes.
2024-03-03 07:48:19 +00:00
let init_state = build_state(&case.init);
let expected_state = build_state(&case.fini);
Fixed some tests
2024-03-16 06:01:41 +00:00
executor.bus.write_beu32(Instant::START, MEM_ADDR, case.init.mem).unwrap();
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
Fixed some tests
2024-03-16 06:01:41 +00:00
load_memory(&mut executor.bus, case.data);
Fixed m68k tests after refactor
2024-03-03 21:26:15 +00:00
*executor.state = init_state;
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
Fixed m68k tests after refactor
2024-03-03 21:26:15 +00:00
executor.decode_next().unwrap();
assert_eq!(executor.cycle.decoder.instruction, case.ins);
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
Fixed m68k tests after refactor
2024-03-03 21:26:15 +00:00
executor.execute_current().unwrap();
assert_eq!(*executor.state, expected_state);
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
Fixed some tests
2024-03-16 06:01:41 +00:00
let mem = executor.bus.read_beu32(Instant::START, MEM_ADDR).unwrap();
Refactoring m68k to use a temporary cycle struct I'm trying to extract the memory/bus interface, and pass it in at the start of each cycle instead of having the BusPort permanently embedded, which will allow migrating to emulator-hal. The functional way would be argument drilling; passing an extra argument to each function in the entire execution core. The problem is that it's messy, so a solution that is still functional is to implement all of the execution logic on a newtype that contains a reference to the mutable state and the owned cycle data, and at the end of the cycle, decompose the M68kCycleGuard that holds the reference, and keep the cycle data for debugging purposes.
2024-03-03 07:48:19 +00:00
assert_eq!(mem, case.fini.mem);
});
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
}
#[test]
pub fn run_execute_tests() {
for case in TEST_CASES {
println!("Running test {}", case.name);
run_test(case);
}
}
#[test]
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
#[ignore]
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
pub fn run_assembler_tests() {
use moa_m68k::assembler::M68kAssembler;
let mut tests = 0;
let mut errors = 0;
for case in TEST_CASES {
tests += 1;
let assembly_text = format!("{}", case.ins);
print!("Testing assembling of {:?} ", assembly_text);
let mut assembler = M68kAssembler::new(M68kType::MC68000);
match assembler.assemble_words(&assembly_text) {
Ok(data) => {
if data == case.data {
print!("pass");
} else {
errors += 1;
print!("FAILED");
print!("\ngot: [{}], but expected: [{}]", format_hex(&data), format_hex(case.data));
}
println!();
},
Err(err) => {
println!("FAILED\n{:?}", err);
errors += 1;
},
}
}
if errors > 0 {
panic!("{} errors out of {} tests", errors, tests);
}
}
fn format_hex(data: &[u16]) -> String {
data.iter()
.map(|word| format!("{:#06x}", word))
.collect::<Vec<String>>()
.join(", ")
}
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
#[rustfmt::skip]
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
const TEST_CASES: &'static [TestCase] = &[
TestCase {
name: "nop",
ins: Instruction::NOP,
data: &[ 0x4e71 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "addi with no overflow or carry",
ins: Instruction::ADD(Target::Immediate(0x7f), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0600, 0x007F ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007f, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "addi with no overflow but negative",
ins: Instruction::ADD(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0600, 0x0080 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "addi with overflow",
ins: Instruction::ADD(Target::Immediate(0x7f), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0600, 0x007F ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 },
},
TestCase {
name: "addi with carry",
ins: Instruction::ADD(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0600, 0x0080 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2717, mem: 0x00000000 },
},
TestCase {
name: "adda immediate",
ins: Instruction::ADDA(Target::Immediate(0xF800), 0, Size::Word),
data: &[ 0xD0FC, 0xF800 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0xFFFFF800, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
},
TestCase {
name: "adda register",
ins: Instruction::ADDA(Target::DirectDReg(0), 0, Size::Word),
data: &[ 0xD0C0 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000F800, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000F800, d1: 0x00000000, a0: 0xFFFFF800, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
},
TestCase {
name: "addx",
ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0xD101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FE, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 },
},
TestCase {
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
name: "addx with extend; zero flag not set",
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0xD101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 },
},
TestCase {
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
name: "addx with extend; zero flag set",
ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0xD101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2714, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x270A, mem: 0x00000000 },
},
TestCase {
name: "addx with extend and carry; zero flag not set",
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0xD101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 },
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2711, mem: 0x00000000 },
},
TestCase {
name: "addx with extend and carry; zero flag set",
ins: Instruction::ADDX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0xD101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2714, mem: 0x00000000 },
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 },
},
TestCase {
name: "andi with sr",
ins: Instruction::ANDtoSR(0xF8FF),
data: &[ 0x027C, 0xF8FF ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA7AA, mem: 0x00000000 },
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA00A, mem: 0x00000000 },
},
TestCase {
name: "andi with sr 2",
ins: Instruction::ANDtoSR(0xF8FF),
data: &[ 0x027C, 0xF8FF ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA7FA, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA01A, mem: 0x00000000 },
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
},
TestCase {
name: "asl",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ASL(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE300 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "asr",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ASR(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE200 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000C0, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 },
},
TestCase {
name: "blt with jump",
ins: Instruction::Bcc(Condition::LessThan, 8),
data: &[ 0x6D08 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 },
fini: TestState { pc: 0x0000000A, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 },
},
TestCase {
name: "blt with jump",
ins: Instruction::Bcc(Condition::LessThan, 8),
data: &[ 0x6D08 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "bchg not zero",
ins: Instruction::BCHG(Target::Immediate(7), Target::DirectDReg(1), Size::Long),
data: &[ 0x0841, 0x0007 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x000000FF, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "bchg zero",
ins: Instruction::BCHG(Target::Immediate(7), Target::DirectDReg(1), Size::Long),
data: &[ 0x0841, 0x0007 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000080, a0: 0x00000000, a1: 0x00000000, sr: 0x2704, mem: 0x00000000 },
},
TestCase {
name: "bra 8-bit",
ins: Instruction::BRA(-32),
data: &[ 0x60E0 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0xFFFFFFE2, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "cmpi equal",
ins: Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0C00, 0x0020 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2704, mem: 0x00000000 },
},
TestCase {
name: "cmpi greater than",
ins: Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0C00, 0x0030 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 },
},
TestCase {
name: "cmpi less than",
ins: Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0C00, 0x0010 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000020, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "cmpi no overflow",
ins: Instruction::CMP(Target::Immediate(0x7F), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0C00, 0x007F ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 },
},
TestCase {
name: "cmpi no overflow, already negative",
ins: Instruction::CMP(Target::Immediate(0x8001), Target::DirectDReg(0), Size::Word),
data: &[ 0x0C40, 0x8001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 },
},
TestCase {
name: "cmpi with overflow",
ins: Instruction::CMP(Target::Immediate(0x80), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0C00, 0x0080 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270B, mem: 0x00000000 },
},
TestCase {
name: "cmpi with overflow 2",
ins: Instruction::CMP(Target::Immediate(0x8001), Target::DirectDReg(0), Size::Word),
data: &[ 0x0C40, 0x8001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x270B, mem: 0x00000000 },
},
TestCase {
name: "cmpi no carry",
ins: Instruction::CMP(Target::Immediate(0x01), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0C00, 0x0001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "cmpi with carry",
ins: Instruction::CMP(Target::Immediate(0xFF), Target::DirectDReg(0), Size::Byte),
data: &[ 0x0C00, 0x00FF ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 },
},
TestCase {
name: "divu",
ins: Instruction::DIVW(Target::Immediate(0x0245), 0, Sign::Unsigned),
data: &[ 0x80FC, 0x0245 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00040000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x007101C3, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "divs",
ins: Instruction::DIVW(Target::Immediate(48), 0, Sign::Signed),
data: &[ 0x81FC, 0x0030 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFEB00, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FF90, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "eori",
ins: Instruction::EOR(Target::DirectDReg(1), Target::DirectDReg(0), Size::Long),
data: &[ 0xB380 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAAAA5555, d1: 0x55AA55AA, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFF0000FF, d1: 0x55AA55AA, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "exg",
ins: Instruction::EXG(Target::DirectDReg(0), Target::DirectAReg(1)),
data: &[ 0xC189 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x12345678, d1: 0x00000000, a0: 0x00000000, a1: 0x87654321, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x87654321, d1: 0x00000000, a0: 0x00000000, a1: 0x12345678, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "ext",
ins: Instruction::EXT(0, Size::Byte, Size::Word),
data: &[ 0x4880 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FFCB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27F8, mem: 0x00000000 },
},
TestCase {
name: "ext",
ins: Instruction::EXT(0, Size::Word, Size::Long),
data: &[ 0x48C0 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000CB, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27F0, mem: 0x00000000 },
},
TestCase {
name: "lsl",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::LSL(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE308 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x271F, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "lsl with bit out",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::LSL(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE308 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000002, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2711, mem: 0x00000000 },
},
TestCase {
name: "lsr",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::LSR(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE208 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000081, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000040, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2711, mem: 0x00000000 },
},
TestCase {
name: "muls",
ins: Instruction::MULW(Target::Immediate(0x0276), 0, Sign::Signed),
data: &[ 0xC1FC, 0x0276 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000200, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0004ec00, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "movel",
ins: Instruction::MOVE(Target::DirectDReg(0), Target::DirectDReg(1), Size::Long),
data: &[ 0x2200 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0xFEDCBA98, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "movea",
ins: Instruction::MOVEA(Target::DirectDReg(0), 0, Size::Long),
data: &[ 0x2040 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0xFEDCBA98, d1: 0x00000000, a0: 0xFEDCBA98, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
},
// MOVEM
TestCase {
name: "movem word to target",
ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Word, Direction::ToTarget, 0x0003),
data: &[ 0x4890, 0x0003 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0xEFEF5678, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0xEFEF5678, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x12345678 },
},
TestCase {
name: "movem long to target",
ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::ToTarget, 0x0001),
data: &[ 0x48D0, 0x0001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 },
},
TestCase {
name: "movem long from target",
ins: Instruction::MOVEM(Target::IndirectAReg(0), Size::Long, Direction::FromTarget, 0x0001),
data: &[ 0x4CD0, 0x0001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 },
},
TestCase {
name: "movem word from target inc",
ins: Instruction::MOVEM(Target::IndirectARegInc(0), Size::Word, Direction::FromTarget, 0x0001),
data: &[ 0x4C98, 0x0001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFFFFF, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xFFFFABCD, d1: 0x00000000, a0: MEM_ADDR+2, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 },
},
TestCase {
name: "movem long to target dec",
ins: Instruction::MOVEM(Target::IndirectARegDec(0), Size::Long, Direction::ToTarget, 0x8000),
data: &[ 0x48E0, 0x8000 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR+4, a1: 0x00000000, sr: 0x27FF, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xABCD1234, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xABCD1234 },
},
// MOVEP
TestCase {
name: "movep word to even memory",
ins: Instruction::MOVEP(0, 0, 0, Size::Word, Direction::ToTarget),
data: &[ 0x0188, 0x0000 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF },
},
TestCase {
name: "movep word to odd memory",
ins: Instruction::MOVEP(0, 0, 1, Size::Word, Direction::ToTarget),
data: &[ 0x0188, 0x0001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA },
},
TestCase {
name: "movep long to even memory upper",
ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::ToTarget),
data: &[ 0x01C8, 0x0000 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF },
},
TestCase {
name: "movep long to even memory lower",
ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::ToTarget),
data: &[ 0x01C8, 0x0000 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xFFFFFFFF },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF },
},
TestCase {
name: "movep word from even memory",
ins: Instruction::MOVEP(0, 0, 0, Size::Word, Direction::FromTarget),
data: &[ 0x0108, 0x0000 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0x55FFAAFF },
},
TestCase {
name: "movep word from odd memory",
ins: Instruction::MOVEP(0, 0, 1, Size::Word, Direction::FromTarget),
data: &[ 0x0108, 0x0001 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x000055AA, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xFF55FFAA },
},
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
// TODO not sure if these cases are correct
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
TestCase {
name: "movep long from even memory upper",
ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::FromTarget),
data: &[ 0x0148, 0x0000 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF },
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0xAABBCCDD, d1: 0x00000000, a0: MEM_ADDR, a1: 0x00000000, sr: 0x27FF, mem: 0xAAFFBBFF },
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
},
TestCase {
name: "movep long from even memory lower",
ins: Instruction::MOVEP(0, 0, 0, Size::Long, Direction::FromTarget),
data: &[ 0x0148, 0x0000 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000CCDD, d1: 0x00000000, a0: MEM_ADDR-4, a1: 0x00000000, sr: 0x27FF, mem: 0xCCFFDDFF },
},
// NEG
TestCase {
name: "neg",
ins: Instruction::NEG(Target::DirectDReg(0), Size::Word),
data: &[ 0x4440 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000FF80, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 },
},
TestCase {
name: "ori",
ins: Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte),
data: &[ 0x0008, 0x00FF ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x000000FF, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "ori with sr",
ins: Instruction::ORtoSR(0x00AA),
data: &[ 0x007C, 0x00AA ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA755, mem: 0x00000000 },
Fixed tests and clippy warnings
2024-03-16 20:15:34 +00:00
fini: TestState { pc: 0x00000004, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0xA71F, mem: 0x00000000 },
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
},
TestCase {
name: "rol",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ROL(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE318 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2701, mem: 0x00000000 },
},
TestCase {
name: "ror",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ROR(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE218 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2709, mem: 0x00000000 },
},
TestCase {
name: "roxl",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ROXL(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE310 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 },
},
TestCase {
name: "roxr",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ROXR(Target::Immediate(1), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE210 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2715, mem: 0x00000000 },
},
TestCase {
name: "roxl two bits",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ROXL(Target::Immediate(2), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE510 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
},
TestCase {
name: "roxr two bits",
Fixed tests and clippy warnings
2023-06-11 00:39:20 +00:00
ins: Instruction::ROXR(Target::Immediate(2), Target::DirectDReg(0), Size::Byte),
Reorganized m68k tests
2023-03-26 04:27:02 +00:00
data: &[ 0xE410 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000001, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x00000000, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "subx",
ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0x9101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2700, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2708, mem: 0x00000000 },
},
TestCase {
name: "subx with extend",
ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0x9101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x000000FF, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x0000007F, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2702, mem: 0x00000000 },
},
TestCase {
name: "subx with extend and carry",
ins: Instruction::SUBX(Target::DirectDReg(1), Target::DirectDReg(0), Size::Byte),
data: &[ 0x9101 ],
cputype: M68kType::MC68010,
init: TestState { pc: 0x00000000, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000000, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2710, mem: 0x00000000 },
fini: TestState { pc: 0x00000002, ssp: 0x00000000, usp: 0x00000000, d0: 0x00000080, d1: 0x0000007F, a0: 0x00000000, a1: 0x00000000, sr: 0x2719, mem: 0x00000000 },
},
];
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