Added Debuggable trait and added tests
This commit is contained in:
transistor
parent
c980c2f56d
commit
1ad7ad1807
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@ -32,7 +32,7 @@ fn main() {
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system.add_addressable_device(0x00700000, wrap_transmutable(serial)).unwrap();
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let mut cpu = M68k::new(M68kType::MC68030);
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let mut cpu = M68k::new(M68kType::MC68030, 8_000_000);
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//cpu.enable_tracing();
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//cpu.add_breakpoint(0x10781a);
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@ -1,7 +1,7 @@
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use crate::error::Error;
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use crate::system::System;
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use crate::devices::{Address, Addressable};
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use crate::devices::{Address, Addressable, Debuggable};
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use super::state::M68k;
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use super::decode::M68kDecoder;
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@ -47,22 +47,22 @@ impl M68kDebugger {
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}
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}
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impl M68k {
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#[allow(dead_code)]
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pub fn enable_tracing(&mut self) {
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self.debugger.use_tracing = true;
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}
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#[allow(dead_code)]
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pub fn enable_debugging(&mut self) {
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impl Debuggable for M68k {
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fn enable_debugging(&mut self) {
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self.debugger.use_tracing = true;
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self.debugger.use_debugger = true;
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}
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#[allow(dead_code)]
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pub fn add_breakpoint(&mut self, addr: Address) {
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fn add_breakpoint(&mut self, addr: Address) {
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self.debugger.breakpoints.push(addr as u32);
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}
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}
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impl M68k {
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#[allow(dead_code)]
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pub fn enable_tracing(&mut self) {
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self.debugger.use_tracing = true;
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}
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pub fn check_breakpoints(&mut self) {
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for breakpoint in &self.debugger.breakpoints {
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@ -88,7 +88,7 @@ impl M68kDecoder {
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let data = self.read_instruction_word(memory)?;
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match optype {
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0b0000 => Ok(Instruction::ORtoCCR(data as u8)),
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0b0001 => Ok(Instruction::ANDtoCCR(data as u8)),
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0b0010 => Ok(Instruction::ANDtoCCR(data as u8)),
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0b1010 => Ok(Instruction::EORtoCCR(data as u8)),
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_ => return Err(Error::processor(Exceptions::IllegalInstruction as u32)),
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}
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@ -423,10 +423,12 @@ impl M68kDecoder {
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match size {
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Some(size) => {
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if (ins & 0b100110000) == 0b100000000 {
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let mode = (ins & 0x08) == 0;
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// TODO implement SUBX
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panic!("Not Implemented");
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let src = get_low_reg(ins);
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let dest = get_high_reg(ins);
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match (ins & 0x08) == 0 {
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true => Ok(Instruction::SUBX(Target::DirectDReg(src), Target::DirectDReg(dest), size)),
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false => Ok(Instruction::SUBX(Target::IndirectARegDec(src), Target::DirectDReg(dest), size)),
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}
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} else {
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let target = self.decode_lower_effective_address(memory, ins, Some(size))?;
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if dir == 0 {
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@ -506,10 +508,12 @@ impl M68kDecoder {
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match size {
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Some(size) => {
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if (ins & 0b100110000) == 0b100000000 {
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let mode = (ins & 0x08) == 0;
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// TODO implement ADDX
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panic!("Not Implemented");
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let src = get_low_reg(ins);
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let dest = get_high_reg(ins);
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match (ins & 0x08) == 0 {
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true => Ok(Instruction::ADDX(Target::DirectDReg(src), Target::DirectDReg(dest), size)),
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false => Ok(Instruction::ADDX(Target::IndirectARegDec(src), Target::DirectDReg(dest), size)),
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}
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} else {
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let target = self.decode_lower_effective_address(memory, ins, Some(size))?;
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if dir == 0 {
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@ -1,7 +1,7 @@
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use crate::system::System;
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use crate::error::{ErrorType, Error};
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use crate::devices::{ClockElapsed, Address, Steppable, Interruptable, Addressable, Transmutable};
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use crate::devices::{ClockElapsed, Address, Steppable, Interruptable, Addressable, Debuggable, Transmutable};
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use super::instructions::{
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Register,
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@ -67,6 +67,10 @@ impl Transmutable for M68k {
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fn as_interruptable(&mut self) -> Option<&mut dyn Interruptable> {
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Some(self)
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}
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fn as_debuggable(&mut self) -> Option<&mut dyn Debuggable> {
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Some(self)
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}
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}
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@ -98,6 +98,7 @@ pub enum Target {
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pub enum Instruction {
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ABCD(Target, Target),
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ADD(Target, Target, Size),
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ADDX(Target, Target, Size),
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AND(Target, Target, Size),
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ANDtoCCR(u8),
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ANDtoSR(u16),
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@ -183,6 +184,7 @@ pub enum Instruction {
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Scc(Condition, Target),
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STOP(u16),
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SUB(Target, Target, Size),
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SUBX(Target, Target, Size),
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SWAP(Register),
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TAS(Target),
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@ -32,6 +32,14 @@ mod decode_tests {
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(cpu, system)
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}
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fn load_memory(system: &System, data: &[u16]) {
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let mut addr = INIT_ADDR;
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for word in data {
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system.get_bus().write_beu16(addr, *word).unwrap();
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addr += 2;
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}
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}
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fn get_decode_memory(cpu: &mut M68k, system: &System) -> TransmutableBox {
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let (memory, relative_addr) = system.get_bus().get_device_at(INIT_ADDR, 12).unwrap();
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cpu.decoder.init((INIT_ADDR - relative_addr) as u32, INIT_ADDR as u32);
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@ -302,30 +310,130 @@ mod decode_tests {
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fn instruction_nop() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0x4e71).unwrap();
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load_memory(&system, &[0x4e71]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::NOP);
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}
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#[test]
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fn instruction_ori() {
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fn instruction_ori_byte() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0x0008).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x00FF).unwrap();
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load_memory(&system, &[0x0008, 0x00FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte));
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}
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#[test]
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fn instruction_ori_to_ccr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x003C, 0x00FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ORtoCCR(0xFF));
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}
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#[test]
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fn instruction_ori_to_sr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x007C, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ORtoSR(0x1234));
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}
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#[test]
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fn instruction_andi_word() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0263, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::AND(Target::Immediate(0x1234), Target::IndirectARegDec(3), Size::Word));
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}
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#[test]
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fn instruction_andi_to_ccr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x023C, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ANDtoCCR(0x34));
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}
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#[test]
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fn instruction_andi_to_sr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x027C, 0xF8FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ANDtoSR(0xF8FF));
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}
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#[test]
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fn instruction_subi() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0487, 0x1234, 0x5678]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::SUB(Target::Immediate(0x12345678), Target::DirectDReg(7), Size::Long));
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}
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#[test]
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fn instruction_addi() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x063A, 0x1234, 0x0055]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ADD(Target::Immediate(0x34), Target::IndirectRegOffset(BaseRegister::PC, None, 0x55), Size::Byte));
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}
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#[test]
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fn instruction_eori_byte() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0A23, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::EOR(Target::Immediate(0x34), Target::IndirectARegDec(3), Size::Byte));
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}
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#[test]
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fn instruction_eori_to_ccr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0A3C, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::EORtoCCR(0x34));
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}
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#[test]
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fn instruction_eori_to_sr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0A7C, 0xF8FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::EORtoSR(0xF8FF));
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}
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#[test]
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fn instruction_cmpi_equal() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0x7020).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x0C00).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 4, 0x0020).unwrap();
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cpu.step(&system).unwrap();
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load_memory(&system, &[0x0C00, 0x0020]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte));
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}
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@ -333,11 +441,9 @@ mod decode_tests {
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fn instruction_cmpi_greater() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0x7020).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x0C00).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 4, 0x0030).unwrap();
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cpu.step(&system).unwrap();
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load_memory(&system, &[0x0C00, 0x0030]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte));
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}
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@ -345,62 +451,59 @@ mod decode_tests {
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fn instruction_cmpi_less() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0x7020).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x0C00).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 4, 0x0010).unwrap();
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cpu.step(&system).unwrap();
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load_memory(&system, &[0x0C00, 0x0010]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte));
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}
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#[test]
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fn instruction_andi_sr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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fn instruction_movel_full_extension() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68030);
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system.get_bus().write_beu16(INIT_ADDR, 0x027C).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0xF8FF).unwrap();
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load_memory(&system, &[0x21bc, 0x0010, 0x14c4, 0x09b0, 0x0010, 0xdf40]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ANDtoSR(0xF8FF));
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}
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#[test]
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fn instruction_muls() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0xC1FC).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x0276).unwrap();
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed));
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}
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#[test]
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fn instruction_divs() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0x81FC).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x0003).unwrap();
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed));
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assert_eq!(cpu.decoder.instruction, Instruction::MOVE(Target::Immediate(1053892), Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Long }), 0x10df40), Size::Long));
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}
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#[test]
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fn instruction_mulsl() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68030);
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system.get_bus().write_beu16(INIT_ADDR, 0x4c3c).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x0800).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 4, 0x0000).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 6, 0x0097).unwrap();
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load_memory(&system, &[0x4c3c, 0x0800, 0x0000, 0x0097]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::MULL(Target::Immediate(0x97), None, 0, Sign::Signed));
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}
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#[test]
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fn instruction_divs() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x81FC, 0x0003]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed));
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}
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#[test]
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fn instruction_muls() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0xC1FC, 0x0276]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed));
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}
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#[test]
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fn instruction_asli() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0xE300).unwrap();
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load_memory(&system, &[0xE300]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left));
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}
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@ -408,8 +511,9 @@ mod decode_tests {
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fn instruction_asri() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0xE200).unwrap();
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load_memory(&system, &[0xE200]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right));
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}
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@ -417,8 +521,9 @@ mod decode_tests {
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fn instruction_roli() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0xE318).unwrap();
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load_memory(&system, &[0xE318]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left));
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}
|
||||
|
||||
|
|
@ -426,25 +531,11 @@ mod decode_tests {
|
|||
fn instruction_rori() {
|
||||
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
||||
|
||||
system.get_bus().write_beu16(INIT_ADDR, 0xE218).unwrap();
|
||||
load_memory(&system, &[0xE218]);
|
||||
cpu.decode_next(&system).unwrap();
|
||||
|
||||
assert_eq!(cpu.decoder.instruction, Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn instruction_movel_full_extension() {
|
||||
let (mut cpu, system) = init_decode_test(M68kType::MC68030);
|
||||
|
||||
let mut addr = INIT_ADDR;
|
||||
let data = [0x21bc, 0x0010, 0x14c4, 0x09b0, 0x0010, 0xdf40];
|
||||
for word in data {
|
||||
system.get_bus().write_beu16(addr, word).unwrap();
|
||||
addr += 2;
|
||||
}
|
||||
|
||||
cpu.decode_next(&system).unwrap();
|
||||
assert_eq!(cpu.decoder.instruction, Instruction::MOVE(Target::Immediate(1053892), Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Long }), 0x10df40), Size::Long));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -485,9 +576,10 @@ mod execute_tests {
|
|||
|
||||
cpu.decoder.instruction = Instruction::NOP;
|
||||
|
||||
let previous = cpu.state.clone();
|
||||
let expected_state = cpu.state.clone();
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state, previous);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -497,8 +589,12 @@ mod execute_tests {
|
|||
|
||||
cpu.decoder.instruction = Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2708;
|
||||
expected_state.a_reg[0] = 0x000000FF;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.a_reg[0], 0x000000FF);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -509,8 +605,11 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = value;
|
||||
cpu.decoder.instruction = Instruction::CMP(Target::Immediate(value), Target::DirectDReg(0), Size::Byte);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2704;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.sr & 0x0F, 0x04);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -520,8 +619,11 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x20;
|
||||
cpu.decoder.instruction = Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2709;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.sr & 0x0F, 0x09);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -531,8 +633,11 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x20;
|
||||
cpu.decoder.instruction = Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2700;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.sr & 0x0F, 0x00);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -542,8 +647,11 @@ mod execute_tests {
|
|||
cpu.state.sr = 0xA7AA;
|
||||
cpu.decoder.instruction = Instruction::ANDtoSR(0xF8FF);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0xA0AA;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.sr, 0xA0AA);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -553,8 +661,11 @@ mod execute_tests {
|
|||
cpu.state.sr = 0xA755;
|
||||
cpu.decoder.instruction = Instruction::ORtoSR(0x00AA);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0xA7FF;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.sr, 0xA7FF);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -565,8 +676,11 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x0200;
|
||||
cpu.decoder.instruction = Instruction::MULW(Target::Immediate(value), 0, Sign::Signed);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.d_reg[0] = 0x4ec00;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x4ec00);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -577,8 +691,11 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x40000;
|
||||
cpu.decoder.instruction = Instruction::DIVW(Target::Immediate(value), 0, Sign::Unsigned);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.d_reg[0] = 0x007101C3;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x007101C3);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -588,9 +705,12 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x01;
|
||||
cpu.decoder.instruction = Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2700;
|
||||
expected_state.d_reg[0] = 0x00000002;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x00000002);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x00);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -600,9 +720,12 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x81;
|
||||
cpu.decoder.instruction = Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2719;
|
||||
expected_state.d_reg[0] = 0x000000C0;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x000000C0);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x19);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -612,9 +735,12 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x80;
|
||||
cpu.decoder.instruction = Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2701;
|
||||
expected_state.d_reg[0] = 0x00000001;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x00000001);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x01);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -624,9 +750,12 @@ mod execute_tests {
|
|||
cpu.state.d_reg[0] = 0x01;
|
||||
cpu.decoder.instruction = Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2709;
|
||||
expected_state.d_reg[0] = 0x00000080;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x00000080);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x09);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -637,9 +766,12 @@ mod execute_tests {
|
|||
cpu.state.sr = 0x2700;
|
||||
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2715;
|
||||
expected_state.d_reg[0] = 0x00000000;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x00000000);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x15);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -650,9 +782,12 @@ mod execute_tests {
|
|||
cpu.state.sr = 0x2700;
|
||||
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2715;
|
||||
expected_state.d_reg[0] = 0x00000000;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x00000000);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x15);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -663,9 +798,12 @@ mod execute_tests {
|
|||
cpu.state.sr = 0x2700;
|
||||
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2700;
|
||||
expected_state.d_reg[0] = 0x00000001;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x00000001);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x00);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -676,9 +814,28 @@ mod execute_tests {
|
|||
cpu.state.sr = 0x2700;
|
||||
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2708;
|
||||
expected_state.d_reg[0] = 0x00000080;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state.d_reg[0], 0x00000080);
|
||||
assert_eq!(cpu.state.sr & 0x1F, 0x08);
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn instruction_neg_word() {
|
||||
let (mut cpu, system) = init_test();
|
||||
|
||||
cpu.state.d_reg[0] = 0x80;
|
||||
cpu.state.sr = 0x2700;
|
||||
cpu.decoder.instruction = Instruction::NEG(Target::DirectDReg(0), Size::Word);
|
||||
|
||||
let mut expected_state = cpu.state.clone();
|
||||
expected_state.sr = 0x2709;
|
||||
expected_state.d_reg[0] = 0x0000FF80;
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -102,6 +102,13 @@ pub fn write_beu32(value: u32) -> [u8; 4] {
|
|||
]
|
||||
}
|
||||
|
||||
/// A device that can debugged by putting it into debug mode, or setting breakpoints
|
||||
pub trait Debuggable {
|
||||
fn enable_debugging(&mut self);
|
||||
fn add_breakpoint(&mut self, addr: Address);
|
||||
}
|
||||
|
||||
|
||||
pub trait Transmutable {
|
||||
fn as_steppable(&mut self) -> Option<&mut dyn Steppable> {
|
||||
None
|
||||
|
|
@ -114,6 +121,10 @@ pub trait Transmutable {
|
|||
fn as_interruptable(&mut self) -> Option<&mut dyn Interruptable> {
|
||||
None
|
||||
}
|
||||
|
||||
fn as_debuggable(&mut self) -> Option<&mut dyn Debuggable> {
|
||||
None
|
||||
}
|
||||
}
|
||||
|
||||
pub type TransmutableBox = Rc<RefCell<Box<dyn Transmutable>>>;
|
||||
|
|
|
|||
8
todo.txt
8
todo.txt
|
|
@ -1,15 +1,11 @@
|
|||
|
||||
* should you simulate clock ticks, and only step devices when they next request it
|
||||
|
||||
|
||||
* make devices nameable, using a hashmap to store them
|
||||
* can you eventually make the system connections all configurable via a config file?
|
||||
* make it possible to break out of the current execution, into the debugger, by using a certain keystroke
|
||||
|
||||
|
||||
* make tests for each instruction
|
||||
|
||||
* unimplemented: ABCD, ADDX, BFFFO, BFINS, BKPT, CHK, EXG, ILLEGAL, MOVEfromCCR, MOVEP, RTR, RTD, SBCD, SUBX
|
||||
* undecoded: ADDX, SUBX
|
||||
* modify execution for >=MC68020: MOVEM
|
||||
* >=MC68020 undecoded & unimplemented: CALLM, CAS, CAS2, CHK2, CMP2, RTM, PACK, TRAPcc, UNPK
|
||||
|
||||
* add support for MMU
|
||||
|
|
|
|||
Loading…
Reference in New Issue