mirror of
https://github.com/transistorfet/moa.git
synced 2024-05-28 13:41:30 +00:00
932 lines
31 KiB
Rust
932 lines
31 KiB
Rust
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#[cfg(test)]
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mod decode_tests {
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use crate::error::{Error, ErrorType};
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use crate::system::System;
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use crate::memory::MemoryBlock;
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use crate::devices::{Address, Addressable, Steppable, TransmutableBox, wrap_transmutable, MAX_READ};
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use crate::cpus::m68k::{M68k, M68kType};
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use crate::cpus::m68k::state::Exceptions;
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use crate::cpus::m68k::instructions::{Instruction, Target, Size, Sign, XRegister, BaseRegister, IndexRegister, ShiftDirection};
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const INIT_STACK: Address = 0x00002000;
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const INIT_ADDR: Address = 0x00000010;
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fn init_decode_test(cputype: M68kType) -> (M68k, System) {
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let mut system = System::new();
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// Insert basic initialization
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let data = vec![0; 0x00100000];
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let mem = MemoryBlock::new(data);
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system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap();
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system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap();
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system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap();
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// Initialize the CPU and make sure it's in the expected state
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let mut cpu = M68k::new(cputype, 10_000_000);
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cpu.init(&system).unwrap();
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assert_eq!(cpu.state.pc, INIT_ADDR as u32);
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assert_eq!(cpu.state.msp, INIT_STACK as u32);
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assert_eq!(cpu.decoder.instruction, Instruction::NOP);
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(cpu, system)
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}
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fn load_memory(system: &System, data: &[u16]) {
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let mut addr = INIT_ADDR;
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for word in data {
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system.get_bus().write_beu16(addr, *word).unwrap();
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addr += 2;
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}
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}
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fn get_decode_memory(cpu: &mut M68k, system: &System) -> TransmutableBox {
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let (memory, relative_addr) = system.get_bus().get_device_at(INIT_ADDR, 12).unwrap();
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cpu.decoder.init((INIT_ADDR - relative_addr) as u32, INIT_ADDR as u32);
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memory
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}
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//
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// Addressing Mode Target Tests
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//
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#[test]
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fn target_direct_d() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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let expected = 0x1234;
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b000, 0b001, Some(size)).unwrap();
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assert_eq!(target, Target::DirectDReg(1));
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}
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#[test]
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fn target_direct_a() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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let expected = 0x1234;
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b001, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::DirectAReg(2));
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}
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#[test]
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fn target_indirect_a() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Long;
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let expected_addr = INIT_ADDR;
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let expected = 0x12345678;
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system.get_bus().write_beu32(INIT_ADDR, expected).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b010, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectAReg(2));
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}
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#[test]
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fn target_indirect_a_inc() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Long;
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let expected_addr = INIT_ADDR;
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let expected = 0x12345678;
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system.get_bus().write_beu32(INIT_ADDR, expected).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b011, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectARegInc(2));
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}
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#[test]
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fn target_indirect_a_dec() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Long;
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let expected_addr = INIT_ADDR + 4;
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let expected = 0x12345678;
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system.get_bus().write_beu32(INIT_ADDR, expected).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b100, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectARegDec(2));
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}
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#[test]
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fn target_indirect_a_reg_offset() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Long;
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let offset = -8;
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system.get_bus().write_beu16(INIT_ADDR, (offset as i16) as u16).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b101, 0b100, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(4), None, offset));
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}
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#[test]
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fn target_indirect_a_reg_brief_extension_word() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Long;
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let offset = -8;
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let brief_extension = 0x3800 | (((offset as i8) as u8) as u16);
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system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, (offset as i16) as u16).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), Some(IndexRegister { xreg: XRegister::DReg(3), scale: 0, size: size }), offset));
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}
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#[test]
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fn target_indirect_a_reg_full_extension_word() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68020);
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF330;
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system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap();
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system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset));
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}
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#[test]
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fn target_indirect_a_reg_full_extension_word_no_base() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68020);
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF3B0;
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system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap();
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system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset));
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}
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#[test]
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fn target_indirect_a_reg_full_extension_word_no_index() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68020);
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF370;
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system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap();
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system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b110, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::AReg(2), None, offset));
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}
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#[test]
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fn target_indirect_pc_offset() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Long;
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let offset = -8;
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system.get_bus().write_beu16(INIT_ADDR, (offset as i16) as u16).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b111, 0b010, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, None, offset));
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}
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#[test]
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fn target_indirect_pc_brief_extension_word() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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let offset = -8;
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let brief_extension = 0x3000 | (((offset as i8) as u8) as u16);
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system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, (offset as i16) as u16).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b111, 0b011, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::DReg(3), scale: 0, size: size }), offset));
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}
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#[test]
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fn target_indirect_pc_full_extension_word() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68020);
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let size = Size::Word;
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let offset = -1843235 as i32;
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let brief_extension = 0xF330;
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system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap();
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system.get_bus().write_beu32(INIT_ADDR + 2, offset as u32).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b111, 0b011, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectRegOffset(BaseRegister::PC, Some(IndexRegister { xreg: XRegister::AReg(7), scale: 1, size: size }), offset));
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}
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#[test]
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fn target_indirect_immediate_word() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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let expected = 0x1234;
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system.get_bus().write_beu16(INIT_ADDR, expected as u16).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b111, 0b000, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectMemory(expected));
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}
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#[test]
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fn target_indirect_immediate_long() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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let expected = 0x12345678;
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system.get_bus().write_beu32(INIT_ADDR, expected).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b111, 0b001, Some(size)).unwrap();
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assert_eq!(target, Target::IndirectMemory(expected));
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}
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#[test]
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fn target_immediate() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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let expected = 0x1234;
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system.get_bus().write_beu16(INIT_ADDR, expected as u16).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let target = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b111, 0b100, Some(size)).unwrap();
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assert_eq!(target, Target::Immediate(expected));
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}
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#[test]
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fn target_full_extension_word_unsupported_on_mc68010() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let brief_extension = 0x0100;
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system.get_bus().write_beu16(INIT_ADDR, brief_extension).unwrap();
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let memory = get_decode_memory(&mut cpu, &system);
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let result = cpu.decoder.get_mode_as_target(memory.borrow_mut().as_addressable().unwrap(), 0b110, 0b010, Some(Size::Long));
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match result {
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Err(Error { err: ErrorType::Processor, native, .. }) if native == Exceptions::IllegalInstruction as u32 => { },
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result => panic!("Expected illegal instruction but found: {:?}", result),
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}
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}
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//
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// Instruction Decode Tests
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//
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#[test]
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fn instruction_nop() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x4e71]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::NOP);
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}
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#[test]
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fn instruction_ori_byte() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0008, 0x00FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte));
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}
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#[test]
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fn instruction_ori_to_ccr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x003C, 0x00FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ORtoCCR(0xFF));
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}
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#[test]
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fn instruction_ori_to_sr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x007C, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ORtoSR(0x1234));
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}
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#[test]
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fn instruction_andi_word() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0263, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::AND(Target::Immediate(0x1234), Target::IndirectARegDec(3), Size::Word));
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}
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#[test]
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fn instruction_andi_to_ccr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x023C, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ANDtoCCR(0x34));
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}
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#[test]
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fn instruction_andi_to_sr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x027C, 0xF8FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ANDtoSR(0xF8FF));
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}
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#[test]
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fn instruction_subi() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0487, 0x1234, 0x5678]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::SUB(Target::Immediate(0x12345678), Target::DirectDReg(7), Size::Long));
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}
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#[test]
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fn instruction_addi() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x063A, 0x1234, 0x0055]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::ADD(Target::Immediate(0x34), Target::IndirectRegOffset(BaseRegister::PC, None, 0x55), Size::Byte));
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}
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#[test]
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fn instruction_eori_byte() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0A23, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::EOR(Target::Immediate(0x34), Target::IndirectARegDec(3), Size::Byte));
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}
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#[test]
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fn instruction_eori_to_ccr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0A3C, 0x1234]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::EORtoCCR(0x34));
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}
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#[test]
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fn instruction_eori_to_sr() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0A7C, 0xF8FF]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::EORtoSR(0xF8FF));
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}
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#[test]
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fn instruction_cmpi_equal() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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load_memory(&system, &[0x0C00, 0x0020]);
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::CMP(Target::Immediate(0x20), Target::DirectDReg(0), Size::Byte));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_cmpi_greater() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0x0C00, 0x0030]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_cmpi_less() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0x0C00, 0x0010]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_movel_full_extension() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68030);
|
|
|
|
load_memory(&system, &[0x21bc, 0x0010, 0x14c4, 0x09b0, 0x0010, 0xdf40]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::MOVE(Target::Immediate(1053892), Target::IndirectRegOffset(BaseRegister::None, Some(IndexRegister { xreg: XRegister::DReg(0), scale: 0, size: Size::Long }), 0x10df40), Size::Long));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_mulsl() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68030);
|
|
|
|
load_memory(&system, &[0x4c3c, 0x0800, 0x0000, 0x0097]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::MULL(Target::Immediate(0x97), None, 0, Sign::Signed));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_divs() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0x81FC, 0x0003]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_muls() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0xC1FC, 0x0276]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_asli() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0xE300]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_asri() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0xE200]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_roli() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0xE318]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left));
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_rori() {
|
|
let (mut cpu, system) = init_decode_test(M68kType::MC68010);
|
|
|
|
load_memory(&system, &[0xE218]);
|
|
cpu.decode_next(&system).unwrap();
|
|
|
|
assert_eq!(cpu.decoder.instruction, Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right));
|
|
}
|
|
}
|
|
|
|
|
|
#[cfg(test)]
|
|
mod execute_tests {
|
|
use crate::system::System;
|
|
use crate::memory::MemoryBlock;
|
|
use crate::devices::{Address, Addressable, Steppable, wrap_transmutable};
|
|
|
|
use crate::cpus::m68k::{M68k, M68kType};
|
|
use crate::cpus::m68k::instructions::{Instruction, Target, Size, Sign, ShiftDirection};
|
|
|
|
const INIT_STACK: Address = 0x00002000;
|
|
const INIT_ADDR: Address = 0x00000010;
|
|
|
|
fn init_test() -> (M68k, System) {
|
|
let mut system = System::new();
|
|
|
|
// Insert basic initialization
|
|
let data = vec![0; 0x00100000];
|
|
let mem = MemoryBlock::new(data);
|
|
system.add_addressable_device(0x00000000, wrap_transmutable(mem)).unwrap();
|
|
system.get_bus().write_beu32(0, INIT_STACK as u32).unwrap();
|
|
system.get_bus().write_beu32(4, INIT_ADDR as u32).unwrap();
|
|
|
|
let mut cpu = M68k::new(M68kType::MC68010, 10_000_000);
|
|
cpu.step(&system).unwrap();
|
|
assert_eq!(cpu.state.pc, INIT_ADDR as u32);
|
|
assert_eq!(cpu.state.msp, INIT_STACK as u32);
|
|
assert_eq!(cpu.decoder.instruction, Instruction::NOP);
|
|
(cpu, system)
|
|
}
|
|
|
|
|
|
#[test]
|
|
fn instruction_nop() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.decoder.instruction = Instruction::NOP;
|
|
|
|
let expected_state = cpu.state.clone();
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
|
|
#[test]
|
|
fn instruction_ori() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.decoder.instruction = Instruction::OR(Target::Immediate(0xFF), Target::DirectAReg(0), Size::Byte);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2708;
|
|
expected_state.a_reg[0] = 0x000000FF;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_cmpi_equal() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let value = 0x20;
|
|
cpu.state.d_reg[0] = value;
|
|
cpu.decoder.instruction = Instruction::CMP(Target::Immediate(value), Target::DirectDReg(0), Size::Byte);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2704;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_cmpi_greater() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x20;
|
|
cpu.decoder.instruction = Instruction::CMP(Target::Immediate(0x30), Target::DirectDReg(0), Size::Byte);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2709;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_cmpi_less() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x20;
|
|
cpu.decoder.instruction = Instruction::CMP(Target::Immediate(0x10), Target::DirectDReg(0), Size::Byte);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2700;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_andi_sr() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.sr = 0xA7AA;
|
|
cpu.decoder.instruction = Instruction::ANDtoSR(0xF8FF);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0xA0AA;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_ori_sr() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.sr = 0xA755;
|
|
cpu.decoder.instruction = Instruction::ORtoSR(0x00AA);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0xA7FF;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_muls() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let value = 0x0276;
|
|
cpu.state.d_reg[0] = 0x0200;
|
|
cpu.decoder.instruction = Instruction::MULW(Target::Immediate(value), 0, Sign::Signed);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.d_reg[0] = 0x4ec00;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_divu() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let value = 0x0245;
|
|
cpu.state.d_reg[0] = 0x40000;
|
|
cpu.decoder.instruction = Instruction::DIVW(Target::Immediate(value), 0, Sign::Unsigned);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.d_reg[0] = 0x007101C3;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_asli() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x01;
|
|
cpu.decoder.instruction = Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2700;
|
|
expected_state.d_reg[0] = 0x00000002;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_asri() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x81;
|
|
cpu.decoder.instruction = Instruction::ASd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2719;
|
|
expected_state.d_reg[0] = 0x000000C0;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_roli() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x80;
|
|
cpu.decoder.instruction = Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2701;
|
|
expected_state.d_reg[0] = 0x00000001;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_rori() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x01;
|
|
cpu.decoder.instruction = Instruction::ROd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2709;
|
|
expected_state.d_reg[0] = 0x00000080;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_roxl() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x80;
|
|
cpu.state.sr = 0x2700;
|
|
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2715;
|
|
expected_state.d_reg[0] = 0x00000000;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_roxr() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x01;
|
|
cpu.state.sr = 0x2700;
|
|
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(1), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2715;
|
|
expected_state.d_reg[0] = 0x00000000;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_roxl_2() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x80;
|
|
cpu.state.sr = 0x2700;
|
|
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Left);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2700;
|
|
expected_state.d_reg[0] = 0x00000001;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_roxr_2() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x01;
|
|
cpu.state.sr = 0x2700;
|
|
cpu.decoder.instruction = Instruction::ROXd(Target::Immediate(2), Target::DirectDReg(0), Size::Byte, ShiftDirection::Right);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2708;
|
|
expected_state.d_reg[0] = 0x00000080;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
#[test]
|
|
fn instruction_neg_word() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
cpu.state.d_reg[0] = 0x80;
|
|
cpu.state.sr = 0x2700;
|
|
cpu.decoder.instruction = Instruction::NEG(Target::DirectDReg(0), Size::Word);
|
|
|
|
let mut expected_state = cpu.state.clone();
|
|
expected_state.sr = 0x2709;
|
|
expected_state.d_reg[0] = 0x0000FF80;
|
|
|
|
cpu.execute_current(&system).unwrap();
|
|
assert_eq!(cpu.state, expected_state);
|
|
}
|
|
|
|
|
|
|
|
#[test]
|
|
fn target_value_direct_d() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let size = Size::Word;
|
|
let expected = 0x1234;
|
|
let target = Target::DirectDReg(1);
|
|
|
|
cpu.state.d_reg[1] = expected;
|
|
let result = cpu.get_target_value(&system, target, size).unwrap();
|
|
assert_eq!(result, expected);
|
|
}
|
|
|
|
#[test]
|
|
fn target_value_direct_a() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let size = Size::Word;
|
|
let expected = 0x1234;
|
|
let target = Target::DirectAReg(2);
|
|
|
|
cpu.state.a_reg[2] = expected;
|
|
let result = cpu.get_target_value(&system, target, size).unwrap();
|
|
assert_eq!(result, expected);
|
|
}
|
|
|
|
#[test]
|
|
fn target_value_indirect_a() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let size = Size::Long;
|
|
let expected_addr = INIT_ADDR;
|
|
let expected = 0x12345678;
|
|
let target = Target::IndirectAReg(2);
|
|
system.get_bus().write_beu32(INIT_ADDR, expected).unwrap();
|
|
|
|
cpu.state.a_reg[2] = INIT_ADDR as u32;
|
|
let result = cpu.get_target_value(&system, target, size).unwrap();
|
|
assert_eq!(result, expected);
|
|
}
|
|
|
|
#[test]
|
|
fn target_value_indirect_a_inc() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let size = Size::Long;
|
|
let expected_addr = INIT_ADDR;
|
|
let expected = 0x12345678;
|
|
let target = Target::IndirectARegInc(2);
|
|
system.get_bus().write_beu32(INIT_ADDR, expected).unwrap();
|
|
|
|
cpu.state.a_reg[2] = INIT_ADDR as u32;
|
|
let result = cpu.get_target_value(&system, target, size).unwrap();
|
|
assert_eq!(result, expected);
|
|
assert_eq!(cpu.state.a_reg[2], (INIT_ADDR as u32) + 4);
|
|
}
|
|
|
|
#[test]
|
|
fn target_value_indirect_a_dec() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let size = Size::Long;
|
|
let expected_addr = INIT_ADDR + 4;
|
|
let expected = 0x12345678;
|
|
let target = Target::IndirectARegDec(2);
|
|
system.get_bus().write_beu32(INIT_ADDR, expected).unwrap();
|
|
|
|
cpu.state.a_reg[2] = (INIT_ADDR as u32) + 4;
|
|
let result = cpu.get_target_value(&system, target, size).unwrap();
|
|
assert_eq!(result, expected);
|
|
assert_eq!(cpu.state.a_reg[2], INIT_ADDR as u32);
|
|
}
|
|
|
|
|
|
#[test]
|
|
fn target_value_immediate() {
|
|
let (mut cpu, system) = init_test();
|
|
|
|
let size = Size::Word;
|
|
let expected = 0x1234;
|
|
|
|
let target = Target::Immediate(expected);
|
|
|
|
let result = cpu.get_target_value(&system, target, size).unwrap();
|
|
assert_eq!(result, expected);
|
|
}
|
|
}
|
|
|
|
|