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https://github.com/transistorfet/moa.git
synced 2024-11-21 19:30:52 +00:00
Removed averaging of samples in ym2612 operators
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transistor
parent
258fd684e7
commit
43f655cdb4
@ -99,7 +99,7 @@ impl Channel {
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self.operators[3].get_sample(modulator2)
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},
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OperatorAlgorithm::A1 => {
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let sample1 = (self.operators[0].get_sample(0.0) + self.operators[1].get_sample(0.0)) / 2.0;
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let sample1 = self.operators[0].get_sample(0.0) + self.operators[1].get_sample(0.0);
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let sample2 = self.operators[2].get_sample(sample1);
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let sample3 = self.operators[3].get_sample(sample2);
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sample3
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@ -107,7 +107,7 @@ impl Channel {
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OperatorAlgorithm::A2 => {
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let sample1 = self.operators[1].get_sample(0.0);
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let sample2 = self.operators[2].get_sample(sample1);
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let sample3 = (self.operators[0].get_sample(0.0) + sample2) / 2.0;
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let sample3 = self.operators[0].get_sample(0.0) + sample2;
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let sample4 = self.operators[3].get_sample(sample3);
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sample4
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},
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@ -115,7 +115,7 @@ impl Channel {
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let sample1 = self.operators[0].get_sample(0.0);
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let sample2 = self.operators[1].get_sample(sample1);
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let sample3 = self.operators[2].get_sample(0.0);
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let sample4 = self.operators[3].get_sample((sample2 + sample3) / 2.0);
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let sample4 = self.operators[3].get_sample(sample2 + sample3);
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sample4
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},
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OperatorAlgorithm::A4 => {
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@ -123,24 +123,24 @@ impl Channel {
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let sample2 = self.operators[1].get_sample(sample1);
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let sample3 = self.operators[2].get_sample(0.0);
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let sample4 = self.operators[3].get_sample(sample3);
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(sample2 + sample4) / 2.0
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sample2 + sample4
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},
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OperatorAlgorithm::A5 => {
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let sample1 = self.operators[0].get_sample(0.0);
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let sample2 = (self.operators[1].get_sample(sample1) + self.operators[2].get_sample(sample1) + self.operators[3].get_sample(sample1)) / 3.0;
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let sample2 = self.operators[1].get_sample(sample1) + self.operators[2].get_sample(sample1) + self.operators[3].get_sample(sample1);
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sample2
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},
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OperatorAlgorithm::A6 => {
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let sample1 = self.operators[0].get_sample(0.0);
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let sample2 = self.operators[1].get_sample(sample1);
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(sample2 + self.operators[2].get_sample(0.0) + self.operators[3].get_sample(0.0)) / 3.0
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sample2 + self.operators[2].get_sample(0.0) + self.operators[3].get_sample(0.0)
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},
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OperatorAlgorithm::A7 => {
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let sample = self.operators[0].get_sample(0.0)
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+ self.operators[1].get_sample(0.0)
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+ self.operators[2].get_sample(0.0)
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+ self.operators[3].get_sample(0.0);
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sample / 4.0
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sample
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},
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}
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}
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@ -158,6 +158,16 @@ pub struct Ym2612 {
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pub dac_enabled: bool,
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pub dac: VecDeque<u8>,
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pub timer_a_enable: bool,
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pub timer_a: u16,
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pub timer_a_current: u16,
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pub timer_a_overflow: bool,
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pub timer_b_enable: bool,
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pub timer_b: u8,
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pub timer_b_current: u8,
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pub timer_b_overflow: bool,
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}
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impl Ym2612 {
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@ -168,59 +178,101 @@ impl Ym2612 {
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source,
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selected_reg_0: None,
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selected_reg_1: None,
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channels: vec![Channel::new(sample_rate); 8],
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channel_frequencies: [(0, 0); CHANNELS],
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dac_enabled: false,
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dac: VecDeque::with_capacity(100),
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timer_a_enable: false,
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timer_a: 0,
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timer_a_current: 0,
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timer_a_overflow: false,
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timer_b_enable: false,
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timer_b: 0,
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timer_b_current: 0,
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timer_b_overflow: false,
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})
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}
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pub fn set_register(&mut self, bank: usize, reg: usize, data: u8) {
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if reg == 0x28 {
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let ch = (data as usize) & 0x07;
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self.channels[ch].on = data >> 4;
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self.channels[ch].reset();
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println!("Note: {}: {:x}", ch, self.channels[ch].on);
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} else if reg == 0x2a {
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if self.dac_enabled {
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for _ in 0..3 {
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self.dac.push_back(data);
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}
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}
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} else if reg == 0x2b {
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self.dac_enabled = data & 0x80 != 0;
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} else if (reg & 0xF0) == 0x30 {
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let (ch, op) = get_ch_op(bank, reg);
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let multiplier = if data == 0 { 0.5 } else { (data & 0x0F) as f32 };
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let frequency = self.channels[ch].base_frequency;
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debug!("{}: channel {} operator {} set to multiplier {}", DEV_NAME, ch + 1, op + 1, multiplier);
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self.channels[ch].operators[op].set_multiplier(frequency, multiplier)
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} else if reg >= 0xA4 && reg <= 0xA6 {
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let ch = (reg & 0x07) - 4 + (bank * 3);
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self.channel_frequencies[ch].1 = (self.channel_frequencies[ch].1 & 0xFF) | ((data as u16) & 0x07) << 8;
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self.channel_frequencies[ch].0 = (data & 0x38) >> 3;
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} else if reg >= 0xA0 && reg <= 0xA2 {
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let ch = (reg & 0x07) + (bank * 3);
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self.channel_frequencies[ch].1 = (self.channel_frequencies[ch].1 & 0xFF00) | data as u16;
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match reg {
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0x24 => {
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self.timer_a = (self.timer_a & 0x3) | ((data as u16) << 2);
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},
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0x25 => {
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self.timer_a = (self.timer_a & 0xFFFC) | ((data as u16) & 0x03);
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},
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0x26 => {
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self.timer_b = data;
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},
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0x27 => {
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//if (data >> 5) & 0x1 {
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// self.timer_b
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},
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let frequency = fnumber_to_frequency(self.channel_frequencies[ch]);
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debug!("{}: channel {} set to frequency {}", DEV_NAME, ch + 1, frequency);
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self.channels[ch].set_frequency(frequency);
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} else if reg >= 0xB0 && reg <= 0xB2 {
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let ch = (reg & 0x07) + (bank * 3);
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self.channels[ch].algorithm = match data & 0x07 {
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0 => OperatorAlgorithm::A0,
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1 => OperatorAlgorithm::A1,
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2 => OperatorAlgorithm::A2,
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3 => OperatorAlgorithm::A3,
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4 => OperatorAlgorithm::A4,
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5 => OperatorAlgorithm::A5,
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6 => OperatorAlgorithm::A6,
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7 => OperatorAlgorithm::A7,
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_ => OperatorAlgorithm::A0,
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};
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} else {
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warning!("{}: !!! unhandled write to register {:0x} with {:0x}", DEV_NAME, reg, data);
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0x28 => {
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let ch = (data as usize) & 0x07;
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self.channels[ch].on = data >> 4;
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self.channels[ch].reset();
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println!("Note: {}: {:x}", ch, self.channels[ch].on);
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},
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0x2a => {
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if self.dac_enabled {
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for _ in 0..3 {
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self.dac.push_back(data);
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}
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}
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},
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0x2b => {
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self.dac_enabled = data & 0x80 != 0;
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},
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reg if (reg & 0xF0) == 0x30 => {
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let (ch, op) = get_ch_op(bank, reg);
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let multiplier = if data == 0 { 0.5 } else { (data & 0x0F) as f32 };
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let frequency = self.channels[ch].base_frequency;
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debug!("{}: channel {} operator {} set to multiplier {}", DEV_NAME, ch + 1, op + 1, multiplier);
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self.channels[ch].operators[op].set_multiplier(frequency, multiplier)
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},
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reg if reg >= 0xA0 && reg <= 0xA2 => {
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let ch = (reg & 0x07) + (bank * 3);
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self.channel_frequencies[ch].1 = (self.channel_frequencies[ch].1 & 0xFF00) | data as u16;
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let frequency = fnumber_to_frequency(self.channel_frequencies[ch]);
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debug!("{}: channel {} set to frequency {}", DEV_NAME, ch + 1, frequency);
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self.channels[ch].set_frequency(frequency);
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},
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reg if reg >= 0xA4 && reg <= 0xA6 => {
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let ch = (reg & 0x07) - 4 + (bank * 3);
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self.channel_frequencies[ch].1 = (self.channel_frequencies[ch].1 & 0xFF) | ((data as u16) & 0x07) << 8;
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self.channel_frequencies[ch].0 = (data & 0x38) >> 3;
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},
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reg if reg >= 0xB0 && reg <= 0xB2 => {
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let ch = (reg & 0x07) + (bank * 3);
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self.channels[ch].algorithm = match data & 0x07 {
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0 => OperatorAlgorithm::A0,
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1 => OperatorAlgorithm::A1,
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2 => OperatorAlgorithm::A2,
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3 => OperatorAlgorithm::A3,
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4 => OperatorAlgorithm::A4,
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5 => OperatorAlgorithm::A5,
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6 => OperatorAlgorithm::A6,
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7 => OperatorAlgorithm::A7,
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_ => OperatorAlgorithm::A0,
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};
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},
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_ => {
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warning!("{}: !!! unhandled write to register {:0x} with {:0x}", DEV_NAME, reg, data);
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},
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}
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}
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}
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@ -297,7 +349,7 @@ impl Addressable for Ym2612 {
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match addr {
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0 | 1 | 2 | 3 => {
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// Read the status byte (busy/overflow)
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data[0] = 0;
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data[0] = 0 | ((self.timer_a_overflow as u8) << 1) | (self.timer_b_overflow as u8);
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}
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_ => {
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warning!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
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