Modified for Instant as associated type in emulator-hal (#6)

* Modified for Instant as associated type in emulator-hal

* Updated emulator-hal to latest

emulator/core/src/memory.rs

@@ -388,7 +388,7 @@ pub fn dump_slice(data: &[u8], mut count: usize) {
 
 pub fn dump_memory<Bus, Address, Instant>(bus: &mut Bus, clock: Instant, addr: Address, count: Address)
 where
-    Bus: BusAccess<Address, Instant>,
+    Bus: BusAccess<Address, Instant = Instant>,
     Address: From<u64> + Into<u64> + Copy,
     Instant: Copy,
 {
@@ -416,7 +416,8 @@ use emulator_hal::bus::{self, BusAccess};
 
 impl bus::Error for Error {}
 
-impl BusAccess<u64, Instant> for &mut dyn Addressable {
+impl BusAccess<u64> for &mut dyn Addressable {
+    type Instant = Instant;
     type Error = Error;
 
     fn read(&mut self, now: Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {

emulator/cpus/m68k/src/debugger.rs

@@ -28,9 +28,9 @@ pub enum M68kInfo {
     State,
 }
 
-impl<Bus, BusError, Instant, Writer> Inspect<M68kAddress, Instant, Bus, Writer> for M68k<Instant>
+impl<Bus, BusError, Instant, Writer> Inspect<M68kAddress, Bus, Writer> for M68k<Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+    Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     BusError: bus::Error,
     Writer: fmt::Write,
 {
@@ -57,9 +57,9 @@ where
 }
 
 /// Control the execution of a CPU device for debugging purposes
-impl<Bus, BusError, Instant, Writer> Debug<M68kAddress, Instant, Bus, Writer> for M68k<Instant>
+impl<Bus, BusError, Instant, Writer> Debug<M68kAddress, Bus, Writer> for M68k<Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+    Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     BusError: bus::Error,
     Instant: time::Instant,
     Writer: fmt::Write,
@@ -103,7 +103,7 @@ pub struct M68kDebugger {
 
 impl<'a, Bus, BusError, Instant> M68kCycleExecutor<'a, Bus, Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+    Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     Instant: Copy,
 {
     pub fn check_breakpoints(&mut self) -> Result<(), M68kError<BusError>> {

emulator/cpus/m68k/src/decode.rs

@@ -41,7 +41,7 @@ pub struct M68kDecoder<Instant> {
 
 pub struct InstructionDecoding<'a, Bus, Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant>,
+    Bus: BusAccess<M68kAddress, Instant = Instant>,
 {
     pub(crate) bus: &'a mut Bus,
     pub(crate) memory: &'a mut M68kBusPort<Instant>,
@@ -81,7 +81,7 @@ where
         start: u32,
     ) -> Result<(), M68kError<Bus::Error>>
     where
-        Bus: BusAccess<M68kAddress, Instant>,
+        Bus: BusAccess<M68kAddress, Instant = Instant>,
     {
         self.init(is_supervisor, start);
         let mut decoding = InstructionDecoding {
@@ -95,7 +95,7 @@ where
 
     pub fn dump_disassembly<Bus>(&mut self, bus: &mut Bus, memory: &mut M68kBusPort<Instant>, start: u32, length: u32)
     where
-        Bus: BusAccess<M68kAddress, Instant>,
+        Bus: BusAccess<M68kAddress, Instant = Instant>,
     {
         let mut next = start;
         while next < (start + length) {
@@ -117,7 +117,7 @@ where
 
     pub fn dump_decoded<Bus>(&mut self, clock: Instant, bus: &mut Bus)
     where
-        Bus: BusAccess<M68kAddress, Instant>,
+        Bus: BusAccess<M68kAddress, Instant = Instant>,
     {
         let ins_data: Result<String, M68kError<Bus::Error>> = (0..((self.end - self.start) / 2))
             .map(|offset| Ok(format!("{:04x} ", bus.read_beu16(clock, self.start + (offset * 2)).unwrap())))
@@ -128,7 +128,7 @@ where
 
 impl<'a, Bus, Instant> InstructionDecoding<'a, Bus, Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant>,
+    Bus: BusAccess<M68kAddress, Instant = Instant>,
     Instant: Copy,
 {
     #[inline]

emulator/cpus/m68k/src/execute.rs

@@ -61,7 +61,7 @@ where
     #[inline]
     pub fn begin<Bus>(self, cpu: &mut M68k<Instant>, bus: Bus) -> M68kCycleExecutor<'_, Bus, Instant>
     where
-        Bus: BusAccess<M68kAddress, Instant>,
+        Bus: BusAccess<M68kAddress, Instant = Instant>,
     {
         cpu.stats.cycle_number = cpu.stats.cycle_number.wrapping_add(1);
 
@@ -74,9 +74,9 @@ where
     }
 }
 
-impl<Bus, BusError, Instant> Step<M68kAddress, Instant, Bus> for M68k<Instant>
+impl<Bus, BusError, Instant> Step<M68kAddress, Bus> for M68k<Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+    Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     BusError: bus::Error,
     Instant: time::Instant,
 {
@@ -110,7 +110,7 @@ where
 
 pub struct M68kCycleExecutor<'a, Bus, Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant>,
+    Bus: BusAccess<M68kAddress, Instant = Instant>,
 {
     pub state: &'a mut M68kState,
     pub bus: Bus,
@@ -120,7 +120,7 @@ where
 
 impl<'a, Bus, Instant> M68kCycleExecutor<'a, Bus, Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant>,
+    Bus: BusAccess<M68kAddress, Instant = Instant>,
     Instant: Copy,
 {
     pub fn end(self) -> M68kCycle<Instant> {
@@ -130,7 +130,7 @@ where
 
 impl<'a, Bus, Instant> M68kCycleExecutor<'a, Bus, Instant>
 where
-    Bus: BusAccess<M68kAddress, Instant>,
+    Bus: BusAccess<M68kAddress, Instant = Instant>,
     Instant: Copy,
 {
     #[inline]

emulator/cpus/m68k/src/memory.rs

@@ -173,7 +173,7 @@ where
         data: &mut [u8],
     ) -> Result<(), M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         let addr = addr & self.address_mask;
         for i in (0..data.len()).step_by(self.data_bytewidth) {
@@ -193,7 +193,7 @@ where
         data: &[u8],
     ) -> Result<(), M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         let addr = addr & self.address_mask;
         for i in (0..data.len()).step_by(self.data_bytewidth) {
@@ -207,7 +207,7 @@ where
 
     fn read_sized<Bus, BusError>(&mut self, bus: &mut Bus, addr: M68kAddress, size: Size) -> Result<u32, M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         let mut data = [0; 4];
         match size {
@@ -226,7 +226,7 @@ where
         value: u32,
     ) -> Result<(), M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         let data = value.to_be_bytes();
         match size {
@@ -244,7 +244,7 @@ where
         size: Size,
     ) -> Result<u32, M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         self.start_request(is_supervisor, addr, size, MemAccess::Read, MemType::Data, false)?;
         self.read_sized(bus, addr, size)
@@ -259,7 +259,7 @@ where
         value: u32,
     ) -> Result<(), M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         self.start_request(is_supervisor, addr, size, MemAccess::Write, MemType::Data, false)?;
         self.write_sized(bus, addr, size, value)
@@ -272,7 +272,7 @@ where
         addr: u32,
     ) -> Result<u16, M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         self.request.instruction(is_supervisor, addr)?;
         Ok(self.read_sized(bus, addr, Size::Word)? as u16)
@@ -285,7 +285,7 @@ where
         addr: u32,
     ) -> Result<u32, M68kError<BusError>>
     where
-        Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
+        Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     {
         self.request.instruction(is_supervisor, addr)?;
         self.read_sized(bus, addr, Size::Long)
@@ -327,7 +327,7 @@ fn validate_address<BusError>(addr: u32) -> Result<u32, M68kError<BusError>> {
 
 pub fn dump_memory<Bus, Address, Instant>(bus: &mut Bus, clock: Instant, addr: Address, count: Address)
 where
-    Bus: BusAccess<Address, Instant>,
+    Bus: BusAccess<Address, Instant = Instant>,
     Address: From<u32> + Into<u32> + Copy,
     Instant: Copy,
 {

emulator/cpus/m68k/src/moa.rs

@@ -10,7 +10,7 @@ impl Steppable for M68k<Instant> {
         let cycle = M68kCycle::new(self, system.clock);
 
         let mut bus = system.bus.borrow_mut();
-        let mut adapter: bus::BusAdapter<u32, u64, Instant, &mut dyn Addressable, Error> =
+        let mut adapter: bus::BusAdapter<u32, u64, &mut dyn Addressable, Error> =
             bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
 
         let mut executor = cycle.begin(self, &mut adapter);
@@ -99,7 +99,7 @@ impl Debuggable for M68k<Instant> {
         let mut memory = M68kBusPort::from_info(&self.info, system.clock);
 
         let mut bus = system.bus.borrow_mut();
-        let mut adapter: bus::BusAdapter<u32, u64, Instant, &mut dyn Addressable, Error> =
+        let mut adapter: bus::BusAdapter<u32, u64, &mut dyn Addressable, Error> =
             bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
 
         decoder.dump_disassembly(&mut adapter, &mut memory, addr as u32, count as u32);

emulator/cpus/m68k/tests/decode_tests.rs

@@ -81,10 +81,10 @@ fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, Me
     (cpu, cycle, memory)
 }
 
-fn load_memory<Bus: BusAccess<u32, Instant>>(memory: &mut Bus, data: &[u16]) {
+fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(memory: &mut Bus, data: &[u16]) {
     let mut addr = INIT_ADDR;
     for word in data {
-        memory.write_beu16(Instant::START, addr, *word).unwrap();
+        memory.write_beu16(Bus::Instant::START, addr, *word).unwrap();
         addr += 2;
     }
 }

emulator/cpus/m68k/tests/execute_tests.rs

@@ -76,7 +76,7 @@ fn build_state(state: &TestState) -> M68kState {
     new_state
 }
 
-fn load_memory<Bus: BusAccess<u32, Instant>>(bus: &mut Bus, data: &[u16]) {
+fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(bus: &mut Bus, data: &[u16]) {
     for i in 0..data.len() {
         bus.write_beu16(Instant::START, (i << 1) as u32, data[i]).unwrap();
     }

emulator/cpus/m68k/tests/musashi_timing_tests.rs

@@ -29,7 +29,7 @@ fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, Me
     (cpu, cycle, memory)
 }
 
-fn load_memory<Bus: BusAccess<u32, Instant>>(bus: &mut Bus, data: &[u16]) {
+fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(bus: &mut Bus, data: &[u16]) {
     let mut addr = INIT_ADDR;
     for word in data {
         bus.write_beu16(Instant::START, addr, *word).unwrap();

emulator/cpus/m68k/tests/timing_tests.rs

@@ -43,7 +43,7 @@ fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, Me
     (cpu, cycle, memory)
 }
 
-fn load_memory<Bus: BusAccess<u32, Instant>>(bus: &mut Bus, data: &[u16]) {
+fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(bus: &mut Bus, data: &[u16]) {
     let mut addr = INIT_ADDR;
     for word in data {
         bus.write_beu16(Instant::START, addr, *word).unwrap();

emulator/libraries/emulator-hal

@@ -1 +1 @@
-Subproject commit 10000669524747dce101947e60f230551b26f6f8
+Subproject commit 2391a324376bdd9fa1ae9801bbe3d12f2e69fa62