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https://github.com/transistorfet/moa.git
synced 2024-06-10 07:29:31 +00:00
Fixed some warnings
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parent
2c2b8e58b4
commit
8060f7179b
1
.gitignore
vendored
1
.gitignore
vendored
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@ -2,6 +2,7 @@ Cargo.lock
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.*.sw?
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/target
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*.vim
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junk/
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perf.data
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perf.data.old
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@ -505,7 +505,7 @@ fn convert_indirect(lineno: usize, args: &[AssemblyOperand], disallow: Disallow)
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}
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}
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fn convert_reg_and_other<'a>(lineno: usize, args: &'a [AssemblyOperand], disallow: Disallow) -> Result<(u16, u16, &'a AssemblyOperand), Error> {
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fn convert_reg_and_other<'a>(lineno: usize, args: &'a [AssemblyOperand], _disallow: Disallow) -> Result<(u16, u16, &'a AssemblyOperand), Error> {
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match &args {
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&[AssemblyOperand::Register(reg), effective_address] => {
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Ok(((0b1 << 8), expect_reg_num(lineno, ®)?, effective_address))
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@ -600,6 +600,7 @@ fn encode_size_for_move(size: Size) -> u16 {
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}
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}
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#[allow(dead_code)]
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fn encode_size_bit(size: Size) -> Result<u16, Error> {
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match size {
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Size::Word => Ok(0b01 << 6),
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@ -825,14 +825,14 @@ impl M68k {
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for i in 0..8 {
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if (mask & 0x01) != 0 {
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self.state.d_reg[i] = sign_extend_to_long(self.get_address_sized(addr as Address, size)?, size) as u32;
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addr += size.in_bytes();
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(addr, _) = overflowing_add_sized(addr, size.in_bytes(), Size::Long);
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}
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mask >>= 1;
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}
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for i in 0..8 {
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if (mask & 0x01) != 0 {
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*self.get_a_reg_mut(i) = sign_extend_to_long(self.get_address_sized(addr as Address, size)?, size) as u32;
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addr += size.in_bytes();
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(addr, _) = overflowing_add_sized(addr, size.in_bytes(), Size::Long);
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}
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mask >>= 1;
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}
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@ -1058,7 +1058,7 @@ impl M68k {
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fn get_x_reg_value(&self, xreg: XRegister) -> u32 {
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match xreg {
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XRegister::DReg(reg) => self.state.d_reg[reg as usize],
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XRegister::AReg(reg) => self.state.a_reg[reg as usize],
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XRegister::AReg(reg) => self.get_a_reg(reg),
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}
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}
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@ -1091,6 +1091,15 @@ impl M68k {
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if self.is_supervisor() { &mut self.state.ssp } else { &mut self.state.usp }
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}
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#[inline(always)]
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fn get_a_reg(&self, reg: Register) -> u32 {
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if reg == 7 {
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if self.is_supervisor() { self.state.ssp } else { self.state.usp }
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} else {
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self.state.a_reg[reg as usize]
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}
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}
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#[inline(always)]
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fn get_a_reg_mut(&mut self, reg: Register) -> &mut u32 {
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if reg == 7 {
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@ -162,6 +162,7 @@ mod decode_tests {
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}
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/*
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#[test]
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pub fn run_assembler_opcode_tests() {
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let mut tests = 0;
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@ -196,6 +197,7 @@ mod decode_tests {
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panic!("{} errors out of {} tests", errors, tests);
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}
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}
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*/
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//use super::super::testcases::{TimingCase, TIMING_TESTS};
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@ -198,7 +198,7 @@ impl Addressable for GenesisControllers {
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}
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impl Steppable for GenesisControllers {
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fn step(&mut self, system: &System) -> Result<ClockElapsed, Error> {
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fn step(&mut self, _system: &System) -> Result<ClockElapsed, Error> {
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let duration = 100_000; // Update every 100us
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self.reset_timer += duration;
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@ -1,6 +1,4 @@
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use std::iter::Iterator;
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use crate::error::Error;
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use crate::system::System;
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use crate::memory::dump_slice;
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@ -191,7 +189,7 @@ impl Ym7101Memory {
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Ok(())
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}
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pub fn write_data_port(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
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pub fn write_data_port(&mut self, data: &[u8]) -> Result<(), Error> {
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if (self.transfer_type & 0x30) == 0x20 {
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self.ctrl_port_buffer = None;
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self.transfer_fill_word = if data.len() >= 2 { read_beu16(data) } else { data[0] as u16 };
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@ -211,7 +209,7 @@ impl Ym7101Memory {
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Ok(())
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}
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pub fn write_control_port(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
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pub fn write_control_port(&mut self, data: &[u8]) -> Result<(), Error> {
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let value = read_beu16(data);
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match (data.len(), self.ctrl_port_buffer) {
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(2, None) => { self.ctrl_port_buffer = Some(value) },
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@ -814,7 +812,7 @@ impl Addressable for Ym7101 {
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fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
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match addr {
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// Write to Data Port
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0x00 | 0x02 => self.state.memory.write_data_port(addr, data)?,
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0x00 | 0x02 => self.state.memory.write_data_port(data)?,
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// Write to Control Port
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0x04 | 0x06 => {
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@ -831,7 +829,7 @@ impl Addressable for Ym7101 {
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self.set_register(value);
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}
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} else {
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self.state.memory.write_control_port(addr, data)?;
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self.state.memory.write_control_port(data)?;
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self.state.status = (self.state.status & !STATUS_DMA_BUSY) | (if self.state.memory.transfer_dma_busy { STATUS_DMA_BUSY } else { 0 });
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}
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},
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@ -70,7 +70,7 @@ impl NoiseGenerator {
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info!("set attenuation to {} {}", self.attenuation, self.on);
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}
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pub fn set_control(&mut self, bits: u8) {
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pub fn set_control(&mut self, _bits: u8) {
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//let frequency = 3_579_545.0 / (count as f32 * 32.0);
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//self.wave.set_frequency(frequency);
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//debug!("set frequency to {}", frequency);
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@ -48,7 +48,7 @@ impl Operator {
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self.wave.reset();
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}
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pub fn set_multiplier(&mut self, frequency: f32, multiplier: f32) {
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pub fn set_multiplier(&mut self, _frequency: f32, multiplier: f32) {
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self.multiplier = multiplier;
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}
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