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Fixed controllers in Earthworm Jim (but not Mortal Kombat 1)

This commit is contained in:
transistor 2022-01-16 10:39:57 -08:00
parent d21e2c4d6a
commit a60e72fc04
3 changed files with 17 additions and 19 deletions
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12
src/peripherals/genesis/controllers.rs
View File

@ -50,13 +50,13 @@ impl GenesisControllerPort {
match (th_state, self.th_count) {
(true, 0) => self.outputs | ((inputs & 0x003F) as u8),
(false, 0) => self.outputs | (((inputs & 0x00C0) >> 2) as u8) | ((inputs & 0x0003) as u8),
(false, 1) => self.outputs | (((inputs & 0x00C0) >> 2) as u8) | ((inputs & 0x0003) as u8),
(true, 1) => self.outputs | ((inputs & 0x003F) as u8),
(false, 1) => self.outputs | (((inputs & 0x00C0) >> 2) as u8),
(false, 2) => self.outputs | (((inputs & 0x00C0) >> 2) as u8),
(true, 2) => self.outputs | ((inputs & 0x0030) as u8) | (((inputs & 0x0F00) >> 8) as u8),
(false, 2) => self.outputs | (((inputs & 0x00C0) >> 2) as u8) | 0x0F,
(false, 3) => self.outputs | (((inputs & 0x00C0) >> 2) as u8) | 0x0F,
(true, 3) => self.outputs | ((inputs & 0x003F) as u8),
(false, 3) => self.outputs | (((inputs & 0x00C0) >> 2) as u8) | ((inputs & 0x0003) as u8),
(false, 1) => self.outputs | (((inputs & 0x00C0) >> 2) as u8) | ((inputs & 0x0003) as u8),
_ => 0,
}
}
@ -173,14 +173,14 @@ impl Addressable for GenesisControllers {
REG_S_CTRL3 => { data[i] = self.expansion.s_ctrl | 0x02; },
_ => { warning!("{}: !!! unhandled reading from {:0x}", DEV_NAME, addr); },
}
debug!("{}: read from register {:x} the value {:x}", DEV_NAME, addr, data[0]);
info!("{}: read from register {:x} the value {:x}", DEV_NAME, addr, data[0]);
Ok(())
}
fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
self.reset_timer = 0;
debug!("{}: write to register {:x} with {:x}", DEV_NAME, addr, data[0]);
info!("{}: write to register {:x} with {:x}", DEV_NAME, addr, data[0]);
match addr {
REG_DATA1 => { self.port_1.set_data(data[0]); }
REG_DATA2 => { self.port_2.set_data(data[0]); },

10
src/peripherals/genesis/ym7101.rs
View File

@ -159,7 +159,7 @@ impl Ym7101Memory {
4 => Memory::Vsram,
_ => Memory::Cram,
};
info!("{}: transfer requested of type {:x} ({:?}) to address {:x}", DEV_NAME, self.transfer_type, self.transfer_target, self.transfer_dest_addr);
debug!("{}: transfer requested of type {:x} ({:?}) to address {:x}", DEV_NAME, self.transfer_type, self.transfer_target, self.transfer_dest_addr);
if (self.transfer_type & 0x20) != 0 {
if (self.transfer_type & 0x10) != 0 {
self.set_dma_mode(DmaType::Copy);
@ -227,7 +227,7 @@ impl Ym7101Memory {
match self.transfer_run {
DmaType::Memory => {
info!("{}: starting dma transfer {:x} from Mem:{:x} to {:?}:{:x} ({} bytes)", DEV_NAME, self.transfer_type, self.transfer_src_addr, self.transfer_target, self.transfer_dest_addr, self.transfer_remain);
debug!("{}: starting dma transfer {:x} from Mem:{:x} to {:?}:{:x} ({} bytes)", DEV_NAME, self.transfer_type, self.transfer_src_addr, self.transfer_target, self.transfer_dest_addr, self.transfer_remain);
let mut bus = system.get_bus();
while self.transfer_remain > 0 {
@ -245,7 +245,7 @@ impl Ym7101Memory {
}
},
DmaType::Copy => {
info!("{}: starting dma copy from VRAM:{:x} to VRAM:{:x} ({} bytes)", DEV_NAME, self.transfer_src_addr, self.transfer_dest_addr, self.transfer_remain);
debug!("{}: starting dma copy from VRAM:{:x} to VRAM:{:x} ({} bytes)", DEV_NAME, self.transfer_src_addr, self.transfer_dest_addr, self.transfer_remain);
while self.transfer_remain > 0 {
self.vram[self.transfer_dest_addr as usize] = self.vram[self.transfer_src_addr as usize];
self.transfer_dest_addr += self.transfer_auto_inc;
@ -254,7 +254,7 @@ impl Ym7101Memory {
}
},
DmaType::Fill => {
info!("{}: starting dma fill to VRAM:{:x} ({} bytes) with {:x}", DEV_NAME, self.transfer_dest_addr, self.transfer_remain, self.transfer_fill_word);
debug!("{}: starting dma fill to VRAM:{:x} ({} bytes) with {:x}", DEV_NAME, self.transfer_dest_addr, self.transfer_remain, self.transfer_fill_word);
while self.transfer_remain > 0 {
self.vram[self.transfer_dest_addr as usize] = self.transfer_fill_word as u8;
self.transfer_dest_addr += self.transfer_auto_inc;
@ -697,7 +697,7 @@ impl Ym7101 {
fn set_register(&mut self, word: u16) {
let reg = ((word & 0x1F00) >> 8) as usize;
let data = (word & 0x00FF) as u8;
info!("{}: register {:x} set to {:x}", DEV_NAME, reg, data);
debug!("{}: register {:x} set to {:x}", DEV_NAME, reg, data);
self.update_register_value(reg, data);
}

14
todo.txt
View File

@ -57,20 +57,18 @@ Debugger:
Genesis/Mega Drive:
* there's a bug when Sonic 2 goes to the demo screen, it's all corrupted (could it be a dma copy error)
* fix sprite/cell priorities so that they're drawn correctly
* implement highlight and shadow mode, which is also related to the priority
* implement sn76489 and ym2612 for audio
* in some games the controller doesn't seem to work at all (Earthworm Jim, and Mortal Kombat)
* refactor ym7101 into multiple files perhaps. You can separate the DMA stuff, the address/interfacing parts, and the graphics state
* refactor to print line by line, so that colour palette changes have an effect
* there's a bug when Sonic 2 goes to the demo screen, it's all corrupted (could it be a dma copy error)
* colours are still broken in Sonic1
* sonic3 needs some kind of nvram to run
* implement sn76489 and ym2612 for audio
* the 68000/Z80 bank switching is probably buggy, and there's that other banking stuff in the 0xC00000 range, which isn't implemented at all
* add support for the H/V counters at 0xC00008
* fix ym7101 to better handle V/H interrupts (right now it sets and then the next step will clear, but it'd be nice if it could 'edge trigger')
* the 68000/Z80 bank switching is probably buggy
* the H/V counters are not accurate because it seems to count at different speeds in the blanking period (time vs return value numbers don't divide properly)
* make the ym7101 set/reset the v_int occurred flag based on the interrupt controller
* add support for the sprite overflow flag (low priority)
* still possibly a bug with the shadow/highlight colours
Macintosh: