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Minor fixes

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This commit is contained in:
transistor 2022-01-06 23:40:22 -08:00
parent c6eeed03ff
commit b8906fdbb1
3 changed files with 10 additions and 13 deletions
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5
src/host/gfx.rs
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@ -108,6 +108,11 @@ impl FrameSwapper {
pub fn swap(&mut self) { pub fn swap(&mut self) {
std::mem::swap(&mut self.current.lock().unwrap().bitmap, &mut self.previous.lock().unwrap().bitmap); std::mem::swap(&mut self.current.lock().unwrap().bitmap, &mut self.previous.lock().unwrap().bitmap);
} }
pub fn set_size(&mut self, width: u32, height: u32) {
self.previous.lock().unwrap().set_size(width, height);
self.current.lock().unwrap().set_size(width, height);
}
} }
impl WindowUpdater for FrameSwapper { impl WindowUpdater for FrameSwapper {

12
src/peripherals/genesis/coprocessor.rs
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@ -46,18 +46,10 @@ impl Addressable for CoprocessorCoordinator {
match addr { match addr {
0x000 => { /* ROM vs DRAM mode */ }, 0x000 => { /* ROM vs DRAM mode */ },
0x100 => { 0x100 => {
if data[0] != 0 { self.bus_request.set(data[0] != 0);
self.bus_request.set(true);
} else {
self.bus_request.set(false);
}
}, },
0x200 => { 0x200 => {
if data[0] == 0 { self.reset.set(data[0] == 0);
self.reset.set(true);
} else {
self.reset.set(false);
}
}, },
_ => { warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr); }, _ => { warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr); },
} }

6
src/peripherals/genesis/ym7101.rs
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@ -150,10 +150,10 @@ impl Ym7101Memory {
} }
} }
pub fn setup_transfer(&mut self, upper: u16, lower: u16) { pub fn setup_transfer(&mut self, first: u16, second: u16) {
self.ctrl_port_buffer = None; self.ctrl_port_buffer = None;
self.transfer_type = ((((upper & 0xC000) >> 14) | ((lower & 0x00F0) >> 2))) as u8; self.transfer_type = ((((first & 0xC000) >> 14) | ((second & 0x00F0) >> 2))) as u8;
self.transfer_dest_addr = ((upper & 0x3FFF) | ((lower & 0x0003) << 14)) as u32; self.transfer_dest_addr = ((first & 0x3FFF) | ((second & 0x0003) << 14)) as u32;
self.transfer_target = match self.transfer_type & 0x0E { self.transfer_target = match self.transfer_type & 0x0E {
0 => Memory::Vram, 0 => Memory::Vram,
4 => Memory::Vsram, 4 => Memory::Vsram,