transistor
94141e112e
Reorganized decode and add some support for other m68k processors
2021-10-10 14:26:54 -07:00
transistor
c4f41d73ab
Put the types and traits from system into new devices file
2021-10-08 23:11:52 -07:00
transistor
7bd7f3e64f
Added cpu to system, and refactored m68k a bit
2021-10-07 11:35:15 -07:00
transistor
73d11ddb79
Switched to using Rc<RefCell<Box<dyn Trait>>> for devices
2021-10-07 09:41:01 -07:00
transistor
e186637f49
Refactored such that System is the top level object
2021-10-06 16:14:56 -07:00
transistor
59019d9c8e
Refactored address space again
2021-10-05 19:58:22 -07:00
transistor
f2a23a21cb
Added ROd instruction and fixed bug with MOVEM
2021-10-05 16:22:21 -07:00
transistor
338e68a1d9
Fixed some erroneous instruction decodes and added binaries
2021-10-03 09:55:20 -07:00
transistor
10e905674b
Added MUL, DIV, NEG, DBcc, and Scc instructions, and fixed issue with ADD/SUB flags
...
With ADDA, SUBA, and ADDQ/SUBQ when the target is an address register, the condition
flags should not be changed, but the code was changing them, which caused problems.
I've fixed it by making the ADD/SUB executions check for an address target and
will not update flags in that case. This should only occur when the actual instruction
was an ADDA or ADDQ with an address register target
2021-10-02 21:59:28 -07:00
transistor
98883e3daa
Added the Asd, LINK, and UNLK instructions
2021-10-02 15:35:08 -07:00
transistor
38bcf0af3f
Reorganized state and decoding into their own structs
2021-10-02 08:47:20 -07:00
transistor
b0f094cb59
Added start of a testsuite
2021-10-01 19:27:05 -07:00
