Commit Graph

18 Commits

Author SHA1 Message Date
transistor
d0037c8125 Fixed tests and clippy warnings 2024-03-16 13:15:34 -07:00
transistor
c20d7afe6e Fixed some tests 2024-03-15 23:01:41 -07:00
transistor
59306bceff Fixed alloc in harte_tests that was taking all the time 2024-03-14 22:35:02 -07:00
transistor
545f339fe2 Separated moa-core dependency into an optional feature flag 2024-03-13 21:49:04 -07:00
transistor
ec74b64984 Added stats 2024-03-08 23:38:51 -08:00
transistor
8b274f72cc Modified to use emulator-hal traits 2024-03-08 19:41:36 -08:00
transistor
48bf76f430 Fixed some ASR cases, and updated test results 2022-09-18 22:09:56 -07:00
transistor
f5a548ac90 Added test results 2022-09-18 17:10:23 -07:00
transistor
481dd0d7f7 Fixed part of the problem in RTE test failures with Address Error
The I/N bit in the special status word on the stack should be set
when returning from RTE results in a PC that isn't word aligned.
Every other case pretty much, it should be clear
2022-09-17 21:29:04 -07:00
transistor
71c10ff0f0 Slightly improved the handling of the I/N bit in Address Error 2022-09-16 20:49:44 -07:00
transistor
84d2b5e15b Added test results 2022-09-14 22:51:48 -07:00
transistor
d074b7fc5e Test after fixing MULS 2022-09-13 22:18:22 -07:00
transistor
873741846c Implemented the CHK and NEGX instructions 2022-09-12 22:19:01 -07:00
transistor
9ff528c463 Fixed some AddressError tests
Adjusted the PC value stored when an Address Error fault occurs to
use the size of the access operation.

I also flipped the IN bit in the word that's written to the top of
the stack on an AddressError, even though that's opposite of what
the docs say.  It seems to pass the tests.  I probably have something
else going wrong, but it shouldn't be an important bit either way.
2022-09-12 21:47:36 -07:00
transistor
42bfabb743 Added test results 2022-09-11 21:52:29 -07:00
transistor
03f4e11e3b Added proper AddressError handling to m68k
Also a few fixes, such as correcting a decode error in ADDX
2022-09-11 17:42:54 -07:00
transistor
0582625b5e Fixed some issue with m68k
Some debug code was enabled that prevented illegal instructions
from being handled normally with a processor exception

The brief instruction word decoding could cause an illegal instruction
if it didn't match the docs, but the actual implementation would not
complain in those cases, so I modified it to not perform validation
for <=MC68010

Increment and Decrement addressing modes, when using the stack pointer,
will always inc/dec by at least 2 bytes, even if it's a byte operation,
to keep the stack aligned to the nearest word boundary
2022-09-10 21:09:35 -07:00
transistor
27f71b0f33 Added test results 2022-09-10 20:49:26 -07:00