It does something, but doesn't work as it should. It could be a few
things including the on/off signal being too slow due to how time
works in the sample generation, but I wanted to at least commit what
I have. It seems to work roughly right according to the forum post
that describes the chip's operation in detail, but there could still
be some glaring bugs
The hope was that this would reduce the amount of copying and bit
shifting required by the frontend to get the data on screen, but
it doesn't seem to offer much advantage, surprisingly. I'll leave
it in though. There are a few other minor tweaks included here to
try to improve the performance a bit
It wasn't copying the frame data from the sources to the output frame
correctly, and there was a small period of zeros at the start of the
frame.
I also converted to using a vec of tuples for the two channels to
make it easier to reason about, since some of the issues were related
to the differences sizes calculated from the clock based on the sample
rate
It's a bit weirdly implemented because the Addressable trait doesn't
have access to System, so it has to set a flag on the Bus which is
then checked during the step function in System to activate the
breakpoint if a watched memory location was written to
