mirror of
https://github.com/transistorfet/moa.git
synced 2024-05-28 13:41:30 +00:00
595 lines
22 KiB
Rust
595 lines
22 KiB
Rust
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use std::iter::Iterator;
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use std::sync::{Arc, Mutex};
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use crate::error::Error;
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use crate::system::System;
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use crate::devices::{Clock, ClockElapsed, Address, Addressable, Steppable, Transmutable, MAX_READ, read_beu16, read_beu32, write_beu16};
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use crate::host::traits::{Host, BlitableSurface};
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use crate::host::gfx::{Frame, FrameSwapper};
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const REG_MODE_SET_1: usize = 0x00;
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const REG_MODE_SET_2: usize = 0x01;
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const REG_SCROLL_A_ADDR: usize = 0x02;
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const REG_WINDOW_ADDR: usize = 0x03;
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const REG_SCROLL_B_ADDR: usize = 0x04;
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const REG_SPRITES_ADDR: usize = 0x05;
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// Register 0x06 Unused
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const REG_BACKGROUND: usize = 0x07;
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// Register 0x08 Unused
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// Register 0x09 Unused
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const REG_H_INTERRUPT: usize = 0x0A;
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const REG_MODE_SET_3: usize = 0x0B;
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const REG_MODE_SET_4: usize = 0x0C;
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const REG_HSCROLL_ADDR: usize = 0x0D;
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// Register 0x0E Unused
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const REG_AUTO_INCREMENT: usize = 0x0F;
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const REG_SCROLL_SIZE: usize = 0x10;
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const REG_WINDOW_H_POS: usize = 0x11;
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const REG_WINDOW_V_POS: usize = 0x12;
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const REG_DMA_COUNTER_LOW: usize = 0x13;
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const REG_DMA_COUNTER_HIGH: usize = 0x14;
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const REG_DMA_ADDR_LOW: usize = 0x15;
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const REG_DMA_ADDR_MID: usize = 0x16;
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const REG_DMA_ADDR_HIGH: usize = 0x17;
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const STATUS_PAL_MODE: u16 = 0x0001;
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const STATUS_DMA_BUSY: u16 = 0x0002;
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const STATUS_IN_HBLANK: u16 = 0x0004;
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const STATUS_IN_VBLANK: u16 = 0x0008;
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const STATUS_ODD_FRAME: u16 = 0x0010;
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const STATUS_SPRITE_COLLISION: u16 = 0x0020;
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const STATUS_SPRITE_OVERFLOW: u16 = 0x0040;
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const STATUS_V_INTERRUPT: u16 = 0x0080;
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const STATUS_FIFO_FULL: u16 = 0x0100;
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const STATUS_FIFO_EMPTY: u16 = 0x0200;
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const MODE1_BF_ENABLE_HV_COUNTER: u8 = 0x02;
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const MODE1_BF_HSYNC_INTERRUPT: u8 = 0x10;
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const MODE2_BF_V_CELL_MODE: u8 = 0x08;
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const MODE2_BF_VSYNC_INTERRUPT: u8 = 0x20;
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const MODE4_BF_H_CELL_MODE: u8 = 0x01;
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const DEV_NAME: &'static str = "ym7101";
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum DmaType {
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None,
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Memory,
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Fill,
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Copy,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum TargetType {
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Vram,
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Cram,
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Vsram,
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}
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pub struct Ym7101State {
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pub status: u16,
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pub regs: [u8; 24],
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pub vram: [u8; 0x10000],
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pub cram: [u8; 128],
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pub vsram: [u8; 80],
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pub transfer_type: u8,
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pub transfer_addr: u32,
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pub transfer_fill: u16,
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pub transfer_run: DmaType,
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pub transfer_target: TargetType,
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pub transfer_upper: Option<u16>,
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pub last_clock: Clock,
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pub h_clock: u32,
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pub v_clock: u32,
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pub h_scanlines: u8,
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pub reset_int: bool,
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}
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impl Ym7101State {
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pub fn new() -> Self {
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Self {
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status: STATUS_FIFO_EMPTY,
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regs: [0; 24],
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vram: [0; 0x10000],
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cram: [0; 128],
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vsram: [0; 80],
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transfer_type: 0,
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transfer_addr: 0,
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transfer_fill: 0,
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transfer_run: DmaType::None,
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transfer_target: TargetType::Vram,
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transfer_upper: None,
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last_clock: 0,
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h_clock: 0,
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v_clock: 0,
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h_scanlines: 0,
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reset_int: false,
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}
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}
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fn set_register(&mut self, data: u16) {
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let reg = (data & 0x1F00) >> 8;
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self.regs[reg as usize] = (data & 0x00FF) as u8;
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info!("{}: register {:x} set to {:x}", DEV_NAME, reg, self.regs[reg as usize]);
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}
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pub fn set_dma_mode(&mut self, mode: DmaType) {
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match mode {
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DmaType::None => {
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self.status &= !STATUS_DMA_BUSY;
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self.transfer_run = DmaType::None;
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},
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_ => {
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self.status |= STATUS_DMA_BUSY;
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self.transfer_run = mode;
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},
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}
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}
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pub fn get_dma_src_addr(&mut self) -> u32 {
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let src_addr = (((self.regs[REG_DMA_ADDR_HIGH] & 0x7F) as u32) << 17)
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| ((self.regs[REG_DMA_ADDR_MID] as u32) << 9)
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| ((self.regs[REG_DMA_ADDR_LOW] as u32) << 1);
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if (self.regs[REG_DMA_ADDR_HIGH] & 0x80) == 0 {
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src_addr
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} else {
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src_addr & !0x00800000
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}
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}
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pub fn get_dma_count(&mut self) -> i32 {
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(((self.regs[REG_DMA_COUNTER_HIGH] as u32) << 8) | (self.regs[REG_DMA_COUNTER_LOW] as u32)) as i32
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}
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pub fn setup_transfer(&mut self, upper: u16, lower: u16) {
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self.transfer_upper = None;
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self.transfer_type = ((((upper & 0xC000) >> 14) | ((lower & 0x00F0) >> 2))) as u8;
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self.transfer_addr = ((upper & 0x3FFF) | ((lower & 0x0003) << 14)) as u32;
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self.transfer_target = match self.transfer_type & 0x0E {
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0 => TargetType::Vram,
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4 => TargetType::Vsram,
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_ => TargetType::Cram,
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};
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info!("{}: transfer requested of type {:x} ({:?}) to address {:x}", DEV_NAME, self.transfer_type, self.transfer_target, self.transfer_addr);
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if (self.transfer_type & 0x20) != 0 {
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if (self.transfer_type & 0x10) != 0 {
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self.set_dma_mode(DmaType::Copy);
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} else if (self.regs[REG_DMA_ADDR_HIGH] & 0x80) == 0 {
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self.set_dma_mode(DmaType::Memory);
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}
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}
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}
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pub fn get_transfer_target_mut(&mut self) -> &mut [u8] {
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match self.transfer_target {
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TargetType::Vram => &mut self.vram,
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TargetType::Cram => &mut self.cram,
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TargetType::Vsram => &mut self.vsram,
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}
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}
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#[inline(always)]
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fn hsync_int_enabled(&self) -> bool {
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(self.regs[REG_MODE_SET_1] & MODE1_BF_HSYNC_INTERRUPT) != 0
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}
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#[inline(always)]
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fn vsync_int_enabled(&self) -> bool {
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(self.regs[REG_MODE_SET_2] & MODE2_BF_VSYNC_INTERRUPT) != 0
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}
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pub fn get_vram_scroll_a_addr(&self) -> u32 {
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((self.regs[REG_SCROLL_A_ADDR] as u16) << 10) as u32
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}
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pub fn get_vram_scroll_b_addr(&self) -> u32 {
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((self.regs[REG_SCROLL_B_ADDR] as u16) << 13) as u32
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}
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pub fn get_vram_window_addr(&self) -> u32 {
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((self.regs[REG_WINDOW_ADDR] as u16) << 10) as u32
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}
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pub fn get_palette_colour(&self, palette: u8, colour: u8) -> u32 {
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if colour == 0 {
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return 0;
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}
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let rgb = read_beu16(&self.cram[(((palette * 16) + colour) * 2) as usize..]);
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(((rgb & 0xF00) as u32) >> 4) | (((rgb & 0x0F0) as u32) << 8) | (((rgb & 0x00F) as u32) << 20)
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}
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pub fn get_pattern_iter<'a>(&'a self, pattern_name: u16) -> PatternIterator<'a> {
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let pattern_addr = (pattern_name & 0x07FF) << 5;
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let pattern_palette = ((pattern_name & 0x6000) >> 13) as u8;
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let h_rev = (pattern_name & 0x0800) != 0;
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let v_rev = (pattern_name & 0x1000) != 0;
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PatternIterator::new(&self, pattern_addr as u32, pattern_palette, h_rev, v_rev)
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}
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pub fn get_scroll_size(&self) -> (u16, u16) {
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let h = scroll_size(self.regs[REG_SCROLL_SIZE] & 0x03);
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let v = scroll_size((self.regs[REG_SCROLL_SIZE] >> 4) & 0x03);
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(h, v)
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}
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pub fn get_window_coords(&self) -> ((u16, u16), (u16, u16)) {
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let h_cells = if (self.regs[REG_MODE_SET_4] & MODE4_BF_H_CELL_MODE) == 0 { 32 } else { 40 };
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let v_cells = if (self.regs[REG_MODE_SET_2] & MODE2_BF_V_CELL_MODE) == 0 { 28 } else { 30 };
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let win_h = ((self.regs[REG_WINDOW_H_POS] & 0x1F) << 1) as u16;
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let win_v = (self.regs[REG_WINDOW_V_POS] & 0x1F) as u16;
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// TODO this ignores the upper bits of the registers
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if (self.regs[REG_WINDOW_H_POS] & 0x80) != 0 || (self.regs[REG_WINDOW_V_POS] & 0x80) != 0 {
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panic!("window variations not implemented yet");
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}
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((win_h, win_v), (win_h + h_cells, win_v + v_cells))
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}
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pub fn draw_frame(&mut self, frame: &mut Frame) {
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let coords = self.get_window_coords();
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let scroll_size = self.get_scroll_size();
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let bg_colour = self.get_palette_colour((self.regs[REG_BACKGROUND] & 0x30) >> 4, self.regs[REG_BACKGROUND] & 0x0f);
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for i in 0..(frame.width as usize * frame.height as usize) {
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frame.bitmap[i] = bg_colour;
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}
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self.draw_cell_table(frame, self.get_vram_scroll_b_addr(), coords, scroll_size);
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self.draw_cell_table(frame, self.get_vram_scroll_a_addr(), coords, scroll_size);
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self.draw_cell_table(frame, self.get_vram_window_addr(), coords, scroll_size);
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self.draw_sprites(frame, (self.regs[REG_SPRITES_ADDR] as u32) << 9, coords, scroll_size);
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}
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pub fn draw_cell_table(&mut self, frame: &mut Frame, cell_table: u32, coords: ((u16, u16), (u16, u16)), scroll_size: (u16, u16)) {
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let ((win_x_start, win_y_start), (win_x_end, win_y_end)) = coords;
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for cell_y in win_y_start..win_y_end {
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for cell_x in win_x_start..win_x_end {
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let pattern_name = read_beu16(&self.vram[(cell_table + (cell_x + (cell_y * scroll_size.0) << 1) as u32) as usize..]);
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let iter = self.get_pattern_iter(pattern_name);
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frame.blit((cell_x << 3) as u32, (cell_y << 3) as u32, iter, 8, 8);
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}
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}
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}
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pub fn draw_sprites(&mut self, frame: &mut Frame, sprite_table: u32, coords: ((u16, u16), (u16, u16)), scroll_size: (u16, u16)) {
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let ((win_x_start, win_y_start), (win_x_end, win_y_end)) = coords;
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for i in 0..(scroll_size.0 as u32 * 2) {
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let sprite_addr = (sprite_table + (i * 8)) as usize;
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let v_pos = read_beu16(&self.vram[sprite_addr..]);
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let size = self.vram[sprite_addr + 2];
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let link = self.vram[sprite_addr + 3];
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let pattern_name = read_beu16(&self.vram[(sprite_addr + 4)..]);
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let h_pos = read_beu16(&self.vram[(sprite_addr + 6)..]);
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let iter = self.get_pattern_iter(pattern_name);
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frame.blit(h_pos as u32, v_pos as u32, iter, 8, 8);
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}
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}
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}
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fn scroll_size(size: u8) -> u16 {
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match size {
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0b00 => 32,
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0b01 => 64,
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0b11 => 128,
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_ => panic!("{}: invalid scroll size option {:x}", DEV_NAME, size),
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}
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}
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pub struct PatternIterator<'a> {
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state: &'a Ym7101State,
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palette: u8,
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base: usize,
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h_rev: bool,
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v_rev: bool,
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line: i8,
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col: i8,
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second: bool,
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}
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impl<'a> PatternIterator<'a> {
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pub fn new(state: &'a Ym7101State, start: u32, palette: u8, h_rev: bool, v_rev: bool) -> Self {
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Self {
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state,
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palette,
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base: start as usize,
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h_rev,
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v_rev,
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line: 0,
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col: 0,
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second: false,
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}
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}
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}
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impl<'a> Iterator for PatternIterator<'a> {
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type Item = u32;
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fn next(&mut self) -> Option<Self::Item> {
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let offset = self.base + (if !self.v_rev { self.line } else { 7 - self.line }) as usize * 4 + (if !self.h_rev { self.col } else { 3 - self.col }) as usize;
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let value = if (!self.h_rev && !self.second) || (self.h_rev && self.second) {
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self.state.get_palette_colour(self.palette, self.state.vram[offset] >> 4)
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} else {
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self.state.get_palette_colour(self.palette, self.state.vram[offset] & 0x0f)
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};
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if !self.second {
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self.second = true;
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} else {
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self.second = false;
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self.col += 1;
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if self.col >= 4 {
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self.col = 0;
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self.line += 1;
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}
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}
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Some(value)
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}
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}
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pub struct Ym7101 {
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pub swapper: Arc<Mutex<FrameSwapper>>,
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pub state: Ym7101State,
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}
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impl Ym7101 {
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pub fn new<H: Host>(host: &H) -> Ym7101 {
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let swapper = FrameSwapper::new_shared();
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swapper.lock().map(|mut swapper| {
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swapper.current.set_size(320, 224);
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swapper.previous.set_size(320, 224);
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});
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host.add_window(FrameSwapper::to_boxed(swapper.clone()));
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Ym7101 {
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swapper,
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state: Ym7101State::new(),
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}
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}
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}
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impl Transmutable for Ym7101 {
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fn as_addressable(&mut self) -> Option<&mut dyn Addressable> {
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Some(self)
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}
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fn as_steppable(&mut self) -> Option<&mut dyn Steppable> {
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Some(self)
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}
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}
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impl Steppable for Ym7101 {
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fn step(&mut self, system: &System) -> Result<ClockElapsed, Error> {
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let diff = (system.clock - self.state.last_clock) as u32;
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self.state.last_clock = system.clock;
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if self.state.reset_int {
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system.get_interrupt_controller().set(false, 4, 28)?;
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system.get_interrupt_controller().set(false, 6, 30)?;
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}
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self.state.h_clock += diff;
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if (self.state.status & STATUS_IN_HBLANK) == 0 && self.state.v_clock > 58_820 {
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self.state.status |= STATUS_IN_HBLANK;
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}
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if self.state.h_clock > 63_500 {
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self.state.status &= !STATUS_IN_HBLANK;
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self.state.h_clock = 0;
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self.state.h_scanlines = self.state.h_scanlines.wrapping_sub(1);
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if self.state.hsync_int_enabled() && self.state.h_scanlines == 0 {
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self.state.h_scanlines = self.state.regs[REG_H_INTERRUPT];
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system.get_interrupt_controller().set(true, 4, 28)?;
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self.state.reset_int = true;
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}
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}
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self.state.v_clock += diff;
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if (self.state.status & STATUS_IN_VBLANK) == 0 && self.state.v_clock > 14_218_000 {
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self.state.status |= STATUS_IN_VBLANK;
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}
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if self.state.v_clock > 16_630_000 {
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self.state.status &= !STATUS_IN_VBLANK;
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self.state.v_clock = 0;
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if self.state.vsync_int_enabled() {
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system.get_interrupt_controller().set(true, 6, 30)?;
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self.state.reset_int = true;
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}
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let mut swapper = self.swapper.lock().unwrap();
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self.state.draw_frame(&mut swapper.current);
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//let mut swapper = self.swapper.lock().unwrap();
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//let iter = PatternIterator::new(&self.state, 0x260, 0, true, true);
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//swapper.current.blit(0, 0, iter, 8, 8);
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/*
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// Print Palette
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for i in 0..16 {
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println!("{:x}", self.state.get_palette_colour(0, i));
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}
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*/
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/*
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// Print Pattern Table
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let mut swapper = self.swapper.lock().unwrap();
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let coords = self.state.get_window_coords();
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for cell_y in coords.0.1..coords.1.1 {
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for cell_x in coords.0.0..coords.1.0 {
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let pattern_addr = (cell_x + (cell_y * 40)) * 32;
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let iter = PatternIterator::new(&self.state, pattern_addr as u32, 0);
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swapper.current.blit((cell_x << 3) as u32, (cell_y << 3) as u32, iter, 8, 8);
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}
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}
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*/
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}
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|
|
if self.state.transfer_run != DmaType::None {
|
|
// TODO we will just do the full dma transfer here, but it really should be stepped
|
|
|
|
match self.state.transfer_run {
|
|
DmaType::Memory => {
|
|
let mut src_addr = self.state.get_dma_src_addr();
|
|
let mut count = self.state.get_dma_count();
|
|
|
|
info!("{}: starting dma transfer {:x} from Mem:{:x} to {:?}:{:x} ({} bytes)", DEV_NAME, self.state.transfer_type, src_addr, self.state.transfer_target, self.state.transfer_addr, count);
|
|
let mut bus = system.get_bus();
|
|
|
|
// TODO temporary for debugging, will break at the first cram transfer after the display is on
|
|
//if (self.state.regs[REG_MODE_SET_2] & 0x40) != 0 && self.state.transfer_target == TargetType::Cram {
|
|
// system.get_interrupt_controller().target.as_ref().map(|cpu| cpu.borrow_mut().as_debuggable().unwrap().enable_debugging());
|
|
//}
|
|
|
|
//bus.dump_memory(src_addr as Address, count as Address);
|
|
while count > 0 {
|
|
let mut data = [0; 2];
|
|
bus.read(src_addr as Address, &mut data)?;
|
|
|
|
{
|
|
let addr = self.state.transfer_addr;
|
|
let mut target = self.state.get_transfer_target_mut();
|
|
target[addr as usize] = data[0];
|
|
target[addr as usize + 1] = data[1];
|
|
}
|
|
|
|
self.state.transfer_addr += self.state.regs[REG_AUTO_INCREMENT] as u32;
|
|
src_addr += 2;
|
|
count -= 2;
|
|
}
|
|
},
|
|
DmaType::Copy => {
|
|
let mut src_addr = self.state.get_dma_src_addr();
|
|
let mut count = self.state.get_dma_count();
|
|
|
|
info!("{}: starting dma copy from VRAM:{:x} to VRAM:{:x} ({} bytes)", DEV_NAME, src_addr, self.state.transfer_addr, count);
|
|
while count > 0 {
|
|
self.state.vram[self.state.transfer_addr as usize] = self.state.vram[src_addr as usize];
|
|
self.state.transfer_addr += self.state.regs[REG_AUTO_INCREMENT] as u32;
|
|
src_addr += 1;
|
|
count -= 1;
|
|
}
|
|
},
|
|
DmaType::Fill => {
|
|
let mut count = self.state.get_dma_count();
|
|
|
|
info!("{}: starting dma fill to VRAM:{:x} ({} bytes) with {:x}", DEV_NAME, self.state.transfer_addr, count, self.state.transfer_fill);
|
|
while count > 0 {
|
|
self.state.vram[self.state.transfer_addr as usize] = self.state.transfer_fill as u8;
|
|
self.state.transfer_addr += self.state.regs[REG_AUTO_INCREMENT] as u32;
|
|
count -= 1;
|
|
}
|
|
},
|
|
_ => { warning!("{}: !!! error unexpected transfer mode {:x}", DEV_NAME, self.state.transfer_type); },
|
|
}
|
|
|
|
self.state.set_dma_mode(DmaType::None);
|
|
}
|
|
|
|
Ok((1_000_000_000 / 13_423_294) * 4)
|
|
}
|
|
}
|
|
|
|
impl Addressable for Ym7101 {
|
|
fn len(&self) -> usize {
|
|
0x20
|
|
}
|
|
|
|
fn read(&mut self, addr: Address, data: &mut [u8]) -> Result<(), Error> {
|
|
match addr {
|
|
// Read from Data Port
|
|
0x00 | 0x02 => {
|
|
{
|
|
let addr = self.state.transfer_addr;
|
|
let target = self.state.get_transfer_target_mut();
|
|
for i in 0..data.len() {
|
|
data[i] = target[addr as usize + i];
|
|
}
|
|
}
|
|
self.state.transfer_addr += self.state.regs[REG_AUTO_INCREMENT] as u32;
|
|
info!("{}: data port read {} bytes from {:?}:{:x} returning {:x},{:x}", DEV_NAME, data.len(), self.state.transfer_target, addr, data[0], data[1]);
|
|
},
|
|
|
|
// Read from Control Port
|
|
0x04 | 0x06 => {
|
|
debug!("{}: read status byte {:x}", DEV_NAME, self.state.status);
|
|
data[0] = (self.state.status >> 8) as u8;
|
|
data[1] = (self.state.status & 0x00FF) as u8;
|
|
},
|
|
|
|
_ => { println!("{}: !!! unhandled read from {:x}", DEV_NAME, addr); },
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
|
|
match addr {
|
|
// Write to Data Port
|
|
0x00 | 0x02 => {
|
|
if (self.state.transfer_type & 0x30) == 0x20 {
|
|
self.state.transfer_upper = None;
|
|
self.state.transfer_fill = read_beu16(data);
|
|
self.state.set_dma_mode(DmaType::Fill);
|
|
} else {
|
|
info!("{}: data port write {} bytes to {:?}:{:x} with {:?}", DEV_NAME, data.len(), self.state.transfer_target, self.state.transfer_addr, data);
|
|
|
|
{
|
|
let addr = self.state.transfer_addr as usize;
|
|
let target = self.state.get_transfer_target_mut();
|
|
for i in 0..data.len() {
|
|
target[addr + i] = data[i];
|
|
}
|
|
}
|
|
self.state.transfer_addr += self.state.regs[REG_AUTO_INCREMENT] as u32;
|
|
}
|
|
},
|
|
|
|
// Write to Control Port
|
|
0x04 | 0x06 => {
|
|
debug!("{}: write {} bytes to port {:x} with data {:?}", DEV_NAME, data.len(), addr, data);
|
|
|
|
let value = read_beu16(data);
|
|
if (value & 0xC000) == 0x8000 {
|
|
self.state.set_register(value);
|
|
if data.len() == 4 {
|
|
let value = read_beu16(&data[2..]);
|
|
if (value & 0xC000) != 0x8000 {
|
|
panic!("Unexpected");
|
|
}
|
|
self.state.set_register(value);
|
|
}
|
|
} else {
|
|
match (data.len(), self.state.transfer_upper) {
|
|
(2, None) => { self.state.transfer_upper = Some(value) },
|
|
(2, Some(upper)) => self.state.setup_transfer(upper, read_beu16(data)),
|
|
(4, None) => self.state.setup_transfer(value, read_beu16(&data[2..])),
|
|
_ => { error!("{}: !!! error when writing to control port with {} bytes of {:?}", DEV_NAME, data.len(), data); },
|
|
}
|
|
}
|
|
},
|
|
|
|
_ => { warning!("{}: !!! unhandled write to {:x} with {:?}", DEV_NAME, addr, data); },
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
|