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Apple2-IO-RPi/Hardware/Apple2IORPi.kicad_pcb

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Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2build2)
(general
(thickness 1.6)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(drawings 77)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(tracks 0)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(zones 0)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(modules 14)
(nets 97)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(page USLetter)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user hide)
(35 F.Paste user hide)
(36 B.SilkS user)
(37 F.SilkS user)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(38 B.Mask user hide)
(39 F.Mask user hide)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(40 Dwgs.User user hide)
(41 Cmts.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
(44 Edge.Cuts user)
(45 Margin user hide)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(46 B.CrtYd user hide)
(47 F.CrtYd user hide)
(48 B.Fab user hide)
(49 F.Fab user hide)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
(setup
Update PCB component layout
2020-11-17 00:21:56 +00:00
(last_trace_width 0.1778)
(trace_clearance 0.1778)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(zone_clearance 0.508)
(zone_45_only no)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(trace_min 0.1778)
(via_size 0.762)
(via_drill 0.50038)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 "Net-(U0-Pad15)")
(net 2 "Net-(U1-Pad2)")
(net 3 "Net-(U0-Pad14)")
(net 4 "Net-(J0-Pad9)")
(net 5 "Net-(U0-Pad13)")
(net 6 "Net-(J0-Pad8)")
(net 7 "Net-(U0-Pad12)")
(net 8 "Net-(J0-Pad7)")
(net 9 "Net-(U0-Pad11)")
(net 10 "Net-(J0-Pad6)")
(net 11 "Net-(J0-Pad1)")
(net 12 "Net-(J0-Pad5)")
(net 13 "Net-(J0-Pad12)")
(net 14 "Net-(J0-Pad4)")
(net 15 "Net-(J0-Pad3)")
(net 16 "Net-(U1-Pad23)")
(net 17 "Net-(J0-Pad2)")
(net 18 "Net-(J0-Pad11)")
(net 19 "Net-(U0-Pad18)")
(net 20 "Net-(J0-Pad10)")
(net 21 "Net-(U0-Pad17)")
(net 22 "Net-(U1-Pad26)")
(net 23 "Net-(U0-Pad16)")
(net 24 "Net-(J0-Pad13)")
(net 25 "Net-(J0-Pad14)")
(net 26 "Net-(J0-Pad15)")
(net 27 "Net-(J0-Pad16)")
(net 28 "Net-(J0-Pad17)")
(net 29 "Net-(J0-Pad18)")
(net 30 "Net-(J0-Pad19)")
(net 31 "Net-(J0-Pad20)")
(net 32 "Net-(J0-Pad21)")
(net 33 "Net-(J0-Pad22)")
(net 34 "Net-(J0-Pad23)")
(net 35 "Net-(J0-Pad24)")
(net 36 "Net-(J0-Pad29)")
(net 37 "Net-(J0-Pad30)")
(net 38 "Net-(J0-Pad31)")
(net 39 "Net-(J0-Pad32)")
(net 40 "Net-(J0-Pad33)")
(net 41 "Net-(J0-Pad34)")
(net 42 "Net-(J0-Pad35)")
(net 43 "Net-(J0-Pad36)")
(net 44 "Net-(J0-Pad37)")
(net 45 "Net-(J0-Pad38)")
(net 46 "Net-(J0-Pad39)")
(net 47 "Net-(J0-Pad40)")
(net 48 "Net-(J0-Pad43)")
(net 49 "Net-(J0-Pad44)")
(net 50 "Net-(J0-Pad45)")
(net 51 "Net-(J0-Pad46)")
(net 52 "Net-(J0-Pad47)")
(net 53 "Net-(J0-Pad48)")
(net 54 "Net-(J0-Pad49)")
(net 55 "Net-(J0-Pad50)")
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 56 "Net-(J1-Pad3)")
(net 57 "Net-(J1-Pad5)")
(net 58 "Net-(J1-Pad7)")
(net 59 "Net-(J1-Pad8)")
(net 60 "Net-(J1-Pad10)")
(net 61 "Net-(J1-Pad11)")
(net 62 "Net-(J1-Pad12)")
(net 63 "Net-(J1-Pad13)")
(net 64 "Net-(J1-Pad15)")
(net 65 "Net-(J1-Pad16)")
(net 66 "Net-(J1-Pad18)")
(net 67 "Net-(J1-Pad19)")
(net 68 "Net-(J1-Pad21)")
(net 69 "Net-(J1-Pad22)")
(net 70 "Net-(J1-Pad23)")
(net 71 "Net-(J1-Pad24)")
(net 72 "Net-(J1-Pad26)")
(net 73 "Net-(J1-Pad27)")
(net 74 "Net-(J1-Pad28)")
(net 75 "Net-(J1-Pad29)")
(net 76 "Net-(J1-Pad31)")
(net 77 "Net-(J1-Pad32)")
(net 78 "Net-(J1-Pad33)")
(net 79 "Net-(J1-Pad35)")
(net 80 "Net-(J1-Pad36)")
(net 81 "Net-(J1-Pad37)")
(net 82 "Net-(J1-Pad38)")
(net 83 "Net-(J1-Pad40)")
(net 84 "Net-(U0-Pad1)")
(net 85 "Net-(J0-Pad42)")
(net 86 "Net-(U0-Pad19)")
(net 87 "Net-(U2-Pad3)")
(net 88 "Net-(U2-Pad8)")
(net 89 "Net-(J0-Pad41)")
(net 90 "Net-(U3-Pad1)")
(net 91 "Net-(U3-Pad10)")
(net 92 "Net-(C1-Pad2)")
(net 93 "Net-(C1-Pad1)")
(net 94 "Net-(C5-Pad1)")
(net 95 "Net-(U3-Pad3)")
(net 96 "Net-(U3-Pad8)")
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(net_class Default "This is the default net class."
Update PCB component layout
2020-11-17 00:21:56 +00:00
(clearance 0.1778)
(trace_width 0.1778)
(via_dia 0.762)
(via_drill 0.50038)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(uvia_dia 0.3)
(uvia_drill 0.1)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(add_net "Net-(C5-Pad1)")
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(add_net "Net-(J0-Pad1)")
(add_net "Net-(J0-Pad10)")
(add_net "Net-(J0-Pad11)")
(add_net "Net-(J0-Pad12)")
(add_net "Net-(J0-Pad13)")
(add_net "Net-(J0-Pad14)")
(add_net "Net-(J0-Pad15)")
(add_net "Net-(J0-Pad16)")
(add_net "Net-(J0-Pad17)")
(add_net "Net-(J0-Pad18)")
(add_net "Net-(J0-Pad19)")
(add_net "Net-(J0-Pad2)")
(add_net "Net-(J0-Pad20)")
(add_net "Net-(J0-Pad21)")
(add_net "Net-(J0-Pad22)")
(add_net "Net-(J0-Pad23)")
(add_net "Net-(J0-Pad24)")
(add_net "Net-(J0-Pad29)")
(add_net "Net-(J0-Pad3)")
(add_net "Net-(J0-Pad30)")
(add_net "Net-(J0-Pad31)")
(add_net "Net-(J0-Pad32)")
(add_net "Net-(J0-Pad33)")
(add_net "Net-(J0-Pad34)")
(add_net "Net-(J0-Pad35)")
(add_net "Net-(J0-Pad36)")
(add_net "Net-(J0-Pad37)")
(add_net "Net-(J0-Pad38)")
(add_net "Net-(J0-Pad39)")
(add_net "Net-(J0-Pad4)")
(add_net "Net-(J0-Pad40)")
(add_net "Net-(J0-Pad41)")
(add_net "Net-(J0-Pad42)")
(add_net "Net-(J0-Pad43)")
(add_net "Net-(J0-Pad44)")
(add_net "Net-(J0-Pad45)")
(add_net "Net-(J0-Pad46)")
(add_net "Net-(J0-Pad47)")
(add_net "Net-(J0-Pad48)")
(add_net "Net-(J0-Pad49)")
(add_net "Net-(J0-Pad5)")
(add_net "Net-(J0-Pad50)")
(add_net "Net-(J0-Pad6)")
(add_net "Net-(J0-Pad7)")
(add_net "Net-(J0-Pad8)")
(add_net "Net-(J0-Pad9)")
(add_net "Net-(J1-Pad10)")
(add_net "Net-(J1-Pad11)")
(add_net "Net-(J1-Pad12)")
(add_net "Net-(J1-Pad13)")
(add_net "Net-(J1-Pad15)")
(add_net "Net-(J1-Pad16)")
(add_net "Net-(J1-Pad18)")
(add_net "Net-(J1-Pad19)")
(add_net "Net-(J1-Pad21)")
(add_net "Net-(J1-Pad22)")
(add_net "Net-(J1-Pad23)")
(add_net "Net-(J1-Pad24)")
(add_net "Net-(J1-Pad26)")
(add_net "Net-(J1-Pad27)")
(add_net "Net-(J1-Pad28)")
(add_net "Net-(J1-Pad29)")
(add_net "Net-(J1-Pad3)")
(add_net "Net-(J1-Pad31)")
(add_net "Net-(J1-Pad32)")
(add_net "Net-(J1-Pad33)")
(add_net "Net-(J1-Pad35)")
(add_net "Net-(J1-Pad36)")
(add_net "Net-(J1-Pad37)")
(add_net "Net-(J1-Pad38)")
(add_net "Net-(J1-Pad40)")
(add_net "Net-(J1-Pad5)")
(add_net "Net-(J1-Pad7)")
(add_net "Net-(J1-Pad8)")
(add_net "Net-(U0-Pad1)")
(add_net "Net-(U0-Pad11)")
(add_net "Net-(U0-Pad12)")
(add_net "Net-(U0-Pad13)")
(add_net "Net-(U0-Pad14)")
(add_net "Net-(U0-Pad15)")
(add_net "Net-(U0-Pad16)")
(add_net "Net-(U0-Pad17)")
(add_net "Net-(U0-Pad18)")
(add_net "Net-(U0-Pad19)")
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad23)")
(add_net "Net-(U1-Pad26)")
(add_net "Net-(U2-Pad3)")
(add_net "Net-(U2-Pad8)")
(add_net "Net-(U3-Pad1)")
(add_net "Net-(U3-Pad10)")
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(add_net "Net-(U3-Pad3)")
(add_net "Net-(U3-Pad8)")
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net_class Ground ""
(clearance 0.254)
(trace_width 0.8128)
(via_dia 0.762)
(via_drill 0.7112)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(C1-Pad2)")
)
(net_class Power ""
(clearance 0.254)
(trace_width 0.8128)
(via_dia 0.762)
(via_drill 0.7112)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(C1-Pad1)")
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(module Package_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5FB69AA2) (tstamp 5FB68876)
(at 177.8 66.04)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FD4E618)
(fp_text reference U2 (at 3.81 -2.33) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text value 74LS00 (at 3.875 7.75 90) (layer F.SilkS)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.55194 3.06832) (end 2.50444 3.06832) (layer F.SilkS) (width 0.12))
(fp_line (start 1.5494 3.08102) (end 1.5494 3.66776) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.03454 3.683) (end 1.5494 3.683) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.04724 4.35864) (end 2.062479 4.221481) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 2.52476 3.67538) (end 2.52476 3.0734) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.99898 11.72718) (end 1.51384 11.72718) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.01168 12.40282) (end 2.026919 12.265661) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51638 11.1125) (end 2.46888 11.1125) (layer F.SilkS) (width 0.12))
(fp_line (start 2.4892 11.71956) (end 2.4892 11.11758) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51384 11.1252) (end 1.51384 11.71194) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 6.4897) (end 5.19176 6.4897) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 7.16534) (end 5.704839 7.028181) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 5.87502) (end 6.1468 5.87502) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 6.48208) (end 6.16712 5.8801) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 5.88772) (end 5.19176 6.47446) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 13.79982) (end 5.19176 13.79982) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 14.47546) (end 5.704839 14.338301) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 13.18514) (end 6.1468 13.18514) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 13.7922) (end 6.16712 13.19022) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 13.19784) (end 5.19176 13.78458) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 0) (end 2.286 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 0) (end 2.286 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 2.54) (end 1.905 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 1.905 2.54) (end 1.905 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 5.08) (end 2.032 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 5.08) (end 2.032 4.572) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 11.049) (end 2.286 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 7.62) (end 1.143 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 11.049) (end 1.778 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 10.16) (end 1.143 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.573) (end 2.032 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.954) (end 1.143 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 5.842) (end 5.461 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 2.54) (end 6.477 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.842) (end 5.842 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.08) (end 6.477 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 7.747) (end 5.715 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 7.747) (end 5.715 7.366) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 13.081) (end 5.461 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 10.287) (end 6.477 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 13.081) (end 5.842 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 12.7) (end 6.477 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 15.367) (end 5.715 15.367) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 15.367) (end 5.715 14.605) (layer F.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(J0-Pad18)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(U0-Pad19)"))
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(net 29 "Net-(J0-Pad18)"))
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(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
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(module Package_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5FB69841) (tstamp 5FB68898)
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(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
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(fp_line (start 6.45 2.55) (end 5.25 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 2.55) (end 5.25 5.7) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(U3-Pad1)"))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 96 "Net-(U3-Pad8)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(J0-Pad41)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(J0-Pad41)"))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 95 "Net-(U3-Pad3)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(U3-Pad10)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U0-Pad1)"))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(U3-Pad10)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(J0-Pad2)"))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(U2-Pad8)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(U3-Pad1)"))
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(J0-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 93 "Net-(C1-Pad1)"))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB69523) (tstamp 5FB68711)
(at 182.88 62.865 180)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(path /5FB81404)
(fp_text reference C3 (at 1.25 -2.55 180) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text value C (at 1.25 2.55 180) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
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(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
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(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
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(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
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(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 93 "Net-(C1-Pad1)"))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB68DF6) (tstamp 5FB68726)
(at 168.275 62.865 180)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(path /5FB82906)
(fp_text reference C4 (at 1.25 -2.55 180) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text value C (at 1.25 2.55 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
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(net 93 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
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(rotate (xyz 0 0 0))
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(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB68D99) (tstamp 5FB686FC)
(at 188.595 93.98 270)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB849D8)
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(effects (font (size 1 1) (thickness 0.15)))
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(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
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(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
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(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
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(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 93 "Net-(C1-Pad1)"))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
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(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5FB686E7)
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(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
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2020-11-16 03:44:31 +00:00
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "14 A12" (at 20.193 -0.508 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "15 A13" (at 22.733 -0.508 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "13 A11" (at 17.653 -0.508 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "12 A10" (at 15.113 -0.508 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "11 A9" (at 12.319 -0.254 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "10 A8" (at 9.779 -0.254 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_poly (pts (xy 48.895 8.89) (xy 48.895 1.27) (xy -15.875 1.27) (xy -15.875 8.89)) (layer B.Mask) (width 0.15))
(fp_poly (pts (xy 48.895 8.89) (xy 48.895 1.27) (xy -15.875 1.27) (xy -15.875 8.89)) (layer F.Mask) (width 0.15))
(fp_text user "50 +12V" (at -15.494 11.43 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "1 _I/O SELECT" (at -11.303 -2.032 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "3 A1" (at -8.128 -0.127 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "5 A3" (at -3.048 0 45) (layer F.Fab)
Update schematic and create rough PCB layout
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "4 A2" (at -5.588 0.127 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "49 D0" (at -12.446 10.668 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "2 A0" (at -10.668 -0.127 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "8 A6" (at 4.445 0 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "6 A4" (at -0.635 0 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "9 A7" (at 6.985 0 45) (layer F.Fab)
Update schematic and create rough PCB layout
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(effects (font (size 0.762 0.762) (thickness 0.127)))
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Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text user "7 A5" (at 1.905 0 45) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 0.762 0.762) (thickness 0.127)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_line (start -15.875 1.27) (end -16.51 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -15.875 7.62) (end -15.875 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 48.895 1.27) (end 49.53 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 48.895 7.62) (end 48.895 1.27) (layer F.SilkS) (width 0.15))
(pad 50 connect roundrect (at -13.97 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 55 "Net-(J0-Pad50)"))
(pad 49 connect roundrect (at -11.43 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 54 "Net-(J0-Pad49)"))
(pad 48 connect roundrect (at -8.89 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 53 "Net-(J0-Pad48)"))
(pad 47 connect roundrect (at -6.35 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 52 "Net-(J0-Pad47)"))
(pad 46 connect roundrect (at -3.81 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 51 "Net-(J0-Pad46)"))
(pad 45 connect roundrect (at -1.27 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 50 "Net-(J0-Pad45)"))
(pad 44 connect roundrect (at 1.27 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 49 "Net-(J0-Pad44)"))
(pad 43 connect roundrect (at 3.81 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 48 "Net-(J0-Pad43)"))
(pad 42 connect roundrect (at 6.35 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 85 "Net-(J0-Pad42)"))
(pad 41 connect roundrect (at 8.89 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 89 "Net-(J0-Pad41)"))
(pad 40 connect roundrect (at 11.43 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 47 "Net-(J0-Pad40)"))
(pad 39 connect roundrect (at 13.97 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 46 "Net-(J0-Pad39)"))
(pad 37 connect roundrect (at 19.05 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 44 "Net-(J0-Pad37)"))
(pad 38 connect roundrect (at 16.51 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 45 "Net-(J0-Pad38)"))
(pad 36 connect roundrect (at 21.59 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 43 "Net-(J0-Pad36)"))
(pad 35 connect roundrect (at 24.13 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 42 "Net-(J0-Pad35)"))
(pad 34 connect roundrect (at 26.67 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 41 "Net-(J0-Pad34)"))
(pad 33 connect roundrect (at 29.21 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 40 "Net-(J0-Pad33)"))
(pad 32 connect roundrect (at 31.75 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 39 "Net-(J0-Pad32)"))
(pad 31 connect roundrect (at 34.29 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 38 "Net-(J0-Pad31)"))
(pad 30 connect roundrect (at 36.83 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 37 "Net-(J0-Pad30)"))
(pad 29 connect roundrect (at 39.37 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 36 "Net-(J0-Pad29)"))
(pad 28 connect roundrect (at 41.91 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(net 34 "Net-(J0-Pad23)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 27 connect roundrect (at 44.45 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(net 35 "Net-(J0-Pad24)"))
(pad 26 connect roundrect (at 46.99 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
(pad 25 connect roundrect (at 46.99 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 93 "Net-(C1-Pad1)"))
(pad 24 connect roundrect (at 44.45 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(net 35 "Net-(J0-Pad24)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 23 connect roundrect (at 41.91 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(net 34 "Net-(J0-Pad23)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 22 connect roundrect (at 39.37 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 33 "Net-(J0-Pad22)"))
(pad 21 connect roundrect (at 36.83 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 32 "Net-(J0-Pad21)"))
(pad 20 connect roundrect (at 34.29 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 31 "Net-(J0-Pad20)"))
(pad 19 connect roundrect (at 31.75 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 30 "Net-(J0-Pad19)"))
(pad 18 connect roundrect (at 29.21 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 29 "Net-(J0-Pad18)"))
(pad 17 connect roundrect (at 26.67 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 28 "Net-(J0-Pad17)"))
(pad 16 connect roundrect (at 24.13 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 27 "Net-(J0-Pad16)"))
(pad 15 connect roundrect (at 21.59 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 26 "Net-(J0-Pad15)"))
(pad 14 connect roundrect (at 19.05 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 25 "Net-(J0-Pad14)"))
(pad 13 connect roundrect (at 16.51 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 24 "Net-(J0-Pad13)"))
(pad 12 connect roundrect (at 13.97 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 13 "Net-(J0-Pad12)"))
(pad 11 connect roundrect (at 11.43 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 18 "Net-(J0-Pad11)"))
(pad 10 connect roundrect (at 8.89 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 20 "Net-(J0-Pad10)"))
(pad 9 connect roundrect (at 6.35 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 4 "Net-(J0-Pad9)"))
(pad 8 connect roundrect (at 3.81 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 6 "Net-(J0-Pad8)"))
(pad 7 connect roundrect (at 1.27 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 8 "Net-(J0-Pad7)"))
(pad 6 connect roundrect (at -1.27 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 10 "Net-(J0-Pad6)"))
(pad 5 connect roundrect (at -3.81 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 12 "Net-(J0-Pad5)"))
(pad 4 connect roundrect (at -6.35 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 14 "Net-(J0-Pad4)"))
(pad 3 connect roundrect (at -8.89 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 15 "Net-(J0-Pad3)"))
(pad 2 connect roundrect (at -11.43 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 17 "Net-(J0-Pad2)"))
(pad 1 connect roundrect (at -13.97 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 11 "Net-(J0-Pad1)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Connector_PinSocket_2.54mm:PinSocket_2x20_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A433) (tstamp 5FB687FC)
(at 110.49 108.585 180)
(descr "Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 2x20 2.54mm double row")
(path /5FA19C2C)
(fp_text reference J1 (at -1.27 -2.77) (layer F.SilkS)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value Raspberry_Pi_2_3 (at -1.27 51.03) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_line (start -3.81 -1.27) (end 0.27 -1.27) (layer F.Fab) (width 0.1))
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(fp_line (start -3.81 49.53) (end -3.81 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -3.87 -1.33) (end -1.27 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -3.87 -1.33) (end -3.87 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -3.87 49.59) (end 1.33 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -1.33) (end -1.27 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -4.34 -1.8) (end 1.76 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.76 -1.8) (end 1.76 50) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.76 50) (end -4.34 50) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.34 50) (end -4.34 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at -1.27 24.13 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 94 "Net-(C5-Pad1)"))
(pad 2 thru_hole oval (at -2.54 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 3 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 56 "Net-(J1-Pad3)"))
(pad 4 thru_hole oval (at -2.54 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 5 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 57 "Net-(J1-Pad5)"))
(pad 6 thru_hole oval (at -2.54 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 7 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 58 "Net-(J1-Pad7)"))
(pad 8 thru_hole oval (at -2.54 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 59 "Net-(J1-Pad8)"))
(pad 9 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 10 thru_hole oval (at -2.54 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 60 "Net-(J1-Pad10)"))
(pad 11 thru_hole oval (at 0 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 61 "Net-(J1-Pad11)"))
(pad 12 thru_hole oval (at -2.54 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 62 "Net-(J1-Pad12)"))
(pad 13 thru_hole oval (at 0 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 63 "Net-(J1-Pad13)"))
(pad 14 thru_hole oval (at -2.54 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 15 thru_hole oval (at 0 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 64 "Net-(J1-Pad15)"))
(pad 16 thru_hole oval (at -2.54 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 65 "Net-(J1-Pad16)"))
(pad 17 thru_hole oval (at 0 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 94 "Net-(C5-Pad1)"))
(pad 18 thru_hole oval (at -2.54 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 66 "Net-(J1-Pad18)"))
(pad 19 thru_hole oval (at 0 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 67 "Net-(J1-Pad19)"))
(pad 20 thru_hole oval (at -2.54 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 21 thru_hole oval (at 0 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 68 "Net-(J1-Pad21)"))
(pad 22 thru_hole oval (at -2.54 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 69 "Net-(J1-Pad22)"))
(pad 23 thru_hole oval (at 0 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 70 "Net-(J1-Pad23)"))
(pad 24 thru_hole oval (at -2.54 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 71 "Net-(J1-Pad24)"))
(pad 25 thru_hole oval (at 0 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 26 thru_hole oval (at -2.54 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 72 "Net-(J1-Pad26)"))
(pad 27 thru_hole oval (at 0 33.02 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 73 "Net-(J1-Pad27)"))
(pad 28 thru_hole oval (at -2.54 33.02 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 74 "Net-(J1-Pad28)"))
(pad 29 thru_hole oval (at 0 35.56 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 75 "Net-(J1-Pad29)"))
(pad 30 thru_hole oval (at -2.54 35.56 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 31 thru_hole oval (at 0 38.1 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 76 "Net-(J1-Pad31)"))
(pad 32 thru_hole oval (at -2.54 38.1 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 77 "Net-(J1-Pad32)"))
(pad 33 thru_hole oval (at 0 40.64 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 78 "Net-(J1-Pad33)"))
(pad 34 thru_hole oval (at -2.54 40.64 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 35 thru_hole oval (at 0 43.18 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 79 "Net-(J1-Pad35)"))
(pad 36 thru_hole oval (at -2.54 43.18 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 80 "Net-(J1-Pad36)"))
(pad 37 thru_hole oval (at 0 45.72 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 81 "Net-(J1-Pad37)"))
(pad 38 thru_hole oval (at -2.54 45.72 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 82 "Net-(J1-Pad38)"))
(pad 39 thru_hole oval (at 0 48.26 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 40 thru_hole oval (at -2.54 48.26 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 83 "Net-(J1-Pad40)"))
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_2x20_P2.54mm_Vertical.wrl
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB68824)
(at 124.46 99.695 90)
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA15F43)
(fp_text reference U0 (at 3.81 -2.33 90) (layer F.SilkS)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 74LS245 (at 3.81 25.19 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U0-Pad1)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(U0-Pad11)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(J0-Pad49)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(U0-Pad12)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 "Net-(J0-Pad48)"))
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(U0-Pad13)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(J0-Pad47)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(U0-Pad14)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 "Net-(J0-Pad46)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 50 "Net-(J0-Pad45)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 "Net-(J0-Pad44)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(J0-Pad43)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad18)"))
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(J0-Pad42)"))
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(U0-Pad19)"))
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-28_W15.24mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB68854)
(at 185.42 87.63 270)
(descr "28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil")
(path /5FA0EF8B)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text reference U1 (at 7.62 -2.33 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 2764 (at 7.62 35.35 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 -1.27) (end 14.985 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 34.29) (end 0.255 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 34.29) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 34.35) (end 14.08 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 34.35) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 34.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 34.55) (end 16.3 34.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.3 34.55) (end 16.3 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.3 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 7.62 16.51 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 15 thru_hole oval (at 15.24 33.02 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 1 "Net-(U0-Pad15)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(U1-Pad2)"))
(pad 16 thru_hole oval (at 15.24 30.48 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 3 "Net-(U0-Pad14)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(J0-Pad9)"))
(pad 17 thru_hole oval (at 15.24 27.94 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 5 "Net-(U0-Pad13)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(J0-Pad8)"))
(pad 18 thru_hole oval (at 15.24 25.4 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 7 "Net-(U0-Pad12)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 5 thru_hole oval (at 0 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(J0-Pad7)"))
(pad 19 thru_hole oval (at 15.24 22.86 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 9 "Net-(U0-Pad11)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 6 thru_hole oval (at 0 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(J0-Pad6)"))
(pad 20 thru_hole oval (at 15.24 20.32 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J0-Pad1)"))
(pad 7 thru_hole oval (at 0 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 "Net-(J0-Pad5)"))
(pad 21 thru_hole oval (at 15.24 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(J0-Pad12)"))
(pad 8 thru_hole oval (at 0 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(J0-Pad4)"))
(pad 22 thru_hole oval (at 15.24 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J0-Pad1)"))
(pad 9 thru_hole oval (at 0 20.32 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(J0-Pad3)"))
(pad 23 thru_hole oval (at 15.24 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(U1-Pad23)"))
(pad 10 thru_hole oval (at 0 22.86 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(J0-Pad2)"))
(pad 24 thru_hole oval (at 15.24 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(J0-Pad11)"))
(pad 11 thru_hole oval (at 0 25.4 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad18)"))
(pad 25 thru_hole oval (at 15.24 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(J0-Pad10)"))
(pad 12 thru_hole oval (at 0 27.94 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 26 thru_hole oval (at 15.24 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 "Net-(U1-Pad26)"))
(pad 13 thru_hole oval (at 0 30.48 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 27 thru_hole oval (at 15.24 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 14 thru_hole oval (at 0 33.02 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 28 thru_hole oval (at 15.24 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-28_W15.24mm.wrl
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB688C0)
(at 124.46 86.36 90)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA19168)
(fp_text reference U4 (at 3.81 -2.33 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 74LVC245 (at 3.81 25.19 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 94 "Net-(C5-Pad1)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 95 "Net-(U3-Pad3)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(U0-Pad11)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 58 "Net-(J1-Pad7)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(U0-Pad12)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 61 "Net-(J1-Pad11)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(U0-Pad13)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 63 "Net-(J1-Pad13)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(U0-Pad14)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 64 "Net-(J1-Pad15)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 67 "Net-(J1-Pad19)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 68 "Net-(J1-Pad21)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 70 "Net-(J1-Pad23)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad18)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 75 "Net-(J1-Pad29)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB688E8)
(at 124.46 71.755 90)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA1EB22)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text reference U5 (at 3.81 -2.33 90) (layer F.SilkS)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 74LVC374 (at 3.81 25.19 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 96 "Net-(U3-Pad8)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 "Net-(J1-Pad31)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 83 "Net-(J1-Pad40)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 19 "Net-(U0-Pad18)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(U0-Pad14)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(U0-Pad13)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 78 "Net-(J1-Pad33)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 82 "Net-(J1-Pad38)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 79 "Net-(J1-Pad35)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 80 "Net-(J1-Pad36)"))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(U0-Pad12)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(U0-Pad11)"))
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(J1-Pad37)"))
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 "Net-(J1-Pad32)"))
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 94 "Net-(C5-Pad1)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(gr_line (start 191.77 111.125) (end 191.77 58.42) (layer Edge.Cuts) (width 0.05) (tstamp 5FB6D31C))
(gr_text "74LVC374 Output Level Shifter" (at 136.144 67.945) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "74LVC245 Input Level Shifter" (at 135.89 82.677) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "74LS245 Data Bus Buffer" (at 135.636 96.012) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "Attach Raspberry Pi Zero W facing outward from card" (at 115.951 84.709 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_line (start 164.6355 68.718) (end 164.6355 67.794) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 165.633 74.7135) (xy 165.234 74.8815) (xy 164.7195 75.3855) (xy 164.6355 76.131)) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 169.2555 71.385) (xy 169.1715 72.1305) (xy 168.657 72.6345) (xy 168.258 72.8025)) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 168.258 72.8025) (xy 167.859 72.6345) (xy 167.3445 72.1305) (xy 167.2605 71.385)) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 68.424) (end 164.142 66.744) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 68.424) (end 164.142 68.424) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 164.6355 67.794) (xy 165.213 68.0985) (xy 166.053 68.0985) (xy 166.6305 67.794)) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.2605 78.798) (end 167.2605 79.722) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.258 76.425) (end 168.258 77.349) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 79.092) (end 169.749 80.772) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 73.758) (end 165.633 73.758) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 167.2605 79.722) (xy 167.838 79.4175) (xy 168.678 79.4175) (xy 169.2555 79.722)) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 168.258 77.3805) (xy 167.859 77.5485) (xy 167.3445 78.0525) (xy 167.2605 78.798)) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 78.105) (end 165.108 78.105) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.733 81.759) (end 167.733 79.512) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 167.2605 70.461) (xy 167.838 70.7655) (xy 168.678 70.7655) (xy 169.2555 70.461)) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 65.757) (end 166.158 65.757) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.158 79.092) (end 166.158 76.845) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 81.759) (end 167.733 81.759) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 68.424) (end 167.733 68.424) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.2605 71.385) (end 167.2605 70.461) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 76.425) (end 164.142 78.105) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.6355 76.131) (end 164.6355 77.055) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 71.091) (end 165.633 71.091) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 66.744) (end 165.108 66.744) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 169.2555 78.798) (xy 169.1715 78.0525) (xy 168.657 77.5485) (xy 168.258 77.3805)) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 80.772) (end 168.783 80.772) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.733 68.424) (end 167.733 70.671) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.108 66.744) (end 165.108 68.004) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.633 71.091) (end 165.633 70.167) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 166.6305 68.718) (xy 166.5465 69.4635) (xy 166.032 69.9675) (xy 165.633 70.1355)) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 71.091) (end 169.749 71.091) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.258 73.758) (end 168.258 72.834) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.783 69.411) (end 168.783 70.671) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 79.092) (end 166.158 79.092) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 165.633 70.1355) (xy 165.234 69.9675) (xy 164.7195 69.4635) (xy 164.6355 68.718)) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.633 73.758) (end 165.633 74.682) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 164.6355 77.055) (xy 165.213 76.7505) (xy 166.053 76.7505) (xy 166.6305 77.055)) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 76.425) (end 168.258 76.425) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 79.092) (end 169.749 79.092) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.2555 79.722) (end 169.2555 78.798) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.6305 67.794) (end 166.6305 68.718) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 71.091) (end 169.749 69.411) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 69.411) (end 168.783 69.411) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 166.6305 76.131) (xy 166.5465 75.3855) (xy 166.032 74.8815) (xy 165.633 74.7135)) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 76.425) (end 164.142 76.425) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.6305 77.055) (end 166.6305 76.131) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.2555 70.461) (end 169.2555 71.385) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.108 78.105) (end 165.108 76.845) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 73.758) (end 168.258 73.758) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.158 65.757) (end 166.158 68.004) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.783 80.772) (end 168.783 79.512) (layer Dwgs.User) (width 0.14))
(gr_text "27C64 EPROM\nFirmware at $Cn00 - $CnFF\nWhere n = slot number" (at 160.02 95.25) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify left))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(gr_line (start 123.19 119.38) (end 186.69 119.38) (layer Edge.Cuts) (width 0.05) (tstamp 5FB6A4EB))
(gr_line (start 122.555 118.745) (end 123.19 119.38) (layer Edge.Cuts) (width 0.05))
(gr_line (start 122.555 111.76) (end 122.555 118.745) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.95 111.76) (end 122.555 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.315 111.125) (end 107.95 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.315 58.42) (end 107.315 111.125) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.95 57.785) (end 107.315 58.42) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.135 57.785) (end 107.95 57.785) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.77 58.42) (end 191.135 57.785) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.135 111.76) (end 191.77 111.125) (layer Edge.Cuts) (width 0.05))
(gr_line (start 187.325 111.76) (end 191.135 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 187.325 118.745) (end 187.325 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 186.69 119.38) (end 187.325 118.745) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.77 57.785) (end 191.77 111.76) (layer Dwgs.User) (width 0.15))
(gr_line (start 107.315 57.785) (end 213.995 57.785) (layer Dwgs.User) (width 0.15))
(gr_line (start 107.315 113.03) (end 107.315 55.245) (layer Dwgs.User) (width 0.15))
(gr_line (start 121.285 111.76) (end 101.6 111.76) (layer Dwgs.User) (width 0.15))
(gr_line (start 189.23 111.76) (end 207.645 111.76) (layer Dwgs.User) (width 0.15))
(gr_line (start 188.595 111.76) (end 189.865 111.76) (layer Dwgs.User) (width 0.15))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
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