forked from Apple-2-HW/AppleIISd
289 lines
7.6 KiB
VHDL
289 lines
7.6 KiB
VHDL
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-- Copyright (c) 1995-2003 Xilinx, Inc.
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-- All Right Reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 6.3.03i
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-- \ \ Application :
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-- / / Filename : address_decoder.vhf
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-- /___/ /\ Timestamp : 05/11/2017 02:05:37
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-- \ \ / \
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-- \___\/\___\
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--
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--Command:
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--Design Name: FD_MXILINX_address_decoder
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--
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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-- synopsys translate_off
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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-- synopsys translate_on
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entity FD_MXILINX_address_decoder is
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port ( C : in std_logic;
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D : in std_logic;
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Q : out std_logic);
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end FD_MXILINX_address_decoder;
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architecture BEHAVIORAL of FD_MXILINX_address_decoder is
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attribute BOX_TYPE : string ;
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signal XLXN_4 : std_logic;
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component GND
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port ( G : out std_logic);
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end component;
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attribute BOX_TYPE of GND : component is "BLACK_BOX";
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component FDCP
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port ( C : in std_logic;
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CLR : in std_logic;
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D : in std_logic;
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PRE : in std_logic;
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Q : out std_logic);
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end component;
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attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
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begin
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I_36_43 : GND
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port map (G=>XLXN_4);
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U0 : FDCP
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port map (C=>C,
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CLR=>XLXN_4,
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D=>D,
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PRE=>XLXN_4,
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Q=>Q);
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end BEHAVIORAL;
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--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2003 Xilinx, Inc.
|
|
-- All Right Reserved.
|
|
--------------------------------------------------------------------------------
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|
-- ____ ____
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|
-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 6.3.03i
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-- \ \ Application :
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-- / / Filename : address_decoder.vhf
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-- /___/ /\ Timestamp : 05/11/2017 02:05:37
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-- \ \ / \
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-- \___\/\___\
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--
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--Command:
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--Design Name: FDRS_MXILINX_address_decoder
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--
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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-- synopsys translate_off
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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-- synopsys translate_on
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entity FDRS_MXILINX_address_decoder is
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port ( C : in std_logic;
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D : in std_logic;
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R : in std_logic;
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S : in std_logic;
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Q : out std_logic);
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end FDRS_MXILINX_address_decoder;
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architecture BEHAVIORAL of FDRS_MXILINX_address_decoder is
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attribute BOX_TYPE : string ;
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attribute HU_SET : string ;
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signal XLXN_6 : std_logic;
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signal XLXN_7 : std_logic;
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signal XLXN_8 : std_logic;
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component AND2B1
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port ( I0 : in std_logic;
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I1 : in std_logic;
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O : out std_logic);
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end component;
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attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
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component OR2
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port ( I0 : in std_logic;
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I1 : in std_logic;
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O : out std_logic);
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end component;
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attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
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component FD_MXILINX_address_decoder
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port ( C : in std_logic;
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D : in std_logic;
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Q : out std_logic);
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end component;
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attribute HU_SET of U0 : label is "U0_0";
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begin
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I_36_112 : AND2B1
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port map (I0=>R,
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I1=>S,
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O=>XLXN_6);
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I_36_113 : AND2B1
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port map (I0=>R,
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I1=>D,
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O=>XLXN_8);
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I_36_120 : OR2
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port map (I0=>XLXN_6,
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I1=>XLXN_8,
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O=>XLXN_7);
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U0 : FD_MXILINX_address_decoder
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port map (C=>C,
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D=>XLXN_7,
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Q=>Q);
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end BEHAVIORAL;
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--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2003 Xilinx, Inc.
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-- All Right Reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 6.3.03i
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-- \ \ Application :
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-- / / Filename : address_decoder.vhf
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-- /___/ /\ Timestamp : 05/11/2017 02:05:37
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-- \ \ / \
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-- \___\/\___\
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--
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--Command:
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--Design Name: address_decoder
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--
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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-- synopsys translate_off
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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-- synopsys translate_on
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entity address_decoder is
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port ( A8 : in std_logic;
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A9 : in std_logic;
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A10 : in std_logic;
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CLK : in std_logic;
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NIO_SEL : in std_logic;
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NIO_STB : in std_logic;
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A8_B : out std_logic;
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A9_B : out std_logic;
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A10_B : out std_logic;
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NOE : out std_logic);
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end address_decoder;
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architecture BEHAVIORAL of address_decoder is
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attribute BOX_TYPE : string ;
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attribute HU_SET : string ;
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signal XLXN_4 : std_logic;
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signal XLXN_10 : std_logic;
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signal XLXN_11 : std_logic;
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signal XLXN_14 : std_logic;
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signal XLXN_19 : std_logic;
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component NAND2
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port ( I0 : in std_logic;
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I1 : in std_logic;
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O : out std_logic);
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end component;
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attribute BOX_TYPE of NAND2 : component is "BLACK_BOX";
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component FDRS_MXILINX_address_decoder
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port ( C : in std_logic;
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D : in std_logic;
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R : in std_logic;
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S : in std_logic;
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Q : out std_logic);
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end component;
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component VCC
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port ( P : out std_logic);
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end component;
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attribute BOX_TYPE of VCC : component is "BLACK_BOX";
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component AND2
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port ( I0 : in std_logic;
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I1 : in std_logic;
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O : out std_logic);
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end component;
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attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
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component INV
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port ( I : in std_logic;
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O : out std_logic);
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end component;
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attribute BOX_TYPE of INV : component is "BLACK_BOX";
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component AND4B1
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port ( I0 : in std_logic;
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I1 : in std_logic;
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I2 : in std_logic;
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I3 : in std_logic;
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O : out std_logic);
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end component;
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attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
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attribute HU_SET of XLXI_16 : label is "XLXI_16_1";
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begin
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XLXI_13 : NAND2
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port map (I0=>NIO_SEL,
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I1=>NIO_STB,
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O=>XLXN_4);
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XLXI_14 : NAND2
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port map (I0=>XLXN_11,
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I1=>XLXN_4,
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O=>NOE);
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XLXI_16 : FDRS_MXILINX_address_decoder
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port map (C=>CLK,
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D=>XLXN_14,
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R=>XLXN_10,
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S=>XLXN_19,
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Q=>XLXN_11);
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XLXI_17 : VCC
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port map (P=>XLXN_14);
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XLXI_18 : AND2
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port map (I0=>A10,
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I1=>NIO_SEL,
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O=>A10_B);
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XLXI_19 : AND2
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port map (I0=>A9,
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I1=>NIO_SEL,
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O=>A9_B);
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XLXI_20 : AND2
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port map (I0=>A8,
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I1=>NIO_SEL,
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O=>A8_B);
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XLXI_22 : INV
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port map (I=>NIO_SEL,
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O=>XLXN_19);
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XLXI_23 : AND4B1
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port map (I0=>NIO_STB,
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I1=>A10,
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I2=>A9,
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I3=>A8,
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O=>XLXN_10);
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end BEHAVIORAL;
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