GR8RAM/cpld/output_files/GR8RAM.map.summary

Analysis & Synthesis Status : Successful - Fri Oct 18 15:01:54 2019
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX7000S
Total macrocells : 105
Total pins : 61
New PLD revision For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502. 2019-10-18 19:07:38 +00:00			`Analysis & Synthesis Status : Successful - Fri Oct 18 15:01:54 2019`
			`Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition`
CPLD firmware compiles 2019-09-01 02:55:04 +00:00			`Revision Name : GR8RAM`
			`Top-level Entity Name : GR8RAM`
			`Family : MAX7000S`
24-bit counter, CAS fixed 2019-10-12 00:34:51 +00:00			`Total macrocells : 105`
Pipelined addition 2019-09-05 01:45:56 +00:00			`Total pins : 61`