forked from Apple-2-HW/GR8RAM
idk
This commit is contained in:
parent
e5da11855d
commit
a444cc31aa
37
Documentation/Flash Map
Normal file
37
Documentation/Flash Map
Normal file
@ -0,0 +1,37 @@
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GR8RAM/LibraryCard flash memory map
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-----------------------------
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FF FFFF | |
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.. .... | reserved (12 MB) |
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40 0000 | |
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-----------------------------
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3F FFFF | |
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.. .... | firmware 3 (1 MB) |
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30 0000 | |
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-----------------------------
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2F FFFF | |
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.. .... | firmware 2 (1 MB) |
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20 0000 | |
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-----------------------------
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1F FFFF | |
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.. .... | firmware 1 (1 MB) |
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10 0000 | |
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-----------------------------
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0F FFFF | |
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.. .... | firmware 0 (1 MB) |
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00 0000 | |
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-----------------------------
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Firmware area map (X == 0, 1, 2, or 3)
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-----------------------------
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XF FFFF | |
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.. .... | reserved (510 kB) |
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X8 0800 | |
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-----------------------------
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X8 07FF | |
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.. .... | IOSEL area (2 kB) |
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X8 0000 | |
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-----------------------------
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X7 FFFF | |
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.. .... | 256x IOSTRB area (512 kB) |
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X0 0000 | |
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-----------------------------
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140
Documentation/Initialization Sequence
Normal file
140
Documentation/Initialization Sequence
Normal file
@ -0,0 +1,140 @@
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Init sequence
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Init State SDRAM Flash Other
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--------------------------------------------------------------------------------
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$000000-$0FFFBF Wait for Vcc Wait for Vcc
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$000000 NOP CKE /CS hi, CLK lo
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...
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$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFFAF NOP CKE /CS lo, CLK lo
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$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03)
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$0FFFB0 PC all CLK lo, MOSI 0 (b7)
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$0FFFB1 NOP CKE CLK hi
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$0FFFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFB3 NOP CKE CLK hi
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$0FFFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFB5 NOP CKE CLK hi
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$0FFFB6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFB7 NOP CKE CLK hi
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$0FFFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFB9 NOP CKE CLK hi
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$0FFFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFBB NOP CKE CLK hi
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$0FFFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFFBD NOP CKE CLK hi
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$0FFFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFFBF NOP CKE CLK hi
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$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000)
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$0FFFC0 Load mode CLK lo, MOSI 0 (b23)
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$0FFFC1 NOP CKE CLK hi
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$0FFFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFFC3 NOP CKE CLK hi
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$0FFFC4 AREF CLK lo, MOSI Firmware[1] (b21)
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$0FFFC5 NOP CKE CLK hi
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$0FFFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFFC7 NOP CKE CLK hi
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$0FFFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFFC9 NOP CKE CLK hi
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$0FFFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFFCB NOP CKE CLK hi
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$0FFFCC AREF CLK lo, MOSI 0 (b17)
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$0FFFCD NOP CKE CLK hi
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$0FFFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFFCF NOP CKE CLK hi
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$0FFFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFFD1 NOP CKE CLK hi
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$0FFFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFFD3 NOP CKE CLK hi
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$0FFFD4 AREF CLK lo, MOSI 0 (b13)
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$0FFFD5 NOP CKE CLK hi
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$0FFFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFFD7 NOP CKE CLK hi
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$0FFFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFFD9 NOP CKE CLK hi
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$0FFFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFFDB NOP CKE CLK hi
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$0FFFDC AREF CLK lo, MOSI 0 (b9)
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$0FFFDD NOP CKE CLK hi
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$0FFFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFFDF NOP CKE CLK hi
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$0FFFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFE1 NOP CKE CLK hi
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$0FFFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFE3 NOP CKE CLK hi
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$0FFFE4 AREF CLK lo, MOSI 0 (b5)
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$0FFFE5 NOP CKE CLK hi
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$0FFFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFE7 NOP CKE CLK hi
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$0FFFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFE9 NOP CKE CLK hi
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$0FFFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFEB NOP CKE CLK hi
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$0FFFEC AREF CLK lo, MOSI 0 (b1)
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$0FFFED NOP CKE CLK hi
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$0FFFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFFEF NOP CKE CLK hi
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$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks
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$0FFFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFFF1 NOP CKE CLK hi
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$0FFFF2 NOP CKE CLK lo
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$0FFFF3 NOP CKE CLK hi
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$0FFFF4 AREF CLK lo
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$0FFFF5 NOP CKE CLK hi
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$0FFFF6 NOP CKE CLK lo
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$0FFFF7 NOP CKE CLK hi
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$0FFFF8 NOP CKE CLK lo
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$0FFFF9 NOP CKE CLK hi
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$0FFFFA NOP CKE CLK lo
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$0FFFFB NOP CKE CLK hi
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$0FFFFC AREF CLK lo
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$0FFFFD NOP CKE CLK hi
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$0FFFFE NOP CKE CLK lo
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$0FFFFF NOP CKE CLK hi
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Write ROM data Shift in read data
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$100000 NOP CKE CLK lo
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$100001 NOP CKE CLK hi, get b7:6 of $000000
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$100002 NOP CKE CLK lo
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$100003 NOP CKE CLK hi, get b5:4 of $000000
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$100004 AREF CLK lo
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$100005 NOP CKE CLK hi, get b3:2 of $000000
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$100006 ACT CLK lo
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$100007 NOP CKE CLK hi, get b1:0 of $000000
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$100008 WR AP CLK lo
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$100009 NOP CKE CLK hi, get b7:6 of $000001
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$10000A NOP CKE CLK lo
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$10000B NOP CKE CLK hi, get b5:4 of $000001
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$10000C AREF CLK lo
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$10000D NOP CKE CLK hi, get b3:2 of $000001
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$10000E ACT CLK lo
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$10000F NOP CKE CLK hi, get b1:0 of $000001
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...
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$507FF0 WR AP CLK lo
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$503FF1 NOP CKE CLK hi, get b7:6 of $0807FE
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$503FF2 NOP CKE CLK lo
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$503FF3 NOP CKE CLK hi, get b5:4 of $0807FE
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$503FF4 AREF CLK lo
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$503FF5 NOP CKE CLK hi, get b3:2 of $0807FE
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$503FF6 ACT CLK lo
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$503FF7 NOP CKE CLK hi, get b1:0 of $0807FE
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$503FF8 WR AP CLK lo
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$503FF9 NOP CKE CLK hi, get b7:6 of $0807FF
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$503FFA NOP CKE CLK lo
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$503FFB NOP CKE CLK hi, get b5:4 of $0807FF
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$503FFC AREF CLK lo
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$503FFD NOP CKE CLK hi, get b3:2 of $0807FF
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$503FFE ACT CLK lo
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$503FFF NOP CKE CLK hi, get b1:0 of $0807FF
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$504000 WR AP CLK lo, /CS hi
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$504001 NOP CKE CLK lo
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...
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$50400F NOP CKE CLK lo
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$504010 NOP CKE SDRAMActv <= InitActv && ~InitInterrupted
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...
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$5F5E0F flip 1hz, wrap
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@ -1,106 +0,0 @@
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Addr Slinky GR8RAM
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0 RAMAddrL RAMAddrL
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1 RAMAddrM RAMAddrM
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2 RAMAddrH RAMAddrH
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3 Data Data
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4 AppleAddrL (TimerDMAEN)
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5 AppleAddrH (TimerDMAEN)
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6 DMALengthL (TimerDMAEN)
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7 DMALengthH (TimerDMAEN)
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8 Magic (reads 0x57, write command sequence)
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9 Ctl (TimerDMAEN)
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A Readout
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B
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C
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D
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E BankH (ExtBankEN)
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F Bank BankL
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Magic commands
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Set readout
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4 tick bytes
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config byte
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Write hidden control register
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Write IRQ period H
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Write IRQ period L
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Hidden control register
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(1) Enable timer & dma
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(1) enable extended bank
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(2) reserved
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(1) DR shift data bit
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(1) write '1' to shift bit into DR
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(1) write '1' to erase settings
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(1) write '1' to program settings
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Control register (TimerDMAEN)
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(1) Timer IRQ enabled
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(1) Timer IRQ flag
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(1) reserved
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(1) INTout
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(1) DMA Compare result
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(1) RAMAddrHH
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(2) DMA command (always reads 00)
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00 = no operation
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01 = read
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10 = write
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11 = compare
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Configuration Bits
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(1) Config word valid
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1 = invalid
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0 = valid
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(1) Slinky/RamFactor
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1 = RamFactor
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0 = Slinky
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(2) Driver number (BankCX) (0-3)
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(3) Capacity (invert bottom bit, then decode to get mask)
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111 = 011111 = 08192 kB
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110 = 111111 = 16384 kB
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101 = 000111 = 02048 kB
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100 = 001111 = 04096 kB
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011 = 000001 = 00512 kB
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010 = 000011 = 01024 kB
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001 = 000000 = 00256 kB
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000 = reserved
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Flash Memory Map (2 MB)
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-----------------------------
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3FF | |
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... | GS/OS Recovery (1.5 MB) |
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200 | |
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-----------------------------
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1FF | |
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... | ProDOS Recovery (256 kB) |
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180 | |
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-----------------------------
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07F | |
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... | Driver 3 (64 kB) |
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060 | |
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-----------------------------
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05F | |
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... | Driver 2 (64 kB) |
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040 | |
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-----------------------------
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03F | |
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... | Driver 1 (64 kB) |
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020 | |
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-----------------------------
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01F | |
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... | Driver 0 (64 kB) |
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000 | |
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|----------------------------
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SDRAM Memory Map (32 MB)
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1FFFFFF:1800000 RAMWorks copy
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17FFFFF:17F0000 64 kB main RAM copy
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17EFFFF:17E0000 64 kB driver (32 2048 byte banks)
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17DFFFF:1010000 Shared Memory (8064 kB)
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0FFFFFF:0800000 Extended RamFactor
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07FFFFF:0000000 8 MB RamFactor
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@ -1,30 +1,44 @@
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GR8RAM/LibraryCard Slinky memory map
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GR8RAM/LibraryCard Slinky RAM memory map
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-----------------------------
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1 FF FFFF | |
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. .. .... | LibCrd Sect. Cache (8 MB) |
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. .. .... | LibCrd sect. cache (8 MB) |
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1 80 0000 | |
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-----------------------------
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1 7F FFFF | |
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. .. .... | reserved (6 MB) |
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1 20 0000 | |
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-----------------------------
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1 1F FFFF | |
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. .. .... | LibCrd registers (1 MB) |
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1 70 0000 | |
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-----------------------------
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1 6F FFFF | |
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. .. .... | reserved (5.9375 MB) |
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1 11 0000 | |
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-----------------------------
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1 10 FFFF | |
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. .. .... | RAM shadow (64 kB) |
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1 10 0000 | |
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-----------------------------
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1 0F FFFF | |
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. .. .... | 256x IOSTRB area (512 kB) |
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1 08 0000 | |
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-----------------------------
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1 07 FFFF | |
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. .. .... | 256x IOSEL area (512 kB) |
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. .. .... | firmware (1 MB) |
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1 00 0000 | |
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-----------------------------
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0 FF 0000 | |
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. .. .... | RAMFactor Memory (16 MB) |
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0 FF FFFF | |
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. .. .... | RAMFactor RAM (16 MB) |
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0 00 0000 | |
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-----------------------------
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Firmware area map (X == 0, 1, 2, or 3)
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-----------------------------
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1 0F FFFF | |
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. .. .... | reserved (510 kB) |
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1 08 0800 | |
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-----------------------------
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1 08 07FF | |
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. .. .... | IOSEL area (2 kB) |
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1 08 0000 | |
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-----------------------------
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1 07 FFFF | |
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. .. .... | 256x IOSTRB area (512 kB) |
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1 00 0000 | |
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-----------------------------
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Library Card register space
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-----------------------------
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@ -33,18 +47,18 @@ Library Card register space
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1 74 0000 | |
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-----------------------------
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1 73 FFFF | |
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. .. .... | Response B (64 kB) |
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. .. .... | response B (64 kB) |
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1 73 0000 | |
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-----------------------------
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1 72 FFFF | |
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. .. .... | Command B (64 kB) |
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. .. .... | command B (64 kB) |
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1 72 0000 | |
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-----------------------------
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1 71 FFFF | |
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. .. .... | Response A (64 kB) |
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. .. .... | response A (64 kB) |
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1 71 0000 | |
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-----------------------------
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1 70 FFFF | |
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. .. .... | Command A (64 kB) |
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. .. .... | command A (64 kB) |
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1 70 0000 | |
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-----------------------------
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45
Documentation/Registers
Normal file
45
Documentation/Registers
Normal file
@ -0,0 +1,45 @@
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Addr Slinky GR8RAM TimeMachine
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$0 RAddrL RAddrL RAddrL
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$1 RAddrM RAddrM RAddrM
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$2 RAddrH RAddrH RAddrH
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$3 RData RData RData
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$4 DMAAddrL
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$5 DMAAddrH
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$6
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$7
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$8
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$9
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$A
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$B
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$C
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$D Readin/out Readin/out
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$E Command Command
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$F Bank Bank Bank
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GR8RAM commands
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CmdNum Description Argument
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$00 SetReadinout RiNum/RoNum
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$EF CFGPrgmEN don't care
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$EE CFGEraseEN don't care
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GR8RAM Readin
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RiNum Description Data
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$10 SPI flash { MOSI(1), X(6), CS(1) }
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$11 SPI flash + clk pulse { MOSI(1), X(6), CS(1) }
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$13 CFG flash + clk pulse { CFGDin(1), X(7) }
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$20 Mode { RF/nSlinky(1), X(4), Size(3) }
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$21 RAddrHH { X(7), RAddr[24](1) }
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GR8RAM Readout
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RoNum Description
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$00 Magic $C1
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$01 Card ID $00
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$10 SPI flash { MISO(1), X(7) }
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$20 Mode { RF/nSlinky(1), X(4), Size(3) }
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TimeMachine commands
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$XX DMA into Apple RAM Length
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$XX DMA into Slinky RAM Length
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$XX DMA into Apple RAM Length-256
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$XX DMA into Slinky RAM Length-256
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7
Documentation/Settings
Normal file
7
Documentation/Settings
Normal file
@ -0,0 +1,7 @@
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GR8RAM Settings (not applicable to Library Card!)
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Settings[15] SetValid (1 = invalid, 0 = valid)
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Settings[14] SetFW[1] (1 = RAMFactor, 0 = Slinky)
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Settings[13] SetFW[0]
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Settings[12] SetLim8M
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Settings[11:0] Reserved
|
11107
GR8RAM.kicad_pcb
11107
GR8RAM.kicad_pcb
File diff suppressed because it is too large
Load Diff
149
GR8RAM.sch
149
GR8RAM.sch
@ -14,7 +14,7 @@ Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 500 600 500 150
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S 750 650 500 150
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U 5D4D21A0
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F0 "Docs" 50
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F1 "Docs.sch" 50
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@ -2497,18 +2497,6 @@ F 4 "C7955" H 3800 1050 50 0001 C CNN "LCSC Part"
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$EndComp
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Text Label 900 6550 2 50 ~ 0
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FD2
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$Comp
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L Device:R_Small R19
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U 1 1 5FFDC1D7
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P 8300 5000
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F 0 "R19" V 8250 5000 50 0000 C BNN
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F 1 "1k" V 8350 5000 50 0000 C TNN
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F 2 "stdpads:R_0603" H 8300 5000 50 0001 C CNN
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F 3 "~" H 8300 5000 50 0001 C CNN
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F 4 "C21190" H 8300 5000 50 0001 C CNN "LCSC Part"
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1 8300 5000
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0 1 1 0
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$EndComp
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Connection ~ 7800 5000
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Wire Wire Line
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7400 4650 7400 4700
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@ -2541,10 +2529,10 @@ L Device:R_Small R18
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U 1 1 617DE3BC
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||||
P 7050 4750
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||||
F 0 "R18" H 7100 4800 50 0000 L CNN
|
||||
F 1 "22k" H 7100 4700 50 0000 L CNN
|
||||
F 1 "100k" H 7100 4700 50 0000 L CNN
|
||||
F 2 "stdpads:R_0603" H 7050 4750 50 0001 C CNN
|
||||
F 3 "~" H 7050 4750 50 0001 C CNN
|
||||
F 4 "C31850" H 7050 4750 50 0001 C CNN "LCSC Part"
|
||||
F 4 "C25803" H 7050 4750 50 0001 C CNN "LCSC Part"
|
||||
1 7050 4750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
@ -3357,18 +3345,6 @@ F 4 "C23253" H 4200 1300 50 0001 C CNN "LCSC Part"
|
||||
1 4200 1300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C39
|
||||
U 1 1 5FFA952A
|
||||
P 4750 1300
|
||||
F 0 "C39" H 4842 1346 50 0000 L CNN
|
||||
F 1 "1n" H 4842 1255 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 4750 1300 50 0001 C CNN
|
||||
F 3 "~" H 4750 1300 50 0001 C CNN
|
||||
F 4 "C1588" H 4750 1300 50 0001 C CNN "LCSC Part"
|
||||
1 4750 1300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4100 1150 4750 1150
|
||||
Wire Wire Line
|
||||
@ -3414,18 +3390,6 @@ Wire Wire Line
|
||||
Connection ~ 4350 1450
|
||||
Wire Wire Line
|
||||
4350 1200 4350 950
|
||||
$Comp
|
||||
L Device:C_Small C38
|
||||
U 1 1 5FB5B1B9
|
||||
P 4350 1300
|
||||
F 0 "C38" H 4442 1346 50 0000 L CNN
|
||||
F 1 "22n" H 4442 1255 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 4350 1300 50 0001 C CNN
|
||||
F 3 "~" H 4350 1300 50 0001 C CNN
|
||||
F 4 "C21122" H 4350 1300 50 0001 C CNN "LCSC Part"
|
||||
1 4350 1300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4350 1450 4350 1400
|
||||
$Comp
|
||||
@ -3473,23 +3437,6 @@ Text Notes 5000 1150 2 50 ~ 0
|
||||
Wire Wire Line
|
||||
3300 1050 3500 1050
|
||||
$Comp
|
||||
L Device:C_Small C41
|
||||
U 1 1 5FF9336A
|
||||
P 7050 5200
|
||||
F 0 "C41" H 7142 5246 50 0000 L CNN
|
||||
F 1 "22n" H 7142 5155 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 7050 5200 50 0001 C CNN
|
||||
F 3 "~" H 7050 5200 50 0001 C CNN
|
||||
F 4 "C21122" H 7050 5200 50 0001 C CNN "LCSC Part"
|
||||
1 7050 5200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6750 5300 7050 5300
|
||||
Wire Wire Line
|
||||
7050 5300 7400 5300
|
||||
Connection ~ 7050 5300
|
||||
$Comp
|
||||
L Device:R_Small R31
|
||||
U 1 1 60BD9796
|
||||
P 1700 6550
|
||||
@ -3906,16 +3853,6 @@ Wire Wire Line
|
||||
3400 4350 4150 4350
|
||||
Wire Wire Line
|
||||
3400 4250 4150 4250
|
||||
Wire Bus Line
|
||||
600 3750 600 4650
|
||||
Wire Bus Line
|
||||
1800 4650 1800 5450
|
||||
Wire Bus Line
|
||||
3300 1950 3300 4550
|
||||
Wire Bus Line
|
||||
3300 4850 3300 5550
|
||||
Wire Bus Line
|
||||
1800 2350 1800 4250
|
||||
$Comp
|
||||
L Device:C_Small C2
|
||||
U 1 1 5E8640BA
|
||||
@ -4002,4 +3939,84 @@ F 4 "C15850" H 3700 5900 50 0001 C CNN "LCSC Part"
|
||||
1 3700 5900
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5050 900 4750 900
|
||||
Connection ~ 5050 900
|
||||
$Comp
|
||||
L Device:C_Small C38
|
||||
U 1 1 5FB5B1B9
|
||||
P 4350 1300
|
||||
F 0 "C38" H 4442 1346 50 0000 L CNN
|
||||
F 1 "22n" H 4442 1255 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 4350 1300 50 0001 C CNN
|
||||
F 3 "~" H 4350 1300 50 0001 C CNN
|
||||
F 4 "C21122" H 4350 1300 50 0001 C CNN "LCSC Part"
|
||||
1 4350 1300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6750 5300 7050 5300
|
||||
$Comp
|
||||
L Device:C_Small C41
|
||||
U 1 1 6070D634
|
||||
P 7050 5200
|
||||
F 0 "C41" H 7100 5250 50 0000 L CNN
|
||||
F 1 "2u2" H 7100 5150 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 7050 5200 50 0001 C CNN
|
||||
F 3 "~" H 7050 5200 50 0001 C CNN
|
||||
F 4 "C23630" H 7050 5200 50 0001 C CNN "LCSC Part"
|
||||
1 7050 5200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Connection ~ 7050 5300
|
||||
Wire Wire Line
|
||||
7050 5300 7400 5300
|
||||
$Comp
|
||||
L Device:C_Small C39
|
||||
U 1 1 604926F4
|
||||
P 4750 1300
|
||||
F 0 "C39" H 4800 1350 50 0000 L CNN
|
||||
F 1 "2u2" H 4800 1250 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 4750 1300 50 0001 C CNN
|
||||
F 3 "~" H 4750 1300 50 0001 C CNN
|
||||
F 4 "C23630" H 4750 1300 50 0001 C CNN "LCSC Part"
|
||||
1 4750 1300
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C_Small C17
|
||||
U 1 1 60492089
|
||||
P 4750 800
|
||||
F 0 "C17" H 4800 850 50 0000 L CNN
|
||||
F 1 "2u2" H 4800 750 50 0000 L CNN
|
||||
F 2 "stdpads:C_0603" H 4750 800 50 0001 C CNN
|
||||
F 3 "~" H 4750 800 50 0001 C CNN
|
||||
F 4 "C23630" H 4750 800 50 0001 C CNN "LCSC Part"
|
||||
1 4750 800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text GLabel 4750 700 0 50 Input ~ 0
|
||||
Vin
|
||||
$Comp
|
||||
L Device:R_Small R19
|
||||
U 1 1 5FFDC1D7
|
||||
P 8300 5000
|
||||
F 0 "R19" V 8250 5000 50 0000 C BNN
|
||||
F 1 "33k" V 8350 5000 50 0000 C TNN
|
||||
F 2 "stdpads:R_0603" H 8300 5000 50 0001 C CNN
|
||||
F 3 "~" H 8300 5000 50 0001 C CNN
|
||||
F 4 "C4216" H 8300 5000 50 0001 C CNN "LCSC Part"
|
||||
1 8300 5000
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
Wire Bus Line
|
||||
3300 4850 3300 5550
|
||||
Wire Bus Line
|
||||
600 3750 600 4650
|
||||
Wire Bus Line
|
||||
1800 4650 1800 5450
|
||||
Wire Bus Line
|
||||
1800 2350 1800 4250
|
||||
Wire Bus Line
|
||||
3300 1950 3300 4550
|
||||
$EndSCHEMATC
|
||||
|
BIN
Simulations/MenuButton.asc
Normal file
BIN
Simulations/MenuButton.asc
Normal file
Binary file not shown.
BIN
Simulations/MenuButton.plt
Normal file
BIN
Simulations/MenuButton.plt
Normal file
Binary file not shown.
513
cpld/GR8RAM.v
Normal file
513
cpld/GR8RAM.v
Normal file
@ -0,0 +1,513 @@
|
||||
module GR8RAM(C25M, PHI0, nPBOD, nBOD, nRES,
|
||||
nIOSEL, nDEVSEL, nIOSTRB,
|
||||
RA, nWE, nWEout, Adir,
|
||||
RD, Ddir,
|
||||
DMAin, DMAout, INTin, INTout,
|
||||
nDMA, nRDY, nNMI, nIRQ, nINH, nRESout
|
||||
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
|
||||
nFCS, FCK, MISO, MOSI);
|
||||
|
||||
/* Clock signals */
|
||||
/* Outputs: C25M, PHI0r1, PHI0r2, */
|
||||
input C25M, PHI0;
|
||||
reg PHI0r0, PHI0r1, PHI0r2;
|
||||
always @(negedge C25M) begin PHI0r0 <= PHI0; end
|
||||
always @(posedge C25M) begin PHI0r1 <= PHI0r0; PHI0r2 <= PHI0r1; end
|
||||
|
||||
/* Reset/brown-out detect synchronized inputs */
|
||||
/* Outputs: nRESr, nPBODr, nBODf */
|
||||
input nRES, nPBOD, nBOD;
|
||||
reg nRESr0, nRESr;
|
||||
reg nPBODr0, nPBODr;
|
||||
reg nBODr0, nBODr, nBODf0, nBODf;
|
||||
always @(posedge C25M) begin
|
||||
// Double-synchronize nBOD, nPBOD, nRES
|
||||
nPBODr0 <= nPBOD; nBODr0 <= nBOD; nRESr0 <= nRES;
|
||||
nPBODr <= nPBODr0; nBODr <= nBODr0; nRESr <= nRESr0;
|
||||
|
||||
// Filter nBODr to get nBODf. Output hi when hi for $5E0F-$10000 cycles
|
||||
if (LS[15:0]==16'h5E0F) begin // When LS low-order is $5E0F
|
||||
nBODf0 <= nBODr; // "Precharge" nBODf0
|
||||
nBODf <= nBODf0; // "Evaluate" computed nBODf0 into nBODf
|
||||
end else if (nBODr2) begin // Else AND nBODf0 with nBODr
|
||||
nBODf0 <= nBODf0 && nBODr;
|
||||
end
|
||||
end
|
||||
|
||||
/* Long state counter: counts from 0 to $5F5E0F (6,249,999) *
|
||||
* CSec: 1/2 Hz clock */
|
||||
/* Outputs: LS, CSec */
|
||||
reg [22:0] LS = 0;
|
||||
reg [1:0] CSec = 0;
|
||||
reg LSEN = 0;
|
||||
always @(posedge C25M) begin
|
||||
// Allow LS to fully count once nBODf active
|
||||
if (nBODf) LSEN <= 1;
|
||||
|
||||
// LS rolls over at 24'h5F5E0F or at 16'h5E0F when LSEN is 0
|
||||
if ((LS[22:16]==7'h5F || ~LSEN) && LS[15:0]==16'h5E0F) LS <= 0;
|
||||
else LS <= LS+1;
|
||||
|
||||
// Flip 1/2 Hz clocks when LS==23'h5F5E0F
|
||||
if (LS[22:0]==23'h5F5E0F) CSec <= CSec+1;
|
||||
end
|
||||
|
||||
/* Init state */
|
||||
output reg nRESout = 0;
|
||||
reg InitActv = 0;
|
||||
reg InitIntr = 0;
|
||||
reg SDRAMActv = 0;
|
||||
always @(posedge C25M) begin
|
||||
if (~nBODf) begin
|
||||
nRESout <= 0;
|
||||
InitActv <= 0;
|
||||
InitIntr <= 1;
|
||||
end else if (LS[22:0]==23'h0FFF10) begin
|
||||
InitActv <= ~AppleActive;
|
||||
InitIntr <= 0;
|
||||
end else if (LS[22:0]==23'h504010) begin
|
||||
nRESout <= InitActv && ~InitIntr;
|
||||
InitActv <= 0;
|
||||
SDRAMActv <= InitActv && ~InitIntr;
|
||||
end
|
||||
end
|
||||
|
||||
/* Apple IO area select signals */
|
||||
/* Outputs: DEVSELr */
|
||||
input nIOSEL, nDEVSEL, nIOSTRB;
|
||||
reg DEVSELr0, DEVSELr;
|
||||
always @(negedge C25M) begin DEVSELr0 <= ~nDEVSEL; end
|
||||
always @(posedge C25M) begin DEVSELr <= DEVSELr0; end
|
||||
|
||||
/* DMA/IRQ daisy chain */
|
||||
input DMAin, INTin;
|
||||
output DMAout = DMAin;
|
||||
output INTout = INTin;
|
||||
|
||||
/* Apple open-drain outputs */
|
||||
output nDMA = 1;
|
||||
output nRDY = 1;
|
||||
output nNMI = 1;
|
||||
output nIRQ = ~(TIRQEN && TIRQMask);
|
||||
output nINH = 1;
|
||||
|
||||
/* Apple address bus */
|
||||
/* Outputs: RAr1, nWEr1 */
|
||||
input [15:0] RA;
|
||||
input nWE;
|
||||
output RAdir = 1;
|
||||
output nWEout = 1;
|
||||
reg [15:0] RAr0; reg nWEr0;
|
||||
reg [15:0] RAcur; reg nWEcur;
|
||||
always @(negedge C25M) begin RAr0 <= RA; nWEr0 <= nWE; end
|
||||
always @(posedge C25M) begin
|
||||
if (S==0 && PHI0r1 && ~PHI0r2) begin
|
||||
RAcur[15:0] <= RAr0[15:0];
|
||||
nWEcur <= nWEr0;
|
||||
end
|
||||
end
|
||||
|
||||
/* Apple select signals */
|
||||
/* Outputs: ROMSpecRD, RAMSpecSEL, RAMSpecRD, RAMSpecWR, RAMSEL */
|
||||
wire ROMSpecRD = RAcur[15:12]==4'hC && RAcur[11:8]!=4'h0 && nWEcur;
|
||||
wire RAMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[7:4]!=4'h8 && RAcur[3:0]==4'h3;
|
||||
wire RAMSpecRD = RAMSpecSEL && nWEcur;
|
||||
wire RAMSpecWR = RAMSpecSEL && ~nWEcur;
|
||||
reg RAMSEL = 0;
|
||||
wire RAMWR = RAMSEL && ~nWEcur;
|
||||
always @(posedge C25M) begin
|
||||
if (S==5) RAMSEL <= RAMSpecSEL && DEVSELr;
|
||||
else if (S==0) RAMSEL <= 0;
|
||||
end
|
||||
|
||||
/* Apple data bus */
|
||||
inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0];
|
||||
reg [7:0] RDout;
|
||||
reg RDOE = 0;
|
||||
output RDdir = ~((~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOEN)) &&
|
||||
PHI0 && PHI0r2 && nWE && RDOE && ~BODf);
|
||||
|
||||
/* Slinky address registers */
|
||||
reg [24:0] Addr;
|
||||
wire AddrHSpecSEL = RAcur[3:0]==4'h2;
|
||||
wire AddrMSpecSEL = RAcur[3:0]==4'h1;
|
||||
wire AddrLSpecSEL = RAcur[3:0]==4'h0;
|
||||
always @(posedge C25M) begin
|
||||
if (~nRESr) begin
|
||||
Addr[24] <= 1'b0;
|
||||
Addr[23:20] <= SetFW[1] ? 4'h0 : 4'hF;
|
||||
Addr[19:0] <= 20'h00000;
|
||||
end else if (S==7 && DEVSELr) begin
|
||||
if (AddrHSpecSEL || AddrMSpecSEL || AddrLSpecSEL) begin
|
||||
Addr[24] <= 1'b0;
|
||||
end
|
||||
|
||||
if (AddrHSpecSEL) begin
|
||||
Addr[23:16] <= { SetFW[1] ? RD[7:4] : 4'hF, RD[3:0] };
|
||||
end else if ((RAMSEL && Addr[15:0]==16'hFFFF) ||
|
||||
(AddrMSpecSEL && Addr[15] && ~RD[7]) ||
|
||||
(AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF)) begin
|
||||
Addr[23:16] <= Addr[23:16]+1;
|
||||
end
|
||||
|
||||
if (AddrMSpecSEL) begin
|
||||
Addr[15:8] <= RD[7:0];
|
||||
end else if ((RAMSEL && Addr[7:0]==8'hFF) ||
|
||||
(AddrLSpecSEL && Addr[7] && ~RD[7])) begin
|
||||
Addr[15:8] <= Addr[15:8]+1;
|
||||
end
|
||||
|
||||
if (AddrLSpecSEL) begin
|
||||
Addr[7:0] <= RD[7:0];
|
||||
end else if (RAMSEL) begin
|
||||
Addr[7:0] <= Addr[7:0]+1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* SPI flash */
|
||||
output reg nFCS = 1;
|
||||
output reg FCK = 0;
|
||||
output reg MOSI = MOSIOE ? MOSIout : 1'bZ;
|
||||
reg MOSIOE = 0;
|
||||
reg MOSIout;
|
||||
input MISO;
|
||||
|
||||
/* SPI flash control */
|
||||
always @(posedge C25M) begin
|
||||
if (InitActv) begin
|
||||
// Pulse clock from init states $0FFFC0 to $907FFF
|
||||
if (LS[22:0]>=23'h0FFFC0 && LS[22:0]<=23'h907FFF) FCK <= LS[0];
|
||||
end else FCK <= 0;
|
||||
|
||||
// Flash /CS enabled from init states $0FFFB0 to s$90800F
|
||||
if (LS[22:0]>=23'h0FFFB0 && LS[22:0]<=23'h90800F) nFCS <= 0;
|
||||
end else nFCS <= 1;
|
||||
|
||||
// Send command $3B (read) (MSB first)
|
||||
if (LS[22:0]==23'h0FFFB0 || LS[22:0]==23'h0FFFB1) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFB2 || LS[22:0]==23'h0FFFB3) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFB4 || LS[22:0]==23'h0FFFB5) MOSIout <= 1;
|
||||
else if (LS[22:0]==23'h0FFFB6 || LS[22:0]==23'h0FFFB7) MOSIout <= 1;
|
||||
else if (LS[22:0]==23'h0FFFB8 || LS[22:0]==23'h0FFFB9) MOSIout <= 1;
|
||||
else if (LS[22:0]==23'h0FFFBA || LS[22:0]==23'h0FFFBB) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFBC || LS[22:0]==23'h0FFFBD) MOSIout <= 1;
|
||||
else if (LS[22:0]==23'h0FFFBE || LS[22:0]==23'h0FFFBF) MOSIout <= 1;
|
||||
// Send 24-bit address (MSB first)
|
||||
else if (LS[22:0]==23'h0FFFC0 || LS[22:0]==23'h0FFFC1) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFC2 || LS[22:0]==23'h0FFFC3) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFC4 || LS[22:0]==23'h0FFFC5) MOSIout <= SetFW[1];
|
||||
else if (LS[22:0]==23'h0FFFC6 || LS[22:0]==23'h0FFFC7) MOSIout <= SetFW[0];
|
||||
else if (LS[22:0]==23'h0FFFC8 || LS[22:0]==23'h0FFFC9) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFCA || LS[22:0]==23'h0FFFCB) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFCC || LS[22:0]==23'h0FFFCD) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFCE || LS[22:0]==23'h0FFFCF) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFD0 || LS[22:0]==23'h0FFFD1) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFD2 || LS[22:0]==23'h0FFFD3) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFD4 || LS[22:0]==23'h0FFFD5) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFD6 || LS[22:0]==23'h0FFFD7) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFD8 || LS[22:0]==23'h0FFFD9) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFDA || LS[22:0]==23'h0FFFDB) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFDC || LS[22:0]==23'h0FFFDD) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFDE || LS[22:0]==23'h0FFFDF) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFE0 || LS[22:0]==23'h0FFFE1) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFE2 || LS[22:0]==23'h0FFFE3) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFE4 || LS[22:0]==23'h0FFFE5) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFE6 || LS[22:0]==23'h0FFFE7) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFE8 || LS[22:0]==23'h0FFFE9) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFEA || LS[22:0]==23'h0FFFEB) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFEC || LS[22:0]==23'h0FFFED) MOSIout <= 0;
|
||||
else if (LS[22:0]==23'h0FFFEE || LS[22:0]==23'h0FFFEF) MOSIout <= 0;
|
||||
else MOSIout <= 0;
|
||||
|
||||
MOSIOE <= LS[22:0]<23'h0FFFF0;
|
||||
end else if (AppleActive) begin
|
||||
//TODO: control these with Apple II
|
||||
nFCS <= 1;
|
||||
FCK <= 0;
|
||||
MOSIout <= 0;
|
||||
MOSIOE <= 0;
|
||||
//TODO? sample nMenu when MOSI not outputting?
|
||||
end
|
||||
end
|
||||
|
||||
/* SDRAM address/command */
|
||||
output reg [1:0] SBA;
|
||||
output reg [12:0] SA;
|
||||
output reg RCKE = 1;
|
||||
output reg nRCS = 1;
|
||||
output reg nRAS = 1;
|
||||
output reg nCAS = 1;
|
||||
output reg nSWE = 1;
|
||||
output reg DQMH = 1;
|
||||
output reg DQML = 1;
|
||||
|
||||
/* SDRAM data bus */
|
||||
inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
|
||||
reg [7:0] WRD;
|
||||
reg SDOE = 0;
|
||||
always @(posedge C25M) begin
|
||||
// Shift { MISO, MOSI } in when InitActv. When ready, synchronize RD
|
||||
if (InitActv) if (LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
|
||||
end else WRD[7:0] <= RD[7:0];
|
||||
// Output data on SDRAM data bus only during init and when writing
|
||||
SDOE <= InitActv || (RAMSEL && nWEcur && S==6);
|
||||
end
|
||||
|
||||
/* State counters */
|
||||
reg [2:0] S = 0;
|
||||
always @(posedge C25M) begin
|
||||
if ( ~InitActv && SDRAMActv && S==0 && PHI0r1 && ~PHI0r2 && nRESr && nBODf) S <= 1;
|
||||
else if (S==0) S <= 0;
|
||||
else S <= S+1;
|
||||
end
|
||||
|
||||
/* Refresh state */
|
||||
reg RefReady = 0;
|
||||
reg RefDone = 0;
|
||||
always @(posedge C25M) begin
|
||||
// Ready to refresh when init inactive, SDRAM active, S0 and refresh not already done
|
||||
RefReady <= ~InitActv && SDRAMActv && S==0 && ~RefDone;
|
||||
|
||||
if (LS[6:0]==7'h00) RefDone <= 0; // Reset RefDone every 128 C25M cycles (5.12 us)
|
||||
else if (~InitActv && SDRAMActv && S==0 && ~RefDone && RefReady && ~(PHI0r1 && ~PHI0r2)) RefDone <= 1;
|
||||
end
|
||||
|
||||
/* SDRAM control */
|
||||
always @(posedge C25M) begin
|
||||
if (S==0 && InitActv) begin
|
||||
if (LS[22:0]==23'h000000) begin
|
||||
|
||||
end
|
||||
end else if (S==0 && ~SDRAMActv) begin
|
||||
// NOP CKE
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else if (S==0 && PHI0r1 && ~PHI0r2) begin
|
||||
// NOP CKE
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else if (S==0 && ~RefDone) begin
|
||||
// NOP CKE
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else if (S==0 && RefReady) begin
|
||||
// AREF
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else if (S==0) begin
|
||||
// NOP CKD
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else if (S==4'h1) begin
|
||||
if (ROMSpecRD || RAMSpecRD) begin
|
||||
// ACT
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
|
||||
if (RAMSpecRD) begin
|
||||
RBA[1] <= Addr[24];
|
||||
RBA[0] <= Addr[23] & ~SetLim8M;
|
||||
RA[12:0] <= Addr[22:10];
|
||||
end else begin
|
||||
RBA[1] <= 1'b1;
|
||||
RBA[0] <= 1'b0;
|
||||
RA[12:10] <= 3'b000;
|
||||
if (RAcur[11]) begin // IOSTRB
|
||||
RA[9] <= 1'b0;
|
||||
RA[8:1] <= Bank[7:0];
|
||||
RA[0] <= RAcur[10];
|
||||
end else begin // IOSEL
|
||||
RA[9] <= 1'b1;
|
||||
RA[8:1] <= 8'h00;
|
||||
RA[0] <= RAcur[10];
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h2) begin
|
||||
if (ROMSpecRD || RAMSpecRD) begin
|
||||
// RD auto-PC
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b1;
|
||||
|
||||
A[12:11] <= 1'b0; // don't care
|
||||
A[10] <= 1'b1; // auto-precharge
|
||||
A[9] <= 1'b0; // don't care
|
||||
if (RAMSpecRD) begin
|
||||
RBA[1] <= Addr[24];
|
||||
RBA[0] <= Addr[23];
|
||||
RA[8:0] <= Addr[9:1];
|
||||
DQMH <= ~Addr[0];
|
||||
DQML <= Addr[0];
|
||||
end else /* ROMSpecRD */ begin
|
||||
RBA[1] <= 1'b1;
|
||||
RBA[0] <= 1'b0;
|
||||
RA[8:0] <= RAcur[9:1];
|
||||
DQMH <= ~RAcur[0];
|
||||
DQML <= RAcur[0];
|
||||
end
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h3) begin
|
||||
if (ROMSpecRD || RAMSpecRD) begin
|
||||
// NOP cken
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h4) begin
|
||||
if (RAMSpecWR) begin
|
||||
// NOP cken
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h5) begin
|
||||
if (RAMSpecWR && DEVSELr) begin
|
||||
// ACT
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
|
||||
BA[1] <= Addr[24];
|
||||
BA[0] <= Addr[23];
|
||||
A[12:0] <= Addr[22:10];
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (s==4'h6) begin
|
||||
if (RAMWR) begin
|
||||
// WR auto-PC
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nSWE <= 1'b0;
|
||||
|
||||
BA[1] <= Addr[24];
|
||||
BA[0] <= Addr[23];
|
||||
A[12:11] <= 1'b0; // don't care
|
||||
A[10] <= 1'b1; // auto-precharge
|
||||
A[9:0] <= Addr[9:0];
|
||||
DQMH <= ~Addr[10];
|
||||
DQML <= Addr[10];
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end else if (S==4'h7) begin
|
||||
if (RAMSpecWR) begin
|
||||
// NOP cken
|
||||
RCKE <= 1'b1;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end else begin
|
||||
// NOP ckdis
|
||||
RCKE <= 1'b0;
|
||||
nRCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nSWE <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
DQML <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
Loading…
Reference in New Issue
Block a user