Remove old CPLD stuff

This commit is contained in:
Zane Kaminski 2021-03-15 13:40:41 -04:00
parent db594211fa
commit e5da11855d
153 changed files with 0 additions and 3812 deletions

View File

@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 02:27:57 August 06, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "02:27:57 August 06, 2019"
# Revisions
PROJECT_REVISION = "GR8RAM"

View File

@ -1,165 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 02:27:57 August 06, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# GR8RAM_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:27:57 AUGUST 06, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VERILOG_FILE GR8RAM.v
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_1 -to nRES
set_location_assignment PIN_75 -to A[0]
set_location_assignment PIN_77 -to A[2]
set_location_assignment PIN_79 -to A[3]
set_location_assignment PIN_80 -to A[4]
set_location_assignment PIN_81 -to A[5]
set_location_assignment PIN_83 -to C7M
set_location_assignment PIN_84 -to C7M_2
set_location_assignment PIN_4 -to A[6]
set_location_assignment PIN_5 -to A[7]
set_location_assignment PIN_9 -to A[8]
set_location_assignment PIN_10 -to A[9]
set_location_assignment PIN_11 -to A[10]
set_location_assignment PIN_12 -to A[11]
set_location_assignment PIN_15 -to A[12]
set_location_assignment PIN_6 -to Q3
set_location_assignment PIN_16 -to A[13]
set_location_assignment PIN_17 -to A[14]
set_location_assignment PIN_18 -to A[15]
set_location_assignment PIN_20 -to nWE
set_location_assignment PIN_21 -to nDEVSEL
set_location_assignment PIN_22 -to nINH
set_location_assignment PIN_24 -to nIOSTRB
set_location_assignment PIN_25 -to D[7]
set_location_assignment PIN_27 -to D[6]
set_location_assignment PIN_28 -to D[5]
set_location_assignment PIN_29 -to D[4]
set_location_assignment PIN_33 -to D[3]
set_location_assignment PIN_34 -to D[2]
set_location_assignment PIN_35 -to D[1]
set_location_assignment PIN_36 -to D[0]
set_location_assignment PIN_39 -to nCAS0
set_location_assignment PIN_40 -to nCAS1
set_location_assignment PIN_41 -to nRCS
set_location_assignment PIN_45 -to nROE
set_location_assignment PIN_46 -to RA[9]
set_location_assignment PIN_48 -to RA[10]
set_location_assignment PIN_49 -to RA[3]
set_location_assignment PIN_50 -to RA[2]
set_location_assignment PIN_51 -to RA[5]
set_location_assignment PIN_52 -to RA[0]
set_location_assignment PIN_54 -to RA[1]
set_location_assignment PIN_55 -to RA[4]
set_location_assignment PIN_56 -to RA[7]
set_location_assignment PIN_57 -to RA[6]
set_location_assignment PIN_58 -to RA[8]
set_location_assignment PIN_60 -to nRAS
set_location_assignment PIN_61 -to RD[7]
set_location_assignment PIN_63 -to RD[5]
set_location_assignment PIN_64 -to RD[6]
set_location_assignment PIN_65 -to RD[4]
set_location_assignment PIN_67 -to nRWE
set_location_assignment PIN_68 -to RD[3]
set_location_assignment PIN_69 -to RD[2]
set_location_assignment PIN_70 -to RD[1]
set_location_assignment PIN_73 -to RD[0]
set_location_assignment PIN_74 -to nIOSEL
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_global_assignment -name AUTO_PARALLEL_EXPANDERS OFF
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
set_global_assignment -name SLOW_SLEW_RATE ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_location_assignment LC1 -to Addr[0]
set_location_assignment LC2 -to Addr[1]
set_location_assignment LC3 -to Addr[2]
set_location_assignment LC4 -to Addr[3]
set_location_assignment LC5 -to Addr[4]
set_location_assignment LC6 -to Addr[5]
set_location_assignment LC7 -to Addr[6]
set_location_assignment LC8 -to Addr[7]
set_location_assignment LC9 -to Addr[8]
set_location_assignment LC10 -to Addr[9]
set_location_assignment LC11 -to Addr[10]
set_location_assignment LC12 -to Addr[11]
set_location_assignment LC13 -to Addr[12]
set_location_assignment LC14 -to Addr[13]
set_location_assignment LC15 -to Addr[14]
set_location_assignment LC16 -to Addr[15]
set_global_assignment -name PARALLEL_SYNTHESIS OFF
set_global_assignment -name STATE_MACHINE_PROCESSING "USER-ENCODED"
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF
set_location_assignment PIN_76 -to A[1]
set_location_assignment PIN_8 -to PHI0in
set_location_assignment PIN_2 -to PHI1in
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name AUTO_TURBO_BIT OFF
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b1_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b2_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b3_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b4_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b5_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b6_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b7_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b8_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b9_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to IOROMEN
set_location_assignment PIN_44 -to nMode
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to RAMSEL_MC

Binary file not shown.

View File

@ -1,374 +0,0 @@
module GR8RAM(C25M, PHI0, nPBOD, nBOD, nRES,
nIOSEL, nDEVSEL, nIOSTRB,
RA, nWEin, nWEout, Adir,
RD, Ddir,
DMAin, DMAout, INTin, INTout,
nDMA, nRDY, nNMI, nIRQ, nINH, nRESout
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI);
/* Clock signals */
input C25M, PHI0;
reg PHI0r1, PHI0r2, PHI0r3;
always @(negedge C25M) begin PHI0r1 <= PHI0; end
always @(posedge C25M) begin
PHI0r2 <= PHI0r1; PHI0r3 <= PHI0r2;
end
/* Reset/brown-out detect inputs */
input nRES, nPBOD, nBOD;
reg PBODr1, PBODr2, BODr1, BODr2, RESr1, RESr2;
always @(negedge C25M) begin
PBODr1 <= ~nPBOD; BODr1 <= ~nBOD; RESr1 <= ~nRES;
end
always @(posedge C25M) begin
PBODr2 <= PBODr1; BODr2 <= BODr1; RESr2 <= RESr1;
end
/* Apple IO area select signals */
input nIOSEL, nDEVSEL, nIOSTRB;
reg DEVSELr1, DEVSELr2;
always @(negedge C25M) begin DEVSELr1 <= ~nDEVSEL; end
always @(posedge C25M) begin DEVSELr2 <= DEVSELr1; end
/* DMA/IRQ daisy chain */
input DMAin, INTin;
output DMAout = DMAin;
output INTout = INTin;
/* Apple open-drain outputs */
output nDMA = 1;
output nRDY = 1;
output nNMI = 1;
output nIRQ = 1;
output nINH = 1;
output nRESout = 0;
/* Apple address bus */
input [15:0] RA;
input nWEin;
output RAdir = 1;
output nWEout = 1;
reg [15:0] RAr1; reg nWEr1;
reg [15:0] RAr2; reg nWEr2;
reg [15:0] RAcur; reg nWEcur;
always @(negedge C25M) begin RAr1 <= RA; nWEr1 <= nWE; end
always @(posedge C25M) begin RAr2 <= RAr1; nWEr2 <= nWEr1; end
always @(posedge C25M) begin
if (S==0 && ~PHI0r2) begin
RAcur <= RAr2;
nWEcur <= nWER2;
end
end
/* Apple select signals */
wire ROMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]!=4'h0;
wire ROMSpecRD = ROMSpecSEL && nWE;
wire RAMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[7:4]!=4'h8 && RAcur[3:0]==4'h3;
wire RAMSpecRD = RAMSpecSEL && nWE;
wire RAMSpecWR = RAMSpecSEL && ~nWE;
wire SpecRD = ROMSpecRD || RAMSpecRD;
reg RAMRD = 0, RAMWR = 0;
always @(posedge C25M) begin
if (S==5) begin
RAMRD <= RAMSpecRD && DEVSELr2;
RAMWR <= RAMSpecWR && DEVSELr2;
end else if (S==0) begin
RAMRD <= 0;
RAMWR <= 0;
end
end
/* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0];
reg RDdir = 1;
reg [7:0] RDout;
/* SDRAM data bus */
inout [7:0] SD = SDOE ? RD[7:0] : 8'bZ;
reg SDOE = 0;
/* SDRAM address/command */
output reg [1:0] SBA;
output reg [12:0] SA;
output reg RCKE = 1;
output reg nRCS = 1;
output reg nRAS = 1;
output reg nCAS = 1;
output reg nSWE = 1;
output reg DQMH = 1;
output reg DQML = 1;
/* SPI flash */
output reg nFCS = 1;
output reg FCK = 0;
output reg MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
reg MOSIout;
input MISO;
/* State counters */
reg [24:0] FS = 0;
always @(posedge C25M) begin FS <= FS+1; end
reg [2:0] S = 0;
always @(posedge C25M) begin
if (S==0 && PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2) S <= 1;
else if (S==0) S <= 0;
else S <= S+1;
end
/* Refresh state */
reg RefReady = 0;
reg RefDone = 0;
always @(posedge C25M) begin RefReady <= S==0; end
always @(posedge C25M) begin
if (FS[6:0]==7'h00) RefDone <= 0;
else (S==0 && RefReady && RCKE && ~(PHI0r2 && ~PHI0r3)) RefDone <= 1;
end
/* Slinky registers */
reg [24:0] Addr;
wire AddrHSpecSEL = RAcur[3:0]==4'h2;
wire AddrMSpecSEL = RAcur[3:0]==4'h1;
wire AddrLSpecSEL = RAcur[3:0]==4'h0;
always @(posedge C25M) begin
if (S==7 && DEVSELr2) begin
if (AddrHSpecSEL || AddrMSpecSEL || AddrLSpecSEL) begin
Addr[24] <= 1'b0;
end
if (AddrHSpecSEL) begin
Addr[23:16] <= RD[7:0];
end else if (RAMRD || RAMWR ||
(AddrMSpecSEL && Addr[15] && ~RD[7]) ||
(AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF)) begin
Addr[23:16] <= Addr[23:16]+1;
end
if (AddrMSpecSEL) begin
Addr[15:8] <= RD[7:0];
end else if (RAMRD || RAMWR ||
(AddrLSpecSEL && Addr[7] && ~RD[7])) begin
Addr[15:8] <= Addr[15:8]+1;
end
if (AddrLSpecSEL) begin
Addr[7:0] <= RD[7:0];
end else if (RAMRD || RAMWR) begin
Addr[7:0] <= Addr[7:0]+1;
end
end
end
always @(posedge C25M) begin
if (S==0) begin
if ((PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2 && SpecRD) ||
(~RefReady && ~RefDone)) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else if (RefReady && ~RefDone && RCKE &&
~(PHI0r2 && ~PHI0r3)) begin
// AREF
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h1) begin
if (SpecRD) begin
// ACT
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
if (RAMSpecRD) begin
RBA[1] <= Addr[24];
RBA[0] <= Addr[23];
RA[12:0] <= Addr[22:10];
end else begin
RBA[1] <= 1'b1;
RBA[0] <= 1'b0;
RA[12:10] <= 3'b000;
RA[9:2] <= Bank[7:0];
RA[1:0] <= RAcur[11:10];
end
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h2) begin
if (SpecRD) begin
// RD auto-PC
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b1;
A[12:11] <= 1'b0; // don't care
A[10] <= 1'b1; // auto-precharge
A[9] <= 1'b0; // don't care
if (RAMSpecRD) begin
RBA[1] <= Addr[24];
RBA[0] <= Addr[23];
RA[8:0] <= Addr[9:1];
DQMH <= ~Addr[0];
DQML <= Addr[0];
end else /* ROMSpecRD */ begin
RBA[1] <= 1'b1;
RBA[0] <= 1'b0;
RA[8:0] <= RAcur[9:1];
DQMH <= ~RAcur[0];
DQML <= RAcur[0];
end
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h3) begin
if (SpecRD) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h4) begin
if (RAMSpecWR) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h5) begin
if (RAMSpecWR && DEVSELr2) begin
// ACT
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
BA[1] <= Addr[24];
BA[0] <= Addr[23];
A[12:0] <= Addr[22:10];
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (s==4'h6) begin
if (RAMWR) begin
// WR auto-PC
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b0;
BA[1] <= Addr[24];
BA[0] <= Addr[23];
A[12:11] <= 1'b0; // don't care
A[10] <= 1'b1; // auto-precharge
A[9:0] <= Addr[9:0];
DQMH <= ~Addr[10];
DQML <= Addr[10];
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end else if (S==4'h7) begin
if (RAMSpecWR) begin
// NOP cken
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP ckdis
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end
end
end
endmodule

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

View File

@ -1,5 +0,0 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581829847188 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581829847188 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 00:10:47 2020 " "Processing started: Sun Feb 16 00:10:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581829847188 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1581829847188 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1581829847188 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1581829847318 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:47 2020 " "Processing ended: Sun Feb 16 00:10:47 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1581829847468 ""}

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

View File

@ -1 +0,0 @@
v1

Binary file not shown.

Binary file not shown.

View File

@ -1,3 +0,0 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Sat Feb 15 22:14:18 2020

Binary file not shown.

View File

@ -1,3 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566710684975 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566710684990 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 01:24:45 2019 " "Processing ended: Sun Aug 25 01:24:45 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566710685506 ""}

View File

@ -1,3 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566710988914 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566710988930 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 01:29:49 2019 " "Processing ended: Sun Aug 25 01:29:49 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566710989446 ""}

View File

@ -1,5 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566711499269 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566711499284 ""}
{ "Error" "EF7K_LAB_TOO_MANY_SEXP" "15 LAB_A 3 " "Can't place 15 sharable expanders in LAB LAB_A because the LAB can contain only 3 sharable expanders" { } { } 0 163057 "Can't place %1!d! sharable expanders in LAB %2!s! because the LAB can contain only %3!d! sharable expanders" 0 0 "Fitter" 0 -1 1566711499362 ""}
{ "Error" "EF7K_FIT_FAIL" "" "Cannot find fit." { } { } 0 163000 "Cannot find fit." 0 0 "Fitter" 0 -1 1566711499362 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 25 01:38:19 2019 " "Processing ended: Sun Aug 25 01:38:19 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566711499753 ""}

View File

@ -1,3 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566712873057 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566712873088 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:01:13 2019 " "Processing ended: Sun Aug 25 02:01:13 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566712873807 ""}

View File

@ -1,3 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566713553094 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566713553110 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:12:33 2019 " "Processing ended: Sun Aug 25 02:12:33 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566713553610 ""}

View File

@ -1,3 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566716030143 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566716030190 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:53:51 2019 " "Processing ended: Sun Aug 25 02:53:51 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566716031347 ""}

View File

@ -1,3 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566718076312 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566718076344 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 03:27:57 2019 " "Processing ended: Sun Aug 25 03:27:57 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566718077453 ""}

View File

@ -1,3 +0,0 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1581829846147 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1581829846157 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:46 2020 " "Processing ended: Sun Feb 16 00:10:46 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1581829846367 ""}

View File

@ -1,129 +0,0 @@
|GR8RAM
C7M => always3.IN0
C7M => CASr.CLK
C7M => CASel.CLK
C7M => RASr.CLK
C7M => IOROMEN.CLK
C7M => REGEN.CLK
C7M => CSEN.CLK
C7M => DBEN.CLK
C7M => Ref[0].CLK
C7M => Ref[1].CLK
C7M => Ref[2].CLK
C7M => Ref[3].CLK
C7M => S[0].CLK
C7M => S[1].CLK
C7M => S[2].CLK
C7M => PHI0seen.CLK
C7M => PHI1reg.CLK
C7M_2 => ~NO_FANOUT~
Q3 => ~NO_FANOUT~
PHI0in => ~NO_FANOUT~
PHI1in => comb.IN0
PHI1in => PHI1b0_MC.DATAIN
nRES => always1.IN0
nMode => ~NO_FANOUT~
A[0] => Equal0.IN7
A[0] => Equal1.IN7
A[0] => Equal2.IN7
A[0] => Equal3.IN7
A[0] => Equal4.IN7
A[0] => Equal5.IN7
A[0] => Equal13.IN21
A[1] => Equal0.IN6
A[1] => Equal1.IN6
A[1] => Equal2.IN6
A[1] => Equal3.IN6
A[1] => Equal4.IN6
A[1] => Equal5.IN6
A[1] => Equal13.IN20
A[2] => Equal0.IN5
A[2] => Equal1.IN5
A[2] => Equal2.IN5
A[2] => Equal3.IN5
A[2] => Equal4.IN5
A[2] => Equal5.IN5
A[2] => Equal13.IN19
A[3] => Equal0.IN4
A[3] => Equal1.IN4
A[3] => Equal2.IN4
A[3] => Equal3.IN4
A[3] => Equal4.IN4
A[3] => Equal5.IN4
A[3] => Equal13.IN18
A[4] => Equal13.IN17
A[5] => Equal13.IN16
A[6] => Equal13.IN15
A[7] => Equal13.IN14
A[8] => Equal13.IN13
A[9] => Equal13.IN12
A[10] => Equal13.IN11
A[11] => ~NO_FANOUT~
A[12] => ~NO_FANOUT~
A[13] => ~NO_FANOUT~
A[14] => ~NO_FANOUT~
A[15] => ~NO_FANOUT~
RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
RA[10] <= RA.DB_MAX_OUTPUT_PORT_TYPE
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.IN0
nWE => comb.DATAB
nWE => CSEN.IN1
nWE => RASr.IN1
nWE => CASel.IN0
nWE => CASr.IN1
nWE => CAS0f.IN1
nWE => CAS1f.IN1
D[0] <> D[0]
D[1] <> D[1]
D[2] <> D[2]
D[3] <> D[3]
D[4] <> D[4]
D[5] <> D[5]
D[6] <> D[6]
D[7] <> D[7]
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nDEVSEL => comb.IN0
nIOSEL => RA.IN1
nIOSEL => RA.IN0
nIOSEL => comb.IN0
nIOSTRB => RA.IN0
nIOSTRB => RA.IN1
nIOSTRB => RA.IN1
nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= comb.DB_MAX_OUTPUT_PORT_TYPE
nCAS0 <= comb.DB_MAX_OUTPUT_PORT_TYPE
nCAS1 <= comb.DB_MAX_OUTPUT_PORT_TYPE
nRCS <= comb.DB_MAX_OUTPUT_PORT_TYPE
nROE <= comb.DB_MAX_OUTPUT_PORT_TYPE
nRWE <= comb.DB_MAX_OUTPUT_PORT_TYPE

Binary file not shown.

Binary file not shown.

View File

@ -1,18 +0,0 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

Binary file not shown.

View File

@ -1,5 +0,0 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Binary file not shown.

Some files were not shown because too many files have changed in this diff Show More