forked from Apple-2-HW/GR8RAM
idk
This commit is contained in:
Zane Kaminski
parent
b0b8b0dc6c
commit
c4844b9646
@ -1,37 +0,0 @@
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GR8RAM/LibraryCard flash memory map
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-----------------------------
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FF FFFF | |
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.. .... | reserved (12 MB) |
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40 0000 | |
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-----------------------------
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3F FFFF | |
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.. .... | firmware 3 (1 MB) |
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30 0000 | |
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-----------------------------
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2F FFFF | |
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.. .... | firmware 2 (1 MB) |
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20 0000 | |
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-----------------------------
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1F FFFF | |
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.. .... | firmware 1 (1 MB) |
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10 0000 | |
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-----------------------------
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0F FFFF | |
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.. .... | firmware 0 (1 MB) |
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00 0000 | |
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-----------------------------
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Firmware area map (X == 0, 1, 2, or 3)
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-----------------------------
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XF FFFF | |
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.. .... | reserved (510 kB) |
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X8 0800 | |
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-----------------------------
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X8 07FF | |
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.. .... | IOSEL area (2 kB) |
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X8 0000 | |
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-----------------------------
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X7 FFFF | |
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.. .... | 256x IOSTRB area (512 kB) |
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X0 0000 | |
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-----------------------------
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38
Documentation/Flash Map
Normal file
38
Documentation/Flash Map
Normal file
@ -0,0 +1,38 @@
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GR8RAM flash memory map
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.... -----------------------------
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7FFF | |
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.... | firmware 3 (8 kB) |
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6000 | |
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-----------------------------
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5FFF | |
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.... | firmware 2 (8 kB) |
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4000 | |
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-----------------------------
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3FFF | |
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.... | firmware 1 (8 kB) |
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2000 | |
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-----------------------------
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1FFF | |
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.... | firmware 0 (8 kB) |
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0000 | |
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-----------------------------
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Firmware area map (N=$0000, $2000, $4000, $6000)
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-----------------------------
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N+1FFF | |
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.... | IOSTRB bank 1 (2 kB) |
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N+1800 | |
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-----------------------------
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N+17FF | |
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.... | IOSEL bank 1 (2 kB) |
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N+1000 | |
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-----------------------------
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N+0FFF | |
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.... | IOSTRB bank 0 (2 kB) |
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N+0800 | |
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-----------------------------
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N+07FF | |
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.... | IOSEL bank 0 (2 kB) |
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N+0000 | |
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-----------------------------
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@ -1,45 +0,0 @@
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Addr Slinky GR8RAM TimeMachine
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$0 RAddrL RAddrL RAddrL
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$1 RAddrM RAddrM RAddrM
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$2 RAddrH RAddrH RAddrH
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$3 RData RData RData
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$4 DMAAddrL
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$5 DMAAddrH
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$6
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$7
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$8
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$9
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$A
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$B
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$C
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$D Readin/out Readin/out
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$E Command Command
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$F Bank Bank Bank
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GR8RAM commands
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CmdNum Description Argument
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$00 SetReadinout RiNum/RoNum
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$EF CFGPrgmEN don't care
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$EE CFGEraseEN don't care
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GR8RAM Readin
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RiNum Description Data
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$10 SPI flash { MOSI(1), X(6), CS(1) }
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$11 SPI flash + clk pulse { MOSI(1), X(6), CS(1) }
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$13 CFG flash + clk pulse { CFGDin(1), X(7) }
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$20 Mode { RF/nSlinky(1), X(4), Size(3) }
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$21 RAddrHH { X(7), RAddr[24](1) }
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GR8RAM Readout
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RoNum Description
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$00 Magic $C1
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$01 Card ID $00
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$10 SPI flash { MISO(1), X(7) }
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$20 Mode { RF/nSlinky(1), X(4), Size(3) }
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TimeMachine commands
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$XX DMA into Apple RAM Length
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$XX DMA into Slinky RAM Length
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$XX DMA into Apple RAM Length-256
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$XX DMA into Slinky RAM Length-256
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@ -1,6 +0,0 @@
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GR8RAM Settings (not applicable to Library Card!)
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Settings[15] SetValid (1 = invalid, 0 = valid)
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Settings[14] SetFW (1 = RAMFactor, 0 = Slinky)
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Settings[13] SetLim8M
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Settings[12:0] Reserved
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@ -1,107 +0,0 @@
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UFM Load
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LState ARCLK ARShft DRCLK DRShft UFM
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--------------------------------------------------------------------------------
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$0000 0 1 0 0
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$0FBF 0 1 0 0
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...
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$0FC0 1 1 0 0
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$0FC1 1 1 0 0
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$0FC2 0 1 0 0
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$0FC3 0 1 0 0
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$0FC4 1 1 0 0
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$0FC5 1 1 0 0
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$0FC6 0 1 0 0
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$0FC7 0 1 0 0
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$0FC8 1 1 0 0
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$0FC9 1 1 0 0
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$0FCA 0 1 0 0
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$0FCB 0 1 0 0
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$0FCC 1 1 0 0
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$0FCD 1 1 0 0
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$0FCE 0 1 0 0
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$0FCF 0 1 0 0
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$0FD0 1 1 0 0
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$0FD1 1 1 0 0
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$0FD2 0 1 0 0
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$0FD3 0 1 0 0
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$0FD4 1 1 0 0
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$0FD5 1 1 0 0
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$0FD6 0 1 0 0
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$0FD7 0 1 0 0
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$0FD8 1 1 0 0
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$0FD9 1 1 0 0
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$0FDA 0 1 0 0
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$0FDB 0 1 0 0
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$0FDC 1 1 0 0
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$0FDD 1 1 0 0
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$0FDE 0 1 0 0
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$0FDF 0 1 0 0
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$0FE0 1 1 0 0
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$0FE1 1 1 0 0
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$0FE2 0 1 0 0
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$0FE3 0 1 0 0
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$0FE4 1 1 0 0
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$0FE5 1 1 0 0
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$0FE6 0 1 0 0
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$0FE7 0 1 0 0
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$0FE8 1 1 0 0
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$0FE9 1 1 0 0
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$0FEA 0 1 0 0
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$0FEB 0 1 0 0
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$0FEC 1 1 0 0
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$0FED 1 1 0 0
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$0FEE 0 1 0 0
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$0FEF 0 1 0 0
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$0FF0 1 1 0 0
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$0FF1 1 1 0 0
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$0FF2 0 1 0 0
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$0FF3 0 1 0 0
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$0FF4 1 1 0 0
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$0FF5 1 1 0 0
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$0FF6 0 1 0 0
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$0FF7 0 1 0 0
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$0FF8 1 1 0 0
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$0FF9 1 1 0 0
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$0FFA 0 1 0 0
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$0FFB 0 1 0 0
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$0FFC 1 1 0 0
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$0FFD 1 1 0 0
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$0FFE 0 1 0 0
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$0FFF 0 1 0 0
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$1000 0 0 1 0 parallel load into DR
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$1001 0 0 1 0
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$1002 0 0 0 1
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$1003 0 0 0 1
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$1004 0 0 1 1 SetLoaded <= Dout
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$1005 0 0 1 1
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$1006 0 0 0 1
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$1007 0 0 0 1
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$1008 0 0 1 1 latch DR[14] (SetFW)
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$1009 0 0 1 1
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$100A 0 0 0 1
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$100B 0 0 0 1
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$100C 1 0 0 1 latch DR[13] (SetLim8M)
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$100D 1 0 0 1
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$100E 0 0 0 0
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$100F 0 0 0 0
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...
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$1FF0 0 0 1 0 parallel load into DR
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$1FF1 0 0 1 0
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$1FF2 0 0 0 1
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$1FF3 0 0 0 1
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$1FF4 0 0 1 1 SetLoaded <= Dout
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$1FF5 0 0 1 1
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$1FF6 0 0 0 1
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$1FF7 0 0 0 1
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$1FF8 0 0 1 1 latch DR[14] (SetFW)
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$1FF9 0 0 1 1
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$1FFA 0 0 0 1
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$1FFB 0 0 0 1
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$1FFC 1 0 0 1 latch DR[13] (SetLim8M)
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$1FFD 1 0 0 1
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$1FFE 0 0 0 0
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$1FFF 0 0 0 0
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$2000 0 0 0 0 Everything 0, set SetLoaded
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@ -548,6 +548,31 @@ X 1 1 0 -100 100 U 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# Switch_SW_DIP_x02
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#
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DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
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F0 "SW" 0 250 50 H V C CNN
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F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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SW?DIP?x2*
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$ENDFPLIST
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DRAW
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C -80 0 20 0 0 0 N
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C -80 100 20 0 0 0 N
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C 80 0 20 0 0 0 N
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C 80 100 20 0 0 0 N
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S -150 200 150 -100 0 1 10 f
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P 2 0 0 0 -60 5 93 46 N
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P 2 0 0 0 -60 105 93 146 N
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X ~ 1 -300 100 200 R 50 50 1 1 P
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X ~ 2 -300 0 200 R 50 50 1 1 P
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X ~ 3 300 0 200 L 50 50 1 1 P
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X ~ 4 300 100 200 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# power_+12V
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#
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DEF power_+12V #PWR 0 0 Y Y 1 F P
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Binary file not shown.
21545
GR8RAM.kicad_pcb
21545
GR8RAM.kicad_pcb
File diff suppressed because it is too large
Load Diff
1641
GR8RAM.sch
1641
GR8RAM.sch
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
20
cpld/GR8RAM.dpf
Executable file
20
cpld/GR8RAM.dpf
Executable file
@ -0,0 +1,20 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<pin_planner>
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<pin_info>
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<pin name="Ddor" source="Pin Planner" >
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</pin>
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<pin name="SDp1[" source="Pin Planner" >
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</pin>
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<pin name="sa[10[" source="Pin Planner" >
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</pin>
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<pin name="fw[0]" source="Pin Planner" >
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</pin>
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</pin_info>
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<buses>
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</buses>
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<group_file_association>
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</group_file_association>
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<pin_planner_file_specifies>
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</pin_planner_file_specifies>
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</pin_planner>
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@ -71,4 +71,75 @@ set_global_assignment -name SYNTHESIS_SEED 123
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set_global_assignment -name SEED 235
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set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
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set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
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set_global_assignment -name VERILOG_FILE GR8RAM.v
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set_global_assignment -name VERILOG_FILE GR8RAM.v
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set_location_assignment PIN_1 -to RA[4]
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set_location_assignment PIN_2 -to RA[5]
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set_location_assignment PIN_3 -to RA[6]
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set_location_assignment PIN_4 -to RA[3]
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set_location_assignment PIN_5 -to nFCS
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set_location_assignment PIN_6 -to RA[7]
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set_location_assignment PIN_7 -to RA[8]
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set_location_assignment PIN_8 -to RA[9]
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set_location_assignment PIN_12 -to FCK
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set_location_assignment PIN_14 -to RA[10]
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set_location_assignment PIN_15 -to MOSI
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set_location_assignment PIN_16 -to MISO
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set_location_assignment PIN_17 -to Ddir
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set_location_assignment PIN_30 -to nRESout
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set_location_assignment PIN_34 -to RA[11]
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set_location_assignment PIN_35 -to RA[12]
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set_location_assignment PIN_36 -to RA[13]
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set_location_assignment PIN_37 -to RA[14]
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set_location_assignment PIN_38 -to RA[15]
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set_location_assignment PIN_39 -to nIOSEL
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set_location_assignment PIN_42 -to nIOSTRB
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set_location_assignment PIN_40 -to nDEVSEL
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set_location_assignment PIN_41 -to PHI0
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set_location_assignment PIN_43 -to nWE
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set_location_assignment PIN_44 -to nRES
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set_location_assignment PIN_47 -to SD[1]
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set_location_assignment PIN_50 -to SD[0]
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set_location_assignment PIN_51 -to SD[4]
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set_location_assignment PIN_100 -to RA[0]
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set_location_assignment PIN_99 -to RD[7]
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set_location_assignment PIN_52 -to SD[5]
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set_location_assignment PIN_54 -to SD[7]
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set_location_assignment PIN_55 -to SD[3]
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set_location_assignment PIN_56 -to SD[2]
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set_location_assignment PIN_53 -to SD[6]
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set_location_assignment PIN_57 -to DQMH
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set_location_assignment PIN_58 -to nSWE
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set_location_assignment PIN_62 -to nRAS
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set_location_assignment PIN_61 -to nCAS
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set_location_assignment PIN_64 -to C25M
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set_location_assignment PIN_66 -to RCKE
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set_location_assignment PIN_67 -to nRCS
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set_location_assignment PIN_68 -to SA[12]
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set_location_assignment PIN_69 -to SBA[0]
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set_location_assignment PIN_70 -to SA[11]
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set_location_assignment PIN_71 -to SBA[1]
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set_location_assignment PIN_72 -to SA[9]
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set_location_assignment PIN_73 -to SA[10]
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set_location_assignment PIN_74 -to SA[8]
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set_location_assignment PIN_75 -to SA[0]
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set_location_assignment PIN_76 -to SA[4]
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set_location_assignment PIN_77 -to SA[6]
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set_location_assignment PIN_78 -to SA[7]
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set_location_assignment PIN_81 -to SA[1]
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set_location_assignment PIN_82 -to SA[2]
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set_location_assignment PIN_83 -to SA[5]
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set_location_assignment PIN_84 -to SA[3]
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set_location_assignment PIN_85 -to DQML
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set_location_assignment PIN_86 -to RD[0]
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set_location_assignment PIN_87 -to RD[1]
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set_location_assignment PIN_88 -to RD[2]
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set_location_assignment PIN_89 -to RD[3]
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set_location_assignment PIN_90 -to RD[4]
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set_location_assignment PIN_91 -to RD[5]
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set_location_assignment PIN_92 -to RD[6]
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set_location_assignment PIN_97 -to RA[2]
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set_location_assignment PIN_98 -to RA[1]
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set_location_assignment PIN_96 -to SetFW[0]
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set_location_assignment PIN_95 -to SetFW[1]
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set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
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set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
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BIN
cpld/GR8RAM.qws
BIN
cpld/GR8RAM.qws
Binary file not shown.
@ -1,6 +1,6 @@
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module GR8RAM(C25M, PHI0, nRES, nRESout,
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nIOSEL, nDEVSEL, nIOSTRB,
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SetRF, SetLim8M,
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SetFW,
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RA, nWE, RD, RDdir,
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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@ -42,10 +42,11 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
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/* Apple select signals */
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wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0;
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wire BankSpecSEL = RA[3:0]==4'hF;
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wire RAMSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && RA[3:0]==4'h3 && REGEN;
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wire AddrHSpecSEL = RA[3:0]==4'h2;
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wire AddrMSpecSEL = RA[3:0]==4'h1;
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wire AddrLSpecSEL = RA[3:0]==4'h0;
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wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN;
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wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3 && (~SetLim1M || Addr[23:20]==0) && (~SetLim8M || ~Addr[23]);
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wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2;
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wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1;
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wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0;
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reg ROMSpecSELr, RAMSpecSELr, nWEr;
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wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
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wire RAMSEL = ~nDEVSEL && RAMSpecSELr;
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@ -53,12 +54,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
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wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
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wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
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wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
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always @(posedge C25M) begin
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if (PSStart) begin
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ROMSpecSELr <= ROMSpecSEL;
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RAMSpecSELr <= RAMSpecSEL;
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nWEr <= nWE;
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end
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always @(posedge PHI0) begin
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ROMSpecSELr <= ROMSpecSEL;
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RAMSpecSELr <= RAMSpecSEL;
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nWEr <= nWE;
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end
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/* IOROMEN and REGEN control */
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@ -174,7 +173,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
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FCK <= ~(IS==5);
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end
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endcase
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FCS <= IS==5 || IS==6;
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FCS <= IS==4 || IS==5 || IS==6;
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MOSIOE <= IS==5;
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end
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@ -183,16 +182,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
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1, 2: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 7
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3'h4: MOSIout <= SetRF; // Address bit 23
|
||||
3'h4: MOSIout <= 1'b0; // Address bit 23
|
||||
3'h5: MOSIout <= 1'b0; // Address bit 15
|
||||
3'h6: MOSIout <= 1'b0; // Address bit 7
|
||||
default MOSIout <= 1'b0;
|
||||
endcase
|
||||
end 3, 4: begin
|
||||
case (LS[2:0])
|
||||
3'h3: MOSIout <= 1'b1; // Command bit 6
|
||||
3'h3: MOSIout <= 1'b0; // Command bit 6
|
||||
3'h4: MOSIout <= 1'b0; // Address bit 22
|
||||
3'h5: MOSIout <= 1'b0; // Address bit 14
|
||||
3'h5: MOSIout <= SetFW[1]; // Address bit 14
|
||||
3'h6: MOSIout <= 1'b0; // Address bit 6
|
||||
default MOSIout <= 1'b0;
|
||||
endcase
|
||||
@ -200,13 +199,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
|
||||
case (LS[2:0])
|
||||
3'h3: MOSIout <= 1'b1; // Command bit 5
|
||||
3'h4: MOSIout <= 1'b0; // Address bit 21
|
||||
3'h5: MOSIout <= 1'b0; // Address bit 13
|
||||
3'h5: MOSIout <= SetFW[0]; // Address bit 13
|
||||
3'h6: MOSIout <= 1'b0; // Address bit 5
|
||||
default MOSIout <= 1'b0;
|
||||
endcase
|
||||
end 7, 8: begin
|
||||
case (LS[2:0])
|
||||
3'h3: MOSIout <= 1'b0; // Command bit 4
|
||||
3'h3: MOSIout <= 1'b1; // Command bit 4
|
||||
3'h4: MOSIout <= 1'b0; // Address bit 20
|
||||
3'h5: MOSIout <= 1'b0; // Address bit 12
|
||||
3'h6: MOSIout <= 1'b0; // Address bit 4
|
||||
@ -248,8 +247,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
|
||||
endcase
|
||||
end
|
||||
|
||||
input SetRF;
|
||||
input SetLim8M;
|
||||
input [1:0] SetFW;
|
||||
wire SetRF = SetFW[1:0] != 2'b11;
|
||||
wire SetLim1M = SetFW[1];
|
||||
wire SetLim8M = SetFW[1:0] != 2'b00;
|
||||
|
||||
/* SDRAM data bus */
|
||||
inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
|
||||
@ -452,7 +453,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
|
||||
SBA[1:0] <= { 2'b10 };
|
||||
SA[12:0] <= { 10'b0011000100, LS[12:10] };
|
||||
end else if (RAMSpecSELr) begin
|
||||
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
|
||||
SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
|
||||
SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]};
|
||||
end else begin
|
||||
SBA[1:0] <= 2'b10;
|
||||
@ -460,7 +461,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
|
||||
end
|
||||
end 2: begin // RD
|
||||
if (RAMSpecSELr) begin
|
||||
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
|
||||
SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
|
||||
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
||||
DQML <= Addr[0];
|
||||
DQMH <= ~Addr[0];
|
||||
|
||||
Binary file not shown.
Binary file not shown.
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@ -1,6 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429543853 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429543868 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:23 2021 " "Processing started: Mon Mar 22 12:12:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429543868 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616429543868 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616429543868 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616429545103 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616429545134 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:25 2021 " "Processing ended: Mon Mar 22 12:12:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616429545696 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161759471 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:38 2021 " "Processing started: Sun Apr 11 13:22:38 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618161760940 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618161760971 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:41 2021 " "Processing ended: Sun Apr 11 13:22:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618161761456 ""}
|
||||
|
||||
Binary file not shown.
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@ -1,3 +1,3 @@
|
||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Mon Mar 22 01:13:17 2021
|
||||
Creation_Time = Sun Apr 11 00:06:29 2021
|
||||
|
||||
Binary file not shown.
File diff suppressed because one or more lines are too long
@ -76,9 +76,6 @@ C25M => Addr[22].CLK
|
||||
C25M => Addr[23].CLK
|
||||
C25M => REGEN.CLK
|
||||
C25M => IOROMEN.CLK
|
||||
C25M => nWEr.CLK
|
||||
C25M => RAMSpecSELr.CLK
|
||||
C25M => ROMSpecSELr.CLK
|
||||
C25M => nRESout~reg0.CLK
|
||||
C25M => LS[0].CLK
|
||||
C25M => LS[1].CLK
|
||||
@ -100,6 +97,9 @@ C25M => PHI0r2.CLK
|
||||
C25M => PHI0r1.CLK
|
||||
C25M => IS~7.DATAIN
|
||||
PHI0 => comb.IN1
|
||||
PHI0 => nWEr.CLK
|
||||
PHI0 => RAMSpecSELr.CLK
|
||||
PHI0 => ROMSpecSELr.CLK
|
||||
PHI0 => PHI0r1.DATAIN
|
||||
nRES => nRESr0.DATAIN
|
||||
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
@ -110,61 +110,60 @@ nDEVSEL => RAMSEL.IN1
|
||||
nDEVSEL => comb.IN1
|
||||
nIOSTRB => comb.IN1
|
||||
nIOSTRB => always5.IN1
|
||||
SetRF => MOSIout.DATAB
|
||||
SetRF => always10.IN1
|
||||
SetRF => SA.OUTPUTSELECT
|
||||
SetRF => SA.OUTPUTSELECT
|
||||
SetRF => SA.OUTPUTSELECT
|
||||
SetRF => SBA.IN1
|
||||
SetRF => always10.IN1
|
||||
SetLim8M => SBA.IN1
|
||||
SetFW[0] => Mux1.IN10
|
||||
SetFW[0] => Equal18.IN1
|
||||
SetFW[0] => Equal19.IN1
|
||||
SetFW[1] => MOSIout.DATAB
|
||||
SetFW[1] => comb.IN1
|
||||
SetFW[1] => Equal18.IN0
|
||||
SetFW[1] => Equal19.IN0
|
||||
RA[0] => DQML.DATAA
|
||||
RA[0] => Equal6.IN3
|
||||
RA[0] => Equal9.IN1
|
||||
RA[0] => Equal10.IN3
|
||||
RA[0] => Equal11.IN0
|
||||
RA[0] => Equal12.IN3
|
||||
RA[0] => Equal13.IN10
|
||||
RA[0] => Equal11.IN3
|
||||
RA[0] => Equal12.IN0
|
||||
RA[0] => Equal13.IN3
|
||||
RA[0] => Equal14.IN10
|
||||
RA[0] => DQMH.DATAA
|
||||
RA[1] => SA.DATAA
|
||||
RA[1] => Equal6.IN2
|
||||
RA[1] => Equal9.IN0
|
||||
RA[1] => Equal10.IN0
|
||||
RA[1] => Equal11.IN3
|
||||
RA[1] => Equal12.IN2
|
||||
RA[1] => Equal13.IN9
|
||||
RA[1] => Equal11.IN0
|
||||
RA[1] => Equal12.IN3
|
||||
RA[1] => Equal13.IN2
|
||||
RA[1] => Equal14.IN9
|
||||
RA[2] => SA.DATAA
|
||||
RA[2] => Equal6.IN1
|
||||
RA[2] => Equal9.IN3
|
||||
RA[2] => Equal10.IN2
|
||||
RA[2] => Equal11.IN2
|
||||
RA[2] => Equal12.IN1
|
||||
RA[2] => Equal13.IN8
|
||||
RA[2] => Equal12.IN2
|
||||
RA[2] => Equal13.IN1
|
||||
RA[2] => Equal14.IN8
|
||||
RA[3] => SA.DATAA
|
||||
RA[3] => Equal6.IN0
|
||||
RA[3] => Equal9.IN2
|
||||
RA[3] => Equal10.IN1
|
||||
RA[3] => Equal11.IN1
|
||||
RA[3] => Equal12.IN0
|
||||
RA[3] => Equal13.IN7
|
||||
RA[3] => Equal12.IN1
|
||||
RA[3] => Equal13.IN0
|
||||
RA[3] => Equal14.IN7
|
||||
RA[4] => SA.DATAA
|
||||
RA[4] => Equal13.IN6
|
||||
RA[4] => Equal14.IN6
|
||||
RA[5] => SA.DATAA
|
||||
RA[5] => Equal13.IN5
|
||||
RA[5] => Equal14.IN5
|
||||
RA[6] => SA.DATAA
|
||||
RA[6] => Equal13.IN4
|
||||
RA[6] => Equal14.IN4
|
||||
RA[7] => comb.IN1
|
||||
RA[7] => SA.DATAA
|
||||
RA[7] => Equal13.IN3
|
||||
RA[7] => Equal14.IN3
|
||||
RA[8] => SA.DATAA
|
||||
RA[8] => Equal8.IN3
|
||||
RA[8] => Equal13.IN2
|
||||
RA[8] => Equal14.IN2
|
||||
RA[9] => SA.DATAA
|
||||
RA[9] => Equal8.IN2
|
||||
RA[9] => Equal13.IN1
|
||||
RA[9] => Equal14.IN1
|
||||
RA[10] => SA.DATAA
|
||||
RA[10] => Equal8.IN1
|
||||
RA[10] => Equal13.IN0
|
||||
RA[10] => Equal14.IN0
|
||||
RA[11] => SA.DATAA
|
||||
RA[11] => Equal8.IN0
|
||||
RA[12] => Equal7.IN3
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,18 +1,18 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429527039 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:06 2021 " "Processing started: Mon Mar 22 12:12:06 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616429528633 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(80) " "Verilog HDL warning at GR8RAM.v(80): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 80 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616429528805 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(255) " "Verilog HDL warning at GR8RAM.v(255): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 255 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616429528805 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616429528805 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616429528805 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616429528914 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(104) " "Verilog HDL assignment warning at GR8RAM.v(104): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(112) " "Verilog HDL assignment warning at GR8RAM.v(112): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 112 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(119) " "Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 119 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(306) " "Verilog HDL assignment warning at GR8RAM.v(306): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 306 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528930 "|GR8RAM"}
|
||||
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1616429530336 ""}
|
||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1616429531165 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "304 " "Implemented 304 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_LCELLS" "235 " "Implemented 235 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616429531211 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616429531211 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616429531352 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:11 2021 " "Processing ended: Mon Mar 22 12:12:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161736158 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:15 2021 " "Processing started: Sun Apr 11 13:22:15 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161737908 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618161738314 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738330 "|GR8RAM"}
|
||||
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618161740127 ""}
|
||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618161740877 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618161740986 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618161740986 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618161741470 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:21 2021 " "Processing ended: Sun Apr 11 13:22:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""}
|
||||
|
||||
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0
cpld/db/GR8RAM.quiproj.1680.rdr.flock
Executable file
0
cpld/db/GR8RAM.quiproj.1680.rdr.flock
Executable file
Binary file not shown.
Binary file not shown.
Binary file not shown.
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@ -1,23 +1,23 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429549056 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:27 2021 " "Processing started: Mon Mar 22 12:12:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616429549087 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616429549337 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616429550197 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616429550353 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616429550353 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616429550525 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616429550962 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616429551103 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616429551118 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616429551243 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.843 " "Worst-case setup slack is -9.843" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.843 -651.483 C25M " " -9.843 -651.483 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.395 " "Worst-case hold slack is 1.395" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.395 0.000 C25M " " 1.395 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -132.120 C25M " " -4.404 -132.120 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616429551415 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616429551525 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616429551525 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:31 2021 " "Processing ended: Mon Mar 22 12:12:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161764909 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:43 2021 " "Processing started: Sun Apr 11 13:22:43 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618161765159 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161765987 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618161766331 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618161766815 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618161767003 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618161767003 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618161767050 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618161767331 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.908 -697.920 C25M " " -9.908 -697.920 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.302 -1.302 PHI0 " " -1.302 -1.302 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.012 0.000 PHI0 " " 1.012 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.288 0.000 C25M " " 1.288 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.389 -131.670 C25M " " -4.389 -131.670 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.835 0.000 C25M " " 4.835 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618161767706 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:48 2021 " "Processing ended: Sun Apr 11 13:22:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""}
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
start_full_compilation:s:00:00:27
|
||||
start_full_compilation:s:00:00:32
|
||||
start_analysis_synthesis:s:00:00:07-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:10-start_full_compilation
|
||||
start_assembler:s:00:00:04-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:06-start_full_compilation
|
||||
start_fitter:s:00:00:12-start_full_compilation
|
||||
start_assembler:s:00:00:06-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:07-start_full_compilation
|
||||
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because one or more lines are too long
Binary file not shown.
@ -1,5 +1,5 @@
|
||||
Assembler report for GR8RAM
|
||||
Mon Mar 22 12:12:25 2021
|
||||
Sun Apr 11 13:22:41 2021
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
@ -37,7 +37,7 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Mon Mar 22 12:12:25 2021 ;
|
||||
; Assembler Status ; Successful - Sun Apr 11 13:22:41 2021 ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
@ -90,8 +90,8 @@ applicable agreement for further details.
|
||||
; Option ; Setting ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
; Device ; EPM240T100C5 ;
|
||||
; JTAG usercode ; 0x00166EAF ;
|
||||
; Checksum ; 0x0016711F ;
|
||||
; JTAG usercode ; 0x00162982 ;
|
||||
; Checksum ; 0x00162E02 ;
|
||||
+----------------+-------------------------------------------------------+
|
||||
|
||||
|
||||
@ -101,14 +101,14 @@ applicable agreement for further details.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Assembler
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Mon Mar 22 12:12:23 2021
|
||||
Info: Processing started: Sun Apr 11 13:22:38 2021
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 293 megabytes
|
||||
Info: Processing ended: Mon Mar 22 12:12:25 2021
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
Info: Processing ended: Sun Apr 11 13:22:41 2021
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:03
|
||||
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Mon Mar 22 12:12:32 2021
|
||||
Sun Apr 11 13:22:49 2021
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,11 +1,11 @@
|
||||
Fitter Status : Successful - Mon Mar 22 12:12:21 2021
|
||||
Fitter Status : Successful - Sun Apr 11 13:22:34 2021
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 223 / 240 ( 93 % )
|
||||
Total logic elements : 227 / 240 ( 95 % )
|
||||
Total pins : 69 / 80 ( 86 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 0 / 1 ( 0 % )
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Flow report for GR8RAM
|
||||
Mon Mar 22 12:12:31 2021
|
||||
Sun Apr 11 13:22:47 2021
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
@ -40,14 +40,14 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+---------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Mon Mar 22 12:12:25 2021 ;
|
||||
; Flow Status ; Successful - Sun Apr 11 13:22:41 2021 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 223 / 240 ( 93 % ) ;
|
||||
; Total logic elements ; 227 / 240 ( 95 % ) ;
|
||||
; Total pins ; 69 / 80 ( 86 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||
@ -59,7 +59,7 @@ applicable agreement for further details.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 03/22/2021 12:12:08 ;
|
||||
; Start date & time ; 04/11/2021 13:22:17 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
+-------------------+---------------------+
|
||||
@ -75,9 +75,11 @@ applicable agreement for further details.
|
||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
||||
; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
|
||||
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 44085571633675.161642952802820 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 44085571633675.161816173700648 ; -- ; -- ; -- ;
|
||||
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
|
||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
||||
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
|
||||
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ;
|
||||
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
@ -100,11 +102,11 @@ applicable agreement for further details.
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ;
|
||||
; Fitter ; 00:00:08 ; 1.5 ; 373 MB ; 00:00:08 ;
|
||||
; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 286 MB ; 00:00:04 ;
|
||||
; Total ; 00:00:19 ; -- ; -- ; 00:00:19 ;
|
||||
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ;
|
||||
; Fitter ; 00:00:10 ; 1.4 ; 382 MB ; 00:00:09 ;
|
||||
; Assembler ; 00:00:03 ; 1.0 ; 292 MB ; 00:00:03 ;
|
||||
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 278 MB ; 00:00:04 ;
|
||||
; Total ; 00:00:23 ; -- ; -- ; 00:00:22 ;
|
||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="73ef203dd7199fdf781e"/>
|
||||
<hash md5_digest_80b="a474eff98051f7f4d66b"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for GR8RAM
|
||||
Mon Mar 22 12:12:11 2021
|
||||
Sun Apr 11 13:22:21 2021
|
||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
|
||||
|
||||
@ -45,12 +45,12 @@ applicable agreement for further details.
|
||||
+-------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Mon Mar 22 12:12:11 2021 ;
|
||||
; Analysis & Synthesis Status ; Successful - Sun Apr 11 13:22:21 2021 ;
|
||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||
; Revision Name ; GR8RAM ;
|
||||
; Top-level Entity Name ; GR8RAM ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 235 ;
|
||||
; Total logic elements ; 240 ;
|
||||
; Total pins ; 69 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||
@ -161,20 +161,20 @@ applicable agreement for further details.
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 235 ;
|
||||
; -- Combinational with no register ; 133 ;
|
||||
; -- Register only ; 13 ;
|
||||
; -- Combinational with a register ; 89 ;
|
||||
; Total logic elements ; 240 ;
|
||||
; -- Combinational with no register ; 138 ;
|
||||
; -- Register only ; 14 ;
|
||||
; -- Combinational with a register ; 88 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 122 ;
|
||||
; -- 3 input functions ; 36 ;
|
||||
; -- 2 input functions ; 64 ;
|
||||
; -- 4 input functions ; 130 ;
|
||||
; -- 3 input functions ; 30 ;
|
||||
; -- 2 input functions ; 66 ;
|
||||
; -- 1 input functions ; 0 ;
|
||||
; -- 0 input functions ; 0 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 202 ;
|
||||
; -- normal mode ; 207 ;
|
||||
; -- arithmetic mode ; 33 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
@ -185,9 +185,9 @@ applicable agreement for further details.
|
||||
; Total logic cells in carry chains ; 37 ;
|
||||
; I/O pins ; 69 ;
|
||||
; Maximum fan-out node ; C25M ;
|
||||
; Maximum fan-out ; 102 ;
|
||||
; Total fan-out ; 1020 ;
|
||||
; Average fan-out ; 3.36 ;
|
||||
; Maximum fan-out ; 99 ;
|
||||
; Total fan-out ; 1036 ;
|
||||
; Average fan-out ; 3.35 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
@ -196,7 +196,7 @@ applicable agreement for further details.
|
||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
|
||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
||||
; |GR8RAM ; 235 (235) ; 102 ; 0 ; 69 ; 0 ; 133 (133) ; 13 (13) ; 89 (89) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
|
||||
; |GR8RAM ; 240 (240) ; 102 ; 0 ; 69 ; 0 ; 138 (138) ; 14 (14) ; 88 (88) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
|
||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
@ -236,7 +236,7 @@ Encoding Type: Minimal Bits
|
||||
; Number of registers using Synchronous Load ; 25 ;
|
||||
; Number of registers using Asynchronous Clear ; 30 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 32 ;
|
||||
; Number of registers using Clock Enable ; 29 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@ -281,30 +281,30 @@ Encoding Type: Minimal Bits
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Info: Processing started: Mon Mar 22 12:12:06 2021
|
||||
Info: Processing started: Sun Apr 11 13:22:15 2021
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||
Info (12023): Found entity 1: GR8RAM
|
||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(104): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(112): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(306): truncated value with size 32 to match size of target (4)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)
|
||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)
|
||||
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
|
||||
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
||||
Info (21057): Implemented 304 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 309 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 26 input pins
|
||||
Info (21059): Implemented 26 output pins
|
||||
Info (21060): Implemented 17 bidirectional pins
|
||||
Info (21061): Implemented 235 logic cells
|
||||
Info (21061): Implemented 240 logic cells
|
||||
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 301 megabytes
|
||||
Info: Processing ended: Mon Mar 22 12:12:11 2021
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
Info: Processing ended: Sun Apr 11 13:22:21 2021
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:06
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(80): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(255): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(79): extended using "x" or "z"
|
||||
Warning (10273): Verilog HDL warning at GR8RAM.v(256): extended using "x" or "z"
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
Analysis & Synthesis Status : Successful - Mon Mar 22 12:12:11 2021
|
||||
Analysis & Synthesis Status : Successful - Sun Apr 11 13:22:21 2021
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : GR8RAM
|
||||
Top-level Entity Name : GR8RAM
|
||||
Family : MAX II
|
||||
Total logic elements : 235
|
||||
Total logic elements : 240
|
||||
Total pins : 69
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 0 / 1 ( 0 % )
|
||||
|
||||
@ -62,103 +62,103 @@ CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
SBA[0] : 1 : output : 3.3-V LVTTL : : 2 : N
|
||||
nCAS : 2 : output : 3.3-V LVTTL : : 1 : N
|
||||
MOSI : 3 : bidir : 3.3-V LVTTL : : 1 : N
|
||||
nRAS : 4 : output : 3.3-V LVTTL : : 1 : N
|
||||
nRCS : 5 : output : 3.3-V LVTTL : : 1 : N
|
||||
nRES : 6 : input : 3.3-V LVTTL : : 1 : N
|
||||
RCKE : 7 : output : 3.3-V LVTTL : : 1 : N
|
||||
SetLim8M : 8 : input : 3.3-V LVTTL : : 1 : N
|
||||
RA[4] : 1 : input : 3.3-V LVTTL : : 2 : Y
|
||||
RA[5] : 2 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[6] : 3 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[3] : 4 : input : 3.3-V LVTTL : : 1 : Y
|
||||
nFCS : 5 : output : 3.3-V LVTTL : : 1 : Y
|
||||
RA[7] : 6 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[8] : 7 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[9] : 8 : input : 3.3-V LVTTL : : 1 : Y
|
||||
VCCIO1 : 9 : power : : 3.3V : 1 :
|
||||
GNDIO : 10 : gnd : : : :
|
||||
GNDINT : 11 : gnd : : : :
|
||||
nDEVSEL : 12 : input : 3.3-V LVTTL : : 1 : N
|
||||
FCK : 12 : output : 3.3-V LVTTL : : 1 : Y
|
||||
VCCINT : 13 : power : : 2.5V/3.3V : :
|
||||
C25M : 14 : input : 3.3-V LVTTL : : 1 : N
|
||||
SD[2] : 15 : bidir : 3.3-V LVTTL : : 1 : N
|
||||
RA[10] : 16 : input : 3.3-V LVTTL : : 1 : N
|
||||
SD[1] : 17 : bidir : 3.3-V LVTTL : : 1 : N
|
||||
RA[8] : 18 : input : 3.3-V LVTTL : : 1 : N
|
||||
RA[7] : 19 : input : 3.3-V LVTTL : : 1 : N
|
||||
RA[11] : 20 : input : 3.3-V LVTTL : : 1 : N
|
||||
RA[9] : 21 : input : 3.3-V LVTTL : : 1 : N
|
||||
RA[10] : 14 : input : 3.3-V LVTTL : : 1 : Y
|
||||
MOSI : 15 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
MISO : 16 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RDdir : 17 : output : 3.3-V LVTTL : : 1 : N
|
||||
GND* : 18 : : : : 1 :
|
||||
GND* : 19 : : : : 1 :
|
||||
GND* : 20 : : : : 1 :
|
||||
GND* : 21 : : : : 1 :
|
||||
TMS : 22 : input : : : 1 :
|
||||
TDI : 23 : input : : : 1 :
|
||||
TCK : 24 : input : : : 1 :
|
||||
TDO : 25 : output : : : 1 :
|
||||
GND* : 26 : : : : 1 :
|
||||
nFCS : 27 : output : 3.3-V LVTTL : : 1 : N
|
||||
GND* : 27 : : : : 1 :
|
||||
GND* : 28 : : : : 1 :
|
||||
GND* : 29 : : : : 1 :
|
||||
SBA[1] : 30 : output : 3.3-V LVTTL : : 1 : N
|
||||
nRESout : 30 : output : 3.3-V LVTTL : : 1 : Y
|
||||
VCCIO1 : 31 : power : : 3.3V : 1 :
|
||||
GNDIO : 32 : gnd : : : :
|
||||
SD[3] : 33 : bidir : 3.3-V LVTTL : : 1 : N
|
||||
SD[0] : 34 : bidir : 3.3-V LVTTL : : 1 : N
|
||||
SA[2] : 35 : output : 3.3-V LVTTL : : 1 : N
|
||||
FCK : 36 : output : 3.3-V LVTTL : : 1 : N
|
||||
SA[1] : 37 : output : 3.3-V LVTTL : : 1 : N
|
||||
SA[0] : 38 : output : 3.3-V LVTTL : : 1 : N
|
||||
SA[5] : 39 : output : 3.3-V LVTTL : : 1 : N
|
||||
RA[6] : 40 : input : 3.3-V LVTTL : : 1 : N
|
||||
RA[4] : 41 : input : 3.3-V LVTTL : : 1 : N
|
||||
nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : N
|
||||
SA[3] : 43 : output : 3.3-V LVTTL : : 1 : N
|
||||
SA[6] : 44 : output : 3.3-V LVTTL : : 1 : N
|
||||
GND* : 33 : : : : 1 :
|
||||
RA[11] : 34 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[12] : 35 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[13] : 36 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[14] : 37 : input : 3.3-V LVTTL : : 1 : Y
|
||||
RA[15] : 38 : input : 3.3-V LVTTL : : 1 : Y
|
||||
nIOSEL : 39 : input : 3.3-V LVTTL : : 1 : Y
|
||||
nDEVSEL : 40 : input : 3.3-V LVTTL : : 1 : Y
|
||||
PHI0 : 41 : input : 3.3-V LVTTL : : 1 : Y
|
||||
nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : Y
|
||||
nWE : 43 : input : 3.3-V LVTTL : : 1 : Y
|
||||
nRES : 44 : input : 3.3-V LVTTL : : 1 : Y
|
||||
VCCIO1 : 45 : power : : 3.3V : 1 :
|
||||
GNDIO : 46 : gnd : : : :
|
||||
GND* : 47 : : : : 1 :
|
||||
SA[7] : 48 : output : 3.3-V LVTTL : : 1 : N
|
||||
SD[1] : 47 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
GND* : 48 : : : : 1 :
|
||||
GND* : 49 : : : : 1 :
|
||||
GND* : 50 : : : : 1 :
|
||||
GND* : 51 : : : : 1 :
|
||||
RD[0] : 52 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
RA[3] : 53 : input : 3.3-V LVTTL : : 2 : N
|
||||
RD[3] : 54 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
RDdir : 55 : output : 3.3-V LVTTL : : 2 : N
|
||||
RA[2] : 56 : input : 3.3-V LVTTL : : 2 : N
|
||||
RD[2] : 57 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
SA[8] : 58 : output : 3.3-V LVTTL : : 2 : N
|
||||
SD[0] : 50 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
SD[4] : 51 : bidir : 3.3-V LVTTL : : 1 : Y
|
||||
SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
SD[6] : 53 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
SD[7] : 54 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
SD[3] : 55 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
SD[2] : 56 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
DQMH : 57 : output : 3.3-V LVTTL : : 2 : Y
|
||||
nSWE : 58 : output : 3.3-V LVTTL : : 2 : Y
|
||||
VCCIO2 : 59 : power : : 3.3V : 2 :
|
||||
GNDIO : 60 : gnd : : : :
|
||||
RD[1] : 61 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
RA[5] : 62 : input : 3.3-V LVTTL : : 2 : N
|
||||
nCAS : 61 : output : 3.3-V LVTTL : : 2 : Y
|
||||
nRAS : 62 : output : 3.3-V LVTTL : : 2 : Y
|
||||
VCCINT : 63 : power : : 2.5V/3.3V : :
|
||||
RA[1] : 64 : input : 3.3-V LVTTL : : 2 : N
|
||||
C25M : 64 : input : 3.3-V LVTTL : : 2 : Y
|
||||
GNDINT : 65 : gnd : : : :
|
||||
nIOSEL : 66 : input : 3.3-V LVTTL : : 2 : N
|
||||
RA[0] : 67 : input : 3.3-V LVTTL : : 2 : N
|
||||
SetRF : 68 : input : 3.3-V LVTTL : : 2 : N
|
||||
GND* : 69 : : : : 2 :
|
||||
SA[11] : 70 : output : 3.3-V LVTTL : : 2 : N
|
||||
SA[9] : 71 : output : 3.3-V LVTTL : : 2 : N
|
||||
RA[13] : 72 : input : 3.3-V LVTTL : : 2 : N
|
||||
RA[12] : 73 : input : 3.3-V LVTTL : : 2 : N
|
||||
RA[15] : 74 : input : 3.3-V LVTTL : : 2 : N
|
||||
RA[14] : 75 : input : 3.3-V LVTTL : : 2 : N
|
||||
SA[12] : 76 : output : 3.3-V LVTTL : : 2 : N
|
||||
GND* : 77 : : : : 2 :
|
||||
GND* : 78 : : : : 2 :
|
||||
RCKE : 66 : output : 3.3-V LVTTL : : 2 : Y
|
||||
nRCS : 67 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[12] : 68 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SBA[0] : 69 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[11] : 70 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SBA[1] : 71 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[9] : 72 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[10] : 73 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[8] : 74 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[0] : 75 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[4] : 76 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[6] : 77 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[7] : 78 : output : 3.3-V LVTTL : : 2 : Y
|
||||
GNDIO : 79 : gnd : : : :
|
||||
VCCIO2 : 80 : power : : 3.3V : 2 :
|
||||
RD[5] : 81 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
RD[6] : 82 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
RD[7] : 83 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
RD[4] : 84 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
SA[10] : 85 : output : 3.3-V LVTTL : : 2 : N
|
||||
DQML : 86 : output : 3.3-V LVTTL : : 2 : N
|
||||
DQMH : 87 : output : 3.3-V LVTTL : : 2 : N
|
||||
PHI0 : 88 : input : 3.3-V LVTTL : : 2 : N
|
||||
nSWE : 89 : output : 3.3-V LVTTL : : 2 : N
|
||||
nWE : 90 : input : 3.3-V LVTTL : : 2 : N
|
||||
SA[4] : 91 : output : 3.3-V LVTTL : : 2 : N
|
||||
SD[5] : 92 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
SA[1] : 81 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[2] : 82 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[5] : 83 : output : 3.3-V LVTTL : : 2 : Y
|
||||
SA[3] : 84 : output : 3.3-V LVTTL : : 2 : Y
|
||||
DQML : 85 : output : 3.3-V LVTTL : : 2 : Y
|
||||
RD[0] : 86 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
RD[1] : 87 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
RD[2] : 88 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
RD[3] : 89 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
RD[4] : 90 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
RD[5] : 91 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
RD[6] : 92 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
GNDIO : 93 : gnd : : : :
|
||||
VCCIO2 : 94 : power : : 3.3V : 2 :
|
||||
SD[6] : 95 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
SD[4] : 96 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
SD[7] : 97 : bidir : 3.3-V LVTTL : : 2 : N
|
||||
MISO : 98 : input : 3.3-V LVTTL : : 2 : N
|
||||
nRESout : 99 : output : 3.3-V LVTTL : : 2 : N
|
||||
GND* : 100 : : : : 2 :
|
||||
SetFW[1] : 95 : input : 3.3-V LVTTL : : 2 : Y
|
||||
SetFW[0] : 96 : input : 3.3-V LVTTL : : 2 : Y
|
||||
RA[2] : 97 : input : 3.3-V LVTTL : : 2 : Y
|
||||
RA[1] : 98 : input : 3.3-V LVTTL : : 2 : Y
|
||||
RD[7] : 99 : bidir : 3.3-V LVTTL : : 2 : Y
|
||||
RA[0] : 100 : input : 3.3-V LVTTL : : 2 : Y
|
||||
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -3,23 +3,35 @@ TimeQuest Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'C25M'
|
||||
Slack : -9.843
|
||||
TNS : -651.483
|
||||
Slack : -9.908
|
||||
TNS : -697.920
|
||||
|
||||
Type : Setup 'PHI0'
|
||||
Slack : -1.302
|
||||
TNS : -1.302
|
||||
|
||||
Type : Hold 'PHI0'
|
||||
Slack : 1.012
|
||||
TNS : 0.000
|
||||