2 Commits

Author	SHA1	Message	Date
Zane Kaminski	9f0867fe56	reset button detect	2020-10-25 05:22:14 -04:00
Zane Kaminski	f471e04244	New PLD revision ... For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.	2019-10-18 15:07:38 -04:00