forked from Apple-2-HW/GR8RAM
301 lines
9.2 KiB
Plaintext
301 lines
9.2 KiB
Plaintext
Init sequence
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Init State SDRAM Flash IS Other
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--------------------------------------------------------------------------------
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$000000-$0FFFBF Wait for Vcc Wait for Vcc 0
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$000000 NOP CKE /CS hi, CLK lo
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...
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$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFFAF NOP CKE /CS lo, CLK lo
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$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03) 1
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$0FFFB0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFB1 NOP CKE CLK hi
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$0FFFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFB3 PC all CLK hi
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$0FFFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFB5 NOP CKE CLK hi
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$0FFFB6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFB7 NOP CKE CLK hi
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$0FFFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFB9 NOP CKE CLK hi
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$0FFFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFBB Load mode CLK hi
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$0FFFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFFBD NOP CKE CLK hi
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$0FFFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFFBF NOP CKE CLK hi
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$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000) 2
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$0FFFC0 NOP CKE CLK lo, MOSI 0 (b23)
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$0FFFC1 NOP CKE CLK hi
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$0FFFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFFC3 AREF CLK hi
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$0FFFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
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$0FFFC5 NOP CKE CLK hi
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$0FFFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFFC7 NOP CKE CLK hi
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$0FFFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFFC9 NOP CKE CLK hi
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$0FFFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFFCB AREF CLK hi
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$0FFFCC NOP CKE CLK lo, MOSI 0 (b17)
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$0FFFCD NOP CKE CLK hi
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$0FFFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFFCF NOP CKE CLK hi
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$0FFFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFFD1 NOP CKE CLK hi
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$0FFFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFFD3 AREF CLK hi
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$0FFFD4 NOP CKE CLK lo, MOSI 0 (b13)
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$0FFFD5 NOP CKE CLK hi
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$0FFFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFFD7 NOP CKE CLK hi
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$0FFFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFFD9 NOP CKE CLK hi
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$0FFFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFFDB AREF CLK hi
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$0FFFDC NOP CKE CLK lo, MOSI 0 (b9)
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$0FFFDD NOP CKE CLK hi
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$0FFFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFFDF NOP CKE CLK hi
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$0FFFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFE1 NOP CKE CLK hi
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$0FFFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFE3 AREF CLK hi
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$0FFFE4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFE5 NOP CKE CLK hi
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$0FFFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFE7 NOP CKE CLK hi
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$0FFFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFE9 NOP CKE CLK hi
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$0FFFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFEB AREF CLK hi
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$0FFFEC NOP CKE CLK lo, MOSI 0 (b1)
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$0FFFED NOP CKE CLK hi
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$0FFFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFFEF NOP CKE CLK hi
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$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks 2
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$0FFFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFFF1 NOP CKE CLK hi
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$0FFFF2 NOP CKE CLK lo
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$0FFFF3 AREF CLK hi
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$0FFFF4 NOP CKE CLK lo
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$0FFFF5 NOP CKE CLK hi
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$0FFFF6 NOP CKE CLK lo
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$0FFFF7 NOP CKE CLK hi
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$0FFFF8 NOP CKE CLK lo
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$0FFFF9 NOP CKE CLK hi
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$0FFFFA NOP CKE CLK lo
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$0FFFFB AREF CLK hi
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$0FFFFC NOP CKE CLK lo
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$0FFFFD NOP CKE CLK hi
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$0FFFFE NOP CKE CLK lo
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$0FFFFF NOP CKE CLK hi
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$100000-$503FFF Write ROM data Shift in read data 3
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$100000 NOP CKE CLK lo
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$100001 NOP CKE CLK hi, get b7:6 of $000000
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$100002 NOP CKE CLK lo
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$100003 AREF CLK hi, get b5:4 of $000000
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$100004 NOP CKE CLK lo
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$100005 ACT CLK hi, get b3:2 of $000000
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$100006 NOP CKE CLK lo
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$100007 WR AP CLK hi, get b1:0 of $000000
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$100008 NOP CKE CLK lo
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$100009 NOP CKE CLK hi, get b7:6 of $000001
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$10000A NOP CKE CLK lo
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$10000B AREF CLK hi, get b5:4 of $000001
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$10000C NOP CKE CLK lo
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$10000D ACT CLK hi, get b3:2 of $000001
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$10000E NOP CKE CLK lo
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$10000F WR AP CLK hi, get b1:0 of $000001
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...
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$503FF0 NOP CKE CLK lo
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$503FF1 NOP CKE CLK hi, get b7:6 of $0807FE
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$503FF2 NOP CKE CLK lo
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$503FF3 AREF CLK hi, get b5:4 of $0807FE
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$503FF4 NOP CKE CLK lo
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$503FF5 ACT CLK hi, get b3:2 of $0807FE
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$503FF6 NOP CKE CLK lo
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$503FF7 WR AP CLK hi, get b1:0 of $0807FE
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$503FF8 NOP CKE CLK lo
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$503FF9 NOP CKE CLK hi, get b7:6 of $0807FF
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$503FFA NOP CKE CLK lo
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$503FFB AREF CLK hi, get b5:4 of $0807FF
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$503FFC NOP CKE CLK lo
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$503FFD ACT CLK hi, get b3:2 of $0807FF
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$503FFE NOP CKE CLK lo
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$503FFF WR AP CLK hi, get b1:0 of $0807FF
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$504000 NOP CKE CLK lo, /CS hi 3
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$504001 NOP CKE CLK lo, /CS hi 3
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$504002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
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...
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$5F5E0F flip 1hz, wrap
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Init sequence
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Init State SDRAM Flash IS Other
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--------------------------------------------------------------------------------
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$00000-$0FFBF Nothing Nothing 0
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$00000 NOP CKE /CS hi, CLK lo
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...
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$0FF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFAF NOP CKE /CS lo, CLK lo
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$0FFB0-$0FFBF Init: Precharge Send read cmd ($03) 1
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$0FFB0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFB1 NOP CKE CLK hi
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$0FFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFB3 PC all CLK hi
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$0FFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFB5 NOP CKE CLK hi
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$0FFB6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFB7 NOP CKE CLK hi
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$0FFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFB9 NOP CKE CLK hi
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$0FFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFBB Load mode CLK hi
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$0FFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFBD NOP CKE CLK hi
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$0FFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFBF NOP CKE CLK hi
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$0FFC0-$0FFEF Init: mode & ref Send address ($000000) 2
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$0FFC0 NOP CKE CLK lo, MOSI 0 (b23)
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$0FFC1 NOP CKE CLK hi
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$0FFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFC3 AREF CLK hi
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$0FFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
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$0FFC5 NOP CKE CLK hi
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$0FFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFC7 NOP CKE CLK hi
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$0FFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFC9 NOP CKE CLK hi
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$0FFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFCB AREF CLK hi
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$0FFCC NOP CKE CLK lo, MOSI 0 (b17)
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$0FFCD NOP CKE CLK hi
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$0FFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFCF NOP CKE CLK hi
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$0FFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFD1 NOP CKE CLK hi
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$0FFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFD3 AREF CLK hi
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$0FFD4 NOP CKE CLK lo, MOSI 0 (b13)
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$0FFD5 NOP CKE CLK hi
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$0FFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFD7 NOP CKE CLK hi
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$0FFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFD9 NOP CKE CLK hi
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$0FFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFDB AREF CLK hi
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$0FFDC NOP CKE CLK lo, MOSI 0 (b9)
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$0FFDD NOP CKE CLK hi
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$0FFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFDF NOP CKE CLK hi
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$0FFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFE1 NOP CKE CLK hi
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$0FFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFE3 AREF CLK hi
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$0FFE4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFE5 NOP CKE CLK hi
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$0FFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFE7 NOP CKE CLK hi
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$0FFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFE9 NOP CKE CLK hi
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$0FFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFEB AREF CLK hi
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$0FFEC NOP CKE CLK lo, MOSI 0 (b1)
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$0FFED NOP CKE CLK hi
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$0FFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFEF NOP CKE CLK hi
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$0FFF0-$0FFFF Init: mode & ref 8 dummy clocks 2
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$0FFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFF1 NOP CKE CLK hi
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$0FFF2 NOP CKE CLK lo
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$0FFF3 AREF CLK hi
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$0FFF4 NOP CKE CLK lo
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$0FFF5 NOP CKE CLK hi
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$0FFF6 NOP CKE CLK lo
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$0FFF7 NOP CKE CLK hi
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$0FFF8 NOP CKE CLK lo
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$0FFF9 NOP CKE CLK hi
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$0FFFA NOP CKE CLK lo
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$0FFFB AREF CLK hi
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$0FFFC NOP CKE CLK lo
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$0FFFD NOP CKE CLK hi
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$0FFFE NOP CKE CLK lo
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$0FFFF NOP CKE CLK hi
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$10000-$2FFFF Write ROM data Shift in read data 3
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$10000 NOP CKE CLK lo
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$10001 NOP CKE CLK hi, get b7:6 of $000000
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$10002 NOP CKE CLK lo
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$10003 AREF CLK hi, get b5:4 of $000000
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$10004 NOP CKE CLK lo
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$10005 ACT CLK hi, get b3:2 of $000000
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$10006 NOP CKE CLK lo
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$10007 WR AP CLK hi, get b1:0 of $000000
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$10008 NOP CKE CLK lo
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$10009 NOP CKE CLK hi, get b7:6 of $000001
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$1000A NOP CKE CLK lo
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$1000B AREF CLK hi, get b5:4 of $000001
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$1000C NOP CKE CLK lo
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$1000D ACT CLK hi, get b3:2 of $000001
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$1000E NOP CKE CLK lo
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$1000F WR AP CLK hi, get b1:0 of $000001
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...
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$2FFF0 NOP CKE CLK lo
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$2FFF1 NOP CKE CLK hi, get b7:6 of $003FFE
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$2FFF2 NOP CKE CLK lo
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$2FFF3 AREF CLK hi, get b5:4 of $003FFE
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$2FFF4 NOP CKE CLK lo
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$2FFF5 ACT CLK hi, get b3:2 of $003FFE
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$2FFF6 NOP CKE CLK lo
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$2FFF7 WR AP CLK hi, get b1:0 of $003FFE
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$2FFF8 NOP CKE CLK lo
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$2FFF9 NOP CKE CLK hi, get b7:6 of $003FFF
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$2FFFA NOP CKE CLK lo
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$2FFFB AREF CLK hi, get b5:4 of $003FFF
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$2FFFC NOP CKE CLK lo
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$2FFFD ACT CLK hi, get b3:2 of $003FFF
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$2FFFE NOP CKE CLK lo
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$2FFFF WR AP CLK hi, get b1:0 of $003FFF
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$30000 NOP CKE CLK lo, /CS hi 3
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$30001 NOP CKE CLK lo, /CS hi 3
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$30002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
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