forked from Apple-2-HW/GR8RAM
ugh
This commit is contained in:
Zane Kaminski
parent
a444cc31aa
commit
3816ecd0a1
@ -1,21 +1,21 @@
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Init sequence
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Init State SDRAM Flash Other
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Init State SDRAM Flash IS Other
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--------------------------------------------------------------------------------
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$000000-$0FFFBF Wait for Vcc Wait for Vcc
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$000000-$0FFFBF Wait for Vcc Wait for Vcc 0
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$000000 NOP CKE /CS hi, CLK lo
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...
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$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFFAF NOP CKE /CS lo, CLK lo
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$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03)
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$0FFFB0 PC all CLK lo, MOSI 0 (b7)
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$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03) 1
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$0FFFB0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFB1 NOP CKE CLK hi
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$0FFFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFB3 NOP CKE CLK hi
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$0FFFB3 PC all CLK hi
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$0FFFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFB5 NOP CKE CLK hi
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$0FFFB6 NOP CKE CLK lo, MOSI 0 (b4)
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@ -23,118 +23,278 @@ $0FFFB7 NOP CKE CLK hi
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$0FFFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFB9 NOP CKE CLK hi
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$0FFFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFBB NOP CKE CLK hi
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$0FFFBB Load mode CLK hi
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$0FFFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFFBD NOP CKE CLK hi
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$0FFFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFFBF NOP CKE CLK hi
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$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000)
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$0FFFC0 Load mode CLK lo, MOSI 0 (b23)
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$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000) 2
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$0FFFC0 NOP CKE CLK lo, MOSI 0 (b23)
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$0FFFC1 NOP CKE CLK hi
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$0FFFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFFC3 NOP CKE CLK hi
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$0FFFC4 AREF CLK lo, MOSI Firmware[1] (b21)
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$0FFFC3 AREF CLK hi
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$0FFFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
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$0FFFC5 NOP CKE CLK hi
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$0FFFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFFC7 NOP CKE CLK hi
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$0FFFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFFC9 NOP CKE CLK hi
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$0FFFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFFCB NOP CKE CLK hi
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$0FFFCC AREF CLK lo, MOSI 0 (b17)
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$0FFFCB AREF CLK hi
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$0FFFCC NOP CKE CLK lo, MOSI 0 (b17)
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$0FFFCD NOP CKE CLK hi
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$0FFFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFFCF NOP CKE CLK hi
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$0FFFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFFD1 NOP CKE CLK hi
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$0FFFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFFD3 NOP CKE CLK hi
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$0FFFD4 AREF CLK lo, MOSI 0 (b13)
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$0FFFD3 AREF CLK hi
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$0FFFD4 NOP CKE CLK lo, MOSI 0 (b13)
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$0FFFD5 NOP CKE CLK hi
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$0FFFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFFD7 NOP CKE CLK hi
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$0FFFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFFD9 NOP CKE CLK hi
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$0FFFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFFDB NOP CKE CLK hi
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$0FFFDC AREF CLK lo, MOSI 0 (b9)
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$0FFFDB AREF CLK hi
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$0FFFDC NOP CKE CLK lo, MOSI 0 (b9)
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$0FFFDD NOP CKE CLK hi
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$0FFFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFFDF NOP CKE CLK hi
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$0FFFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFE1 NOP CKE CLK hi
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$0FFFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFE3 NOP CKE CLK hi
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$0FFFE4 AREF CLK lo, MOSI 0 (b5)
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$0FFFE3 AREF CLK hi
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$0FFFE4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFE5 NOP CKE CLK hi
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$0FFFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFE7 NOP CKE CLK hi
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$0FFFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFE9 NOP CKE CLK hi
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$0FFFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFEB NOP CKE CLK hi
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$0FFFEC AREF CLK lo, MOSI 0 (b1)
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$0FFFEB AREF CLK hi
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$0FFFEC NOP CKE CLK lo, MOSI 0 (b1)
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$0FFFED NOP CKE CLK hi
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$0FFFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFFEF NOP CKE CLK hi
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$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks
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$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks 2
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$0FFFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFFF1 NOP CKE CLK hi
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$0FFFF2 NOP CKE CLK lo
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$0FFFF3 NOP CKE CLK hi
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$0FFFF4 AREF CLK lo
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$0FFFF3 AREF CLK hi
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$0FFFF4 NOP CKE CLK lo
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$0FFFF5 NOP CKE CLK hi
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$0FFFF6 NOP CKE CLK lo
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$0FFFF7 NOP CKE CLK hi
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$0FFFF8 NOP CKE CLK lo
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$0FFFF9 NOP CKE CLK hi
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$0FFFFA NOP CKE CLK lo
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$0FFFFB NOP CKE CLK hi
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$0FFFFC AREF CLK lo
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$0FFFFB AREF CLK hi
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$0FFFFC NOP CKE CLK lo
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$0FFFFD NOP CKE CLK hi
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$0FFFFE NOP CKE CLK lo
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$0FFFFF NOP CKE CLK hi
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Write ROM data Shift in read data
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$100000-$503FFF Write ROM data Shift in read data 3
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$100000 NOP CKE CLK lo
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$100001 NOP CKE CLK hi, get b7:6 of $000000
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$100002 NOP CKE CLK lo
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$100003 NOP CKE CLK hi, get b5:4 of $000000
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$100004 AREF CLK lo
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$100005 NOP CKE CLK hi, get b3:2 of $000000
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$100006 ACT CLK lo
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$100007 NOP CKE CLK hi, get b1:0 of $000000
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$100008 WR AP CLK lo
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$100003 AREF CLK hi, get b5:4 of $000000
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$100004 NOP CKE CLK lo
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$100005 ACT CLK hi, get b3:2 of $000000
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$100006 NOP CKE CLK lo
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$100007 WR AP CLK hi, get b1:0 of $000000
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$100008 NOP CKE CLK lo
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$100009 NOP CKE CLK hi, get b7:6 of $000001
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$10000A NOP CKE CLK lo
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$10000B NOP CKE CLK hi, get b5:4 of $000001
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$10000C AREF CLK lo
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$10000D NOP CKE CLK hi, get b3:2 of $000001
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$10000E ACT CLK lo
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$10000F NOP CKE CLK hi, get b1:0 of $000001
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$10000B AREF CLK hi, get b5:4 of $000001
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$10000C NOP CKE CLK lo
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$10000D ACT CLK hi, get b3:2 of $000001
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$10000E NOP CKE CLK lo
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$10000F WR AP CLK hi, get b1:0 of $000001
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...
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$507FF0 WR AP CLK lo
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$503FF0 NOP CKE CLK lo
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$503FF1 NOP CKE CLK hi, get b7:6 of $0807FE
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$503FF2 NOP CKE CLK lo
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$503FF3 NOP CKE CLK hi, get b5:4 of $0807FE
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$503FF4 AREF CLK lo
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$503FF5 NOP CKE CLK hi, get b3:2 of $0807FE
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$503FF6 ACT CLK lo
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$503FF7 NOP CKE CLK hi, get b1:0 of $0807FE
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$503FF8 WR AP CLK lo
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$503FF3 AREF CLK hi, get b5:4 of $0807FE
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$503FF4 NOP CKE CLK lo
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$503FF5 ACT CLK hi, get b3:2 of $0807FE
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$503FF6 NOP CKE CLK lo
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$503FF7 WR AP CLK hi, get b1:0 of $0807FE
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$503FF8 NOP CKE CLK lo
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$503FF9 NOP CKE CLK hi, get b7:6 of $0807FF
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$503FFA NOP CKE CLK lo
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$503FFB NOP CKE CLK hi, get b5:4 of $0807FF
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$503FFC AREF CLK lo
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$503FFD NOP CKE CLK hi, get b3:2 of $0807FF
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$503FFE ACT CLK lo
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$503FFF NOP CKE CLK hi, get b1:0 of $0807FF
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$504000 WR AP CLK lo, /CS hi
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$504001 NOP CKE CLK lo
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...
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$50400F NOP CKE CLK lo
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$504010 NOP CKE SDRAMActv <= InitActv && ~InitInterrupted
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$503FFB AREF CLK hi, get b5:4 of $0807FF
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$503FFC NOP CKE CLK lo
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$503FFD ACT CLK hi, get b3:2 of $0807FF
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$503FFE NOP CKE CLK lo
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$503FFF WR AP CLK hi, get b1:0 of $0807FF
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$504000 NOP CKE CLK lo, /CS hi 3
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$504001 NOP CKE CLK lo, /CS hi 3
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$504002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
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...
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$5F5E0F flip 1hz, wrap
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$5F5E0F flip 1hz, wrap
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Init sequence
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Init State SDRAM Flash IS Other
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--------------------------------------------------------------------------------
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$00000-$0FFBF Nothing Nothing 0
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$00000 NOP CKE /CS hi, CLK lo
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...
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$0FF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFAF NOP CKE /CS lo, CLK lo
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$0FFB0-$0FFBF Init: Precharge Send read cmd ($03) 1
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$0FFB0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFB1 NOP CKE CLK hi
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$0FFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFB3 PC all CLK hi
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$0FFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFB5 NOP CKE CLK hi
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$0FFB6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFB7 NOP CKE CLK hi
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$0FFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFB9 NOP CKE CLK hi
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$0FFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFBB Load mode CLK hi
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$0FFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFBD NOP CKE CLK hi
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$0FFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFBF NOP CKE CLK hi
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$0FFC0-$0FFEF Init: mode & ref Send address ($000000) 2
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$0FFC0 NOP CKE CLK lo, MOSI 0 (b23)
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$0FFC1 NOP CKE CLK hi
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$0FFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFC3 AREF CLK hi
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$0FFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
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$0FFC5 NOP CKE CLK hi
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$0FFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFC7 NOP CKE CLK hi
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$0FFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFC9 NOP CKE CLK hi
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$0FFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFCB AREF CLK hi
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$0FFCC NOP CKE CLK lo, MOSI 0 (b17)
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$0FFCD NOP CKE CLK hi
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$0FFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFCF NOP CKE CLK hi
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$0FFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFD1 NOP CKE CLK hi
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$0FFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFD3 AREF CLK hi
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$0FFD4 NOP CKE CLK lo, MOSI 0 (b13)
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$0FFD5 NOP CKE CLK hi
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$0FFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFD7 NOP CKE CLK hi
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$0FFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFD9 NOP CKE CLK hi
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$0FFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFDB AREF CLK hi
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$0FFDC NOP CKE CLK lo, MOSI 0 (b9)
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$0FFDD NOP CKE CLK hi
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$0FFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFDF NOP CKE CLK hi
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$0FFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFE1 NOP CKE CLK hi
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$0FFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFE3 AREF CLK hi
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$0FFE4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFE5 NOP CKE CLK hi
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$0FFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFE7 NOP CKE CLK hi
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$0FFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFE9 NOP CKE CLK hi
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$0FFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFEB AREF CLK hi
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$0FFEC NOP CKE CLK lo, MOSI 0 (b1)
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$0FFED NOP CKE CLK hi
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$0FFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFEF NOP CKE CLK hi
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$0FFF0-$0FFFF Init: mode & ref 8 dummy clocks 2
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$0FFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFF1 NOP CKE CLK hi
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$0FFF2 NOP CKE CLK lo
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$0FFF3 AREF CLK hi
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$0FFF4 NOP CKE CLK lo
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$0FFF5 NOP CKE CLK hi
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$0FFF6 NOP CKE CLK lo
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$0FFF7 NOP CKE CLK hi
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$0FFF8 NOP CKE CLK lo
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$0FFF9 NOP CKE CLK hi
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$0FFFA NOP CKE CLK lo
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$0FFFB AREF CLK hi
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$0FFFC NOP CKE CLK lo
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$0FFFD NOP CKE CLK hi
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$0FFFE NOP CKE CLK lo
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$0FFFF NOP CKE CLK hi
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$10000-$2FFFF Write ROM data Shift in read data 3
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$10000 NOP CKE CLK lo
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$10001 NOP CKE CLK hi, get b7:6 of $000000
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$10002 NOP CKE CLK lo
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$10003 AREF CLK hi, get b5:4 of $000000
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$10004 NOP CKE CLK lo
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$10005 ACT CLK hi, get b3:2 of $000000
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$10006 NOP CKE CLK lo
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$10007 WR AP CLK hi, get b1:0 of $000000
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$10008 NOP CKE CLK lo
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$10009 NOP CKE CLK hi, get b7:6 of $000001
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$1000A NOP CKE CLK lo
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$1000B AREF CLK hi, get b5:4 of $000001
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$1000C NOP CKE CLK lo
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$1000D ACT CLK hi, get b3:2 of $000001
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$1000E NOP CKE CLK lo
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$1000F WR AP CLK hi, get b1:0 of $000001
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...
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$2FFF0 NOP CKE CLK lo
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$2FFF1 NOP CKE CLK hi, get b7:6 of $003FFE
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$2FFF2 NOP CKE CLK lo
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$2FFF3 AREF CLK hi, get b5:4 of $003FFE
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$2FFF4 NOP CKE CLK lo
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$2FFF5 ACT CLK hi, get b3:2 of $003FFE
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$2FFF6 NOP CKE CLK lo
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$2FFF7 WR AP CLK hi, get b1:0 of $003FFE
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$2FFF8 NOP CKE CLK lo
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$2FFF9 NOP CKE CLK hi, get b7:6 of $003FFF
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$2FFFA NOP CKE CLK lo
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$2FFFB AREF CLK hi, get b5:4 of $003FFF
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$2FFFC NOP CKE CLK lo
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$2FFFD ACT CLK hi, get b3:2 of $003FFF
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$2FFFE NOP CKE CLK lo
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$2FFFF WR AP CLK hi, get b1:0 of $003FFF
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$30000 NOP CKE CLK lo, /CS hi 3
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$30001 NOP CKE CLK lo, /CS hi 3
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$30002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
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139
Documentation/UFM Load
Normal file
139
Documentation/UFM Load
Normal file
@ -0,0 +1,139 @@
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UFM Load
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LState ARCLK ARShft DRCLK DRShft UFM
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--------------------------------------------------------------------------------
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$0000 0 1 0 0
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$0FBF 0 1 0 0
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...
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$0FC0 1 1 0 0
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$0FC1 1 1 0 0
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$0FC2 0 1 0 0
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$0FC3 0 1 0 0
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$0FC4 1 1 0 0
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$0FC5 1 1 0 0
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$0FC6 0 1 0 0
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$0FC7 0 1 0 0
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$0FC8 1 1 0 0
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$0FC9 1 1 0 0
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$0FCA 0 1 0 0
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$0FCB 0 1 0 0
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$0FCC 1 1 0 0
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$0FCD 1 1 0 0
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$0FCE 0 1 0 0
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$0FCF 0 1 0 0
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$0FD0 1 1 0 0
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$0FD1 1 1 0 0
|
||||
$0FD2 0 1 0 0
|
||||
$0FD3 0 1 0 0
|
||||
$0FD4 1 1 0 0
|
||||
$0FD5 1 1 0 0
|
||||
$0FD6 0 1 0 0
|
||||
$0FD7 0 1 0 0
|
||||
$0FD8 1 1 0 0
|
||||
$0FD9 1 1 0 0
|
||||
$0FDA 0 1 0 0
|
||||
$0FDB 0 1 0 0
|
||||
$0FDC 1 1 0 0
|
||||
$0FDD 1 1 0 0
|
||||
$0FDE 0 1 0 0
|
||||
$0FDF 0 1 0 0
|
||||
$0FE0 1 1 0 0
|
||||
$0FE1 1 1 0 0
|
||||
$0FE2 0 1 0 0
|
||||
$0FE3 0 1 0 0
|
||||
$0FE4 1 1 0 0
|
||||
$0FE5 1 1 0 0
|
||||
$0FE6 0 1 0 0
|
||||
$0FE7 0 1 0 0
|
||||
$0FE8 1 1 0 0
|
||||
$0FE9 1 1 0 0
|
||||
$0FEA 0 1 0 0
|
||||
$0FEB 0 1 0 0
|
||||
$0FEC 1 1 0 0
|
||||
$0FED 1 1 0 0
|
||||
$0FEE 0 1 0 0
|
||||
$0FEF 0 1 0 0
|
||||
$0FF0 1 1 0 0
|
||||
$0FF1 1 1 0 0
|
||||
$0FF2 0 1 0 0
|
||||
$0FF3 0 1 0 0
|
||||
$0FF4 1 1 0 0
|
||||
$0FF5 1 1 0 0
|
||||
$0FF6 0 1 0 0
|
||||
$0FF7 0 1 0 0
|
||||
$0FF8 1 1 0 0
|
||||
$0FF9 1 1 0 0
|
||||
$0FFA 0 1 0 0
|
||||
$0FFB 0 1 0 0
|
||||
$0FFC 1 1 0 0
|
||||
$0FFD 1 1 0 0
|
||||
$0FFE 0 1 0 0
|
||||
$0FFF 0 1 0 0
|
||||
|
||||
$1000 0 0 1 0 parallel load into DR
|
||||
$1001 0 0 1 0
|
||||
$1002 0 0 0 1
|
||||
$1003 0 0 0 1
|
||||
$1004 0 0 1 1 SetLoaded <= Dout
|
||||
$1005 0 0 1 1
|
||||
$1006 0 0 0 1
|
||||
$1007 0 0 0 1
|
||||
$1008 0 0 1 1 latch DR[14] (nSetFW[1])
|
||||
$1009 0 0 1 1
|
||||
$100A 0 0 0 1
|
||||
$100B 0 0 0 1
|
||||
$100C 0 0 1 1 latch DR[13] (nSetFW[0])
|
||||
$100D 0 0 1 1
|
||||
$100E 0 0 0 1
|
||||
$100F 0 0 0 1
|
||||
$1010 0 0 0 1 latch DR[12] (nSetLim8M)
|
||||
$1011 0 0 0 1
|
||||
$1012 0 0 0 1
|
||||
$1013 0 0 0 1
|
||||
$1014 0 0 0 1
|
||||
$1015 0 0 0 1
|
||||
$1016 0 0 0 1
|
||||
$1017 0 0 0 1
|
||||
$1018 0 0 0 1
|
||||
$1019 0 0 0 1
|
||||
$101A 0 0 0 1
|
||||
$101B 0 0 0 1
|
||||
$101C 1 0 0 1 Increment address
|
||||
$101D 1 0 0 1
|
||||
$101E 0 0 0 1
|
||||
$101F 0 0 0 1
|
||||
...
|
||||
$2FE0 0 0 1 0 parallel load into DR
|
||||
$2FE1 0 0 1 0
|
||||
$2FE2 0 0 0 1
|
||||
$2FE3 0 0 0 1
|
||||
$2FE4 0 0 1 1 SetLoaded <= Dout
|
||||
$2FE5 0 0 1 1
|
||||
$2FE6 0 0 0 1
|
||||
$2FE7 0 0 0 1
|
||||
$2FE8 0 0 1 1 latch DR[14] (nSetFW[1])
|
||||
$2FE9 0 0 1 1
|
||||
$2FEA 0 0 0 1
|
||||
$2FEB 0 0 0 1
|
||||
$2FEC 0 0 1 1 latch DR[13] (nSetFW[0])
|
||||
$2FED 0 0 1 1
|
||||
$2FEE 0 0 0 1
|
||||
$2FEF 0 0 0 1
|
||||
$2FF0 0 0 0 1 latch DR[12] (nSetLim8M)
|
||||
$2FF1 0 0 0 1
|
||||
$2FF2 0 0 0 1
|
||||
$2FF3 0 0 0 1
|
||||
$2FF4 0 0 0 1
|
||||
$2FF5 0 0 0 1
|
||||
$2FF6 0 0 0 1
|
||||
$2FF7 0 0 0 1
|
||||
$2FF8 0 0 0 1
|
||||
$2FF9 0 0 0 1
|
||||
$2FFA 0 0 0 1
|
||||
$2FFB 0 0 0 1
|
||||
$2FFC 1 0 0 1 Increment address
|
||||
$2FFD 1 0 0 1
|
||||
$2FFE 0 0 0 1
|
||||
$2FFF 0 0 0 1
|
||||
|
||||
$3000 0 0 0 0 Everything 0, set SetLoaded
|
||||
30
cpld/GR8RAM.qpf
Executable file
30
cpld/GR8RAM.qpf
Executable file
@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:41:40 March 15, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "13:41:40 March 15, 2021"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "GR8RAM"
|
||||
59
cpld/GR8RAM.qsf
Executable file
59
cpld/GR8RAM.qsf
Executable file
@ -0,0 +1,59 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 13:41:40 March 15, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# GR8RAM_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "MAX II"
|
||||
set_global_assignment -name DEVICE EPM240T100C5
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name QIP_FILE UFM.qip
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
807
cpld/GR8RAM.v
807
cpld/GR8RAM.v
File diff suppressed because it is too large
Load Diff
3
cpld/UFM.qip
Executable file
3
cpld/UFM.qip
Executable file
@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
|
||||
268
cpld/UFM.v
Executable file
268
cpld/UFM.v
Executable file
@ -0,0 +1,268 @@
|
||||
// megafunction wizard: %ALTUFM_NONE%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: ALTUFM_NONE
|
||||
|
||||
// ============================================================
|
||||
// File Name: UFM.v
|
||||
// Megafunction Name(s):
|
||||
// ALTUFM_NONE
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// maxii
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
|
||||
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ VERSION_END
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
|
||||
|
||||
//synthesis_resources = maxii_ufm 1
|
||||
//synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
//synopsys translate_on
|
||||
module UFM_altufm_none_0ep
|
||||
(
|
||||
arclk,
|
||||
ardin,
|
||||
arshft,
|
||||
busy,
|
||||
drclk,
|
||||
drdin,
|
||||
drdout,
|
||||
drshft,
|
||||
erase,
|
||||
osc,
|
||||
oscena,
|
||||
program,
|
||||
rtpbusy) ;
|
||||
input arclk;
|
||||
input ardin;
|
||||
input arshft;
|
||||
output busy;
|
||||
input drclk;
|
||||
input drdin;
|
||||
output drdout;
|
||||
input drshft;
|
||||
input erase;
|
||||
output osc;
|
||||
input oscena;
|
||||
input program;
|
||||
output rtpbusy;
|
||||
|
||||
wire wire_maxii_ufm_block1_bgpbusy;
|
||||
wire wire_maxii_ufm_block1_busy;
|
||||
wire wire_maxii_ufm_block1_drdout;
|
||||
wire wire_maxii_ufm_block1_osc;
|
||||
wire ufm_arclk;
|
||||
wire ufm_ardin;
|
||||
wire ufm_arshft;
|
||||
wire ufm_bgpbusy;
|
||||
wire ufm_busy;
|
||||
wire ufm_drclk;
|
||||
wire ufm_drdin;
|
||||
wire ufm_drdout;
|
||||
wire ufm_drshft;
|
||||
wire ufm_erase;
|
||||
wire ufm_osc;
|
||||
wire ufm_oscena;
|
||||
wire ufm_program;
|
||||
|
||||
maxii_ufm maxii_ufm_block1
|
||||
(
|
||||
.arclk(ufm_arclk),
|
||||
.ardin(ufm_ardin),
|
||||
.arshft(ufm_arshft),
|
||||
.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
|
||||
.busy(wire_maxii_ufm_block1_busy),
|
||||
.drclk(ufm_drclk),
|
||||
.drdin(ufm_drdin),
|
||||
.drdout(wire_maxii_ufm_block1_drdout),
|
||||
.drshft(ufm_drshft),
|
||||
.erase(ufm_erase),
|
||||
.osc(wire_maxii_ufm_block1_osc),
|
||||
.oscena(ufm_oscena),
|
||||
.program(ufm_program)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.ctrl_bgpbusy(1'b0),
|
||||
.devclrn(1'b1),
|
||||
.devpor(1'b1),
|
||||
.sbdin(1'b0),
|
||||
.sbdout()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
maxii_ufm_block1.address_width = 9,
|
||||
maxii_ufm_block1.erase_time = 500000000,
|
||||
maxii_ufm_block1.init_file = "none",
|
||||
maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.osc_sim_setting = 180000,
|
||||
maxii_ufm_block1.program_time = 1600000,
|
||||
maxii_ufm_block1.lpm_type = "maxii_ufm";
|
||||
assign
|
||||
busy = ufm_busy,
|
||||
drdout = ufm_drdout,
|
||||
osc = ufm_osc,
|
||||
rtpbusy = ufm_bgpbusy,
|
||||
ufm_arclk = arclk,
|
||||
ufm_ardin = ardin,
|
||||
ufm_arshft = arshft,
|
||||
ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
|
||||
ufm_busy = wire_maxii_ufm_block1_busy,
|
||||
ufm_drclk = drclk,
|
||||
ufm_drdin = drdin,
|
||||
ufm_drdout = wire_maxii_ufm_block1_drdout,
|
||||
ufm_drshft = drshft,
|
||||
ufm_erase = erase,
|
||||
ufm_osc = wire_maxii_ufm_block1_osc,
|
||||
ufm_oscena = oscena,
|
||||
ufm_program = program;
|
||||
endmodule //UFM_altufm_none_0ep
|
||||
//VALID FILE
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module UFM (
|
||||
arclk,
|
||||
ardin,
|
||||
arshft,
|
||||
drclk,
|
||||
drdin,
|
||||
drshft,
|
||||
erase,
|
||||
oscena,
|
||||
program,
|
||||
busy,
|
||||
drdout,
|
||||
osc,
|
||||
rtpbusy);
|
||||
|
||||
input arclk;
|
||||
input ardin;
|
||||
input arshft;
|
||||
input drclk;
|
||||
input drdin;
|
||||
input drshft;
|
||||
input erase;
|
||||
input oscena;
|
||||
input program;
|
||||
output busy;
|
||||
output drdout;
|
||||
output osc;
|
||||
output rtpbusy;
|
||||
|
||||
wire sub_wire0;
|
||||
wire sub_wire1;
|
||||
wire sub_wire2;
|
||||
wire sub_wire3;
|
||||
wire osc = sub_wire0;
|
||||
wire rtpbusy = sub_wire1;
|
||||
wire drdout = sub_wire2;
|
||||
wire busy = sub_wire3;
|
||||
|
||||
UFM_altufm_none_0ep UFM_altufm_none_0ep_component (
|
||||
.arshft (arshft),
|
||||
.drclk (drclk),
|
||||
.erase (erase),
|
||||
.program (program),
|
||||
.arclk (arclk),
|
||||
.drdin (drdin),
|
||||
.oscena (oscena),
|
||||
.ardin (ardin),
|
||||
.drshft (drshft),
|
||||
.osc (sub_wire0),
|
||||
.rtpbusy (sub_wire1),
|
||||
.drdout (sub_wire2),
|
||||
.busy (sub_wire3));
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
|
||||
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
|
||||
// Retrieval info: CONSTANT: LPM_FILE STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
|
||||
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
|
||||
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
|
||||
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
|
||||
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
|
||||
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
|
||||
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
|
||||
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
|
||||
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
|
||||
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
|
||||
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
|
||||
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
|
||||
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
|
||||
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
|
||||
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
|
||||
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
|
||||
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
|
||||
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
|
||||
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
|
||||
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
|
||||
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
|
||||
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
|
||||
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
|
||||
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
|
||||
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
|
||||
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
|
||||
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
|
||||
// Retrieval info: LIB_FILE: maxii
|
||||
BIN
cpld/db/GR8RAM.(0).cnf.cdb
Executable file
BIN
cpld/db/GR8RAM.(0).cnf.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(0).cnf.hdb
Executable file
BIN
cpld/db/GR8RAM.(0).cnf.hdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(1).cnf.cdb
Executable file
BIN
cpld/db/GR8RAM.(1).cnf.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(1).cnf.hdb
Executable file
BIN
cpld/db/GR8RAM.(1).cnf.hdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(2).cnf.cdb
Executable file
BIN
cpld/db/GR8RAM.(2).cnf.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.(2).cnf.hdb
Executable file
BIN
cpld/db/GR8RAM.(2).cnf.hdb
Executable file
Binary file not shown.
6
cpld/db/GR8RAM.asm.qmsg
Executable file
6
cpld/db/GR8RAM.asm.qmsg
Executable file
@ -0,0 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056850427 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:50 2021 " "Processing started: Thu Mar 18 04:40:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616056851802 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616056851833 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:52 2021 " "Processing ended: Thu Mar 18 04:40:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616056852411 ""}
|
||||
BIN
cpld/db/GR8RAM.asm.rdb
Executable file
BIN
cpld/db/GR8RAM.asm.rdb
Executable file
Binary file not shown.
5
cpld/db/GR8RAM.cbx.xml
Executable file
5
cpld/db/GR8RAM.cbx.xml
Executable file
@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="GR8RAM">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
BIN
cpld/db/GR8RAM.cmp.cdb
Executable file
BIN
cpld/db/GR8RAM.cmp.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.cmp.hdb
Executable file
BIN
cpld/db/GR8RAM.cmp.hdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.cmp.idb
Executable file
BIN
cpld/db/GR8RAM.cmp.idb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.cmp.kpt
Executable file
BIN
cpld/db/GR8RAM.cmp.kpt
Executable file
Binary file not shown.
1
cpld/db/GR8RAM.cmp.logdb
Executable file
1
cpld/db/GR8RAM.cmp.logdb
Executable file
@ -0,0 +1 @@
|
||||
v1
|
||||
BIN
cpld/db/GR8RAM.cmp.rdb
Executable file
BIN
cpld/db/GR8RAM.cmp.rdb
Executable file
Binary file not shown.
3
cpld/db/GR8RAM.db_info
Executable file
3
cpld/db/GR8RAM.db_info
Executable file
@ -0,0 +1,3 @@
|
||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
Version_Index = 302049280
|
||||
Creation_Time = Mon Mar 15 13:41:40 2021
|
||||
BIN
cpld/db/GR8RAM.eco.cdb
Executable file
BIN
cpld/db/GR8RAM.eco.cdb
Executable file
Binary file not shown.
58
cpld/db/GR8RAM.fit.qmsg
Executable file
58
cpld/db/GR8RAM.fit.qmsg
Executable file
File diff suppressed because one or more lines are too long
233
cpld/db/GR8RAM.hier_info
Executable file
233
cpld/db/GR8RAM.hier_info
Executable file
@ -0,0 +1,233 @@
|
||||
|GR8RAM
|
||||
C25M => SA[0]~reg0.CLK
|
||||
C25M => SA[1]~reg0.CLK
|
||||
C25M => SA[2]~reg0.CLK
|
||||
C25M => SA[3]~reg0.CLK
|
||||
C25M => SA[4]~reg0.CLK
|
||||
C25M => SA[5]~reg0.CLK
|
||||
C25M => SA[6]~reg0.CLK
|
||||
C25M => SA[7]~reg0.CLK
|
||||
C25M => SA[8]~reg0.CLK
|
||||
C25M => SA[9]~reg0.CLK
|
||||
C25M => SA[10]~reg0.CLK
|
||||
C25M => SA[11]~reg0.CLK
|
||||
C25M => SA[12]~reg0.CLK
|
||||
C25M => SBA[0]~reg0.CLK
|
||||
C25M => SBA[1]~reg0.CLK
|
||||
C25M => DQML~reg0.CLK
|
||||
C25M => DQMH~reg0.CLK
|
||||
C25M => nSWE~reg0.CLK
|
||||
C25M => nCAS~reg0.CLK
|
||||
C25M => nRAS~reg0.CLK
|
||||
C25M => nRCS~reg0.CLK
|
||||
C25M => RCKE~reg0.CLK
|
||||
C25M => IS[0].CLK
|
||||
C25M => IS[1].CLK
|
||||
C25M => RefDone.CLK
|
||||
C25M => S[0].CLK
|
||||
C25M => S[1].CLK
|
||||
C25M => S[2].CLK
|
||||
C25M => S[3].CLK
|
||||
C25M => SDOE.CLK
|
||||
C25M => WRD[0].CLK
|
||||
C25M => WRD[1].CLK
|
||||
C25M => WRD[2].CLK
|
||||
C25M => WRD[3].CLK
|
||||
C25M => WRD[4].CLK
|
||||
C25M => WRD[5].CLK
|
||||
C25M => WRD[6].CLK
|
||||
C25M => WRD[7].CLK
|
||||
C25M => DRDIn.CLK
|
||||
C25M => SetLoaded.CLK
|
||||
C25M => SetLim8M.CLK
|
||||
C25M => SetFW[0].CLK
|
||||
C25M => SetFW[1].CLK
|
||||
C25M => DRShift.CLK
|
||||
C25M => DRCLK.CLK
|
||||
C25M => ARShift.CLK
|
||||
C25M => ARCLK.CLK
|
||||
C25M => MOSIOE.CLK
|
||||
C25M => MOSIout.CLK
|
||||
C25M => FCS.CLK
|
||||
C25M => FCKEN.CLK
|
||||
C25M => FCK~reg0.CLK
|
||||
C25M => Bank[1].CLK
|
||||
C25M => Addr[0].CLK
|
||||
C25M => Addr[1].CLK
|
||||
C25M => Addr[2].CLK
|
||||
C25M => Addr[3].CLK
|
||||
C25M => Addr[4].CLK
|
||||
C25M => Addr[5].CLK
|
||||
C25M => Addr[6].CLK
|
||||
C25M => Addr[7].CLK
|
||||
C25M => Addr[8].CLK
|
||||
C25M => Addr[9].CLK
|
||||
C25M => Addr[10].CLK
|
||||
C25M => Addr[11].CLK
|
||||
C25M => Addr[12].CLK
|
||||
C25M => Addr[13].CLK
|
||||
C25M => Addr[14].CLK
|
||||
C25M => Addr[15].CLK
|
||||
C25M => Addr[16].CLK
|
||||
C25M => Addr[17].CLK
|
||||
C25M => Addr[18].CLK
|
||||
C25M => Addr[19].CLK
|
||||
C25M => Addr[20].CLK
|
||||
C25M => Addr[21].CLK
|
||||
C25M => Addr[22].CLK
|
||||
C25M => Addr[23].CLK
|
||||
C25M => RAMSEL.CLK
|
||||
C25M => nWEcur.CLK
|
||||
C25M => RAcur[0].CLK
|
||||
C25M => RAcur[1].CLK
|
||||
C25M => RAcur[2].CLK
|
||||
C25M => RAcur[3].CLK
|
||||
C25M => RAcur[4].CLK
|
||||
C25M => RAcur[5].CLK
|
||||
C25M => RAcur[6].CLK
|
||||
C25M => RAcur[7].CLK
|
||||
C25M => RAcur[8].CLK
|
||||
C25M => RAcur[9].CLK
|
||||
C25M => RAcur[10].CLK
|
||||
C25M => RAcur[11].CLK
|
||||
C25M => RACr.CLK
|
||||
C25M => DEVSELr.CLK
|
||||
C25M => SDRAMActv.CLK
|
||||
C25M => InitActv.CLK
|
||||
C25M => CmdActv.CLK
|
||||
C25M => InitIntr.CLK
|
||||
C25M => nRESout~reg0.CLK
|
||||
C25M => LS[0].CLK
|
||||
C25M => LS[1].CLK
|
||||
C25M => LS[2].CLK
|
||||
C25M => LS[3].CLK
|
||||
C25M => LS[4].CLK
|
||||
C25M => LS[5].CLK
|
||||
C25M => LS[6].CLK
|
||||
C25M => LS[7].CLK
|
||||
C25M => LS[8].CLK
|
||||
C25M => LS[9].CLK
|
||||
C25M => LS[10].CLK
|
||||
C25M => LS[11].CLK
|
||||
C25M => LS[12].CLK
|
||||
C25M => LS[13].CLK
|
||||
C25M => LS[14].CLK
|
||||
C25M => LS[15].CLK
|
||||
C25M => LS[16].CLK
|
||||
C25M => LS[17].CLK
|
||||
C25M => nBODf.CLK
|
||||
C25M => nBODf0.CLK
|
||||
C25M => nRESr.CLK
|
||||
C25M => nBODr.CLK
|
||||
C25M => nRESr0.CLK
|
||||
C25M => nBODr0.CLK
|
||||
C25M => PHI0r2.CLK
|
||||
C25M => PHI0r1.CLK
|
||||
C25M => PHI0r0.CLK
|
||||
C25M => DEVSELr0.CLK
|
||||
PHI0 => PHI0r0.DATAIN
|
||||
nBOD => nBODr0.DATAIN
|
||||
nRES => nRESr0.DATAIN
|
||||
nIOSEL => ~NO_FANOUT~
|
||||
nDEVSEL => DEVSELr0.DATAIN
|
||||
nIOSTRB => ~NO_FANOUT~
|
||||
RA[0] => RAcur[0].DATAIN
|
||||
RA[1] => RAcur[1].DATAIN
|
||||
RA[2] => RAcur[2].DATAIN
|
||||
RA[3] => RAcur[3].DATAIN
|
||||
RA[4] => RAcur[4].DATAIN
|
||||
RA[5] => RAcur[5].DATAIN
|
||||
RA[6] => RAcur[6].DATAIN
|
||||
RA[7] => RAcur[7].DATAIN
|
||||
RA[8] => RAcur[8].DATAIN
|
||||
RA[9] => RAcur[9].DATAIN
|
||||
RA[10] => RAcur[10].DATAIN
|
||||
RA[11] => RAcur[11].DATAIN
|
||||
RA[12] => Equal3.IN3
|
||||
RA[13] => Equal3.IN2
|
||||
RA[14] => Equal3.IN1
|
||||
RA[15] => Equal3.IN0
|
||||
nWE => nWEcur.DATAIN
|
||||
RAdir <= <VCC>
|
||||
RD[0] <> RD[0]
|
||||
RD[1] <> RD[1]
|
||||
RD[2] <> RD[2]
|
||||
RD[3] <> RD[3]
|
||||
RD[4] <> RD[4]
|
||||
RD[5] <> RD[5]
|
||||
RD[6] <> RD[6]
|
||||
RD[7] <> RD[7]
|
||||
RDdir <= <VCC>
|
||||
DMAin => DMAout.DATAIN
|
||||
DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
|
||||
INTin => INTout.DATAIN
|
||||
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
SD[0] <> SD[0]
|
||||
SD[1] <> SD[1]
|
||||
SD[2] <> SD[2]
|
||||
SD[3] <> SD[3]
|
||||
SD[4] <> SD[4]
|
||||
SD[5] <> SD[5]
|
||||
SD[6] <> SD[6]
|
||||
SD[7] <> SD[7]
|
||||
nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
|
||||
FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
MISO => WRD.DATAB
|
||||
MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|GR8RAM|UFM:UFM_inst
|
||||
arclk => arclk.IN1
|
||||
ardin => ardin.IN1
|
||||
arshft => arshft.IN1
|
||||
drclk => drclk.IN1
|
||||
drdin => drdin.IN1
|
||||
drshft => drshft.IN1
|
||||
erase => erase.IN1
|
||||
oscena => oscena.IN1
|
||||
program => program.IN1
|
||||
busy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.busy
|
||||
drdout <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.drdout
|
||||
osc <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.osc
|
||||
rtpbusy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.rtpbusy
|
||||
|
||||
|
||||
|GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component
|
||||
arclk => maxii_ufm_block1.ARCLK
|
||||
ardin => maxii_ufm_block1.ARDIN
|
||||
arshft => maxii_ufm_block1.ARSHFT
|
||||
busy <= maxii_ufm_block1.BUSY
|
||||
drclk => maxii_ufm_block1.DRCLK
|
||||
drdin => maxii_ufm_block1.DRDIN
|
||||
drdout <= maxii_ufm_block1.DRDOUT
|
||||
drshft => maxii_ufm_block1.DRSHFT
|
||||
erase => maxii_ufm_block1.ERASE
|
||||
osc <= maxii_ufm_block1.OSC
|
||||
oscena => maxii_ufm_block1.OSCENA
|
||||
program => maxii_ufm_block1.PROGRAM
|
||||
rtpbusy <= maxii_ufm_block1.BGPBUSY
|
||||
|
||||
|
||||
BIN
cpld/db/GR8RAM.hif
Executable file
BIN
cpld/db/GR8RAM.hif
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.ipinfo
Executable file
BIN
cpld/db/GR8RAM.ipinfo
Executable file
Binary file not shown.
50
cpld/db/GR8RAM.lpc.html
Executable file
50
cpld/db/GR8RAM.lpc.html
Executable file
@ -0,0 +1,50 @@
|
||||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >UFM_inst|UFM_altufm_none_0ep_component</TD>
|
||||
<TD >9</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >4</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >UFM_inst</TD>
|
||||
<TD >9</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >4</TD>
|
||||
<TD >2</TD>
|
||||
<TD >2</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
BIN
cpld/db/GR8RAM.lpc.rdb
Executable file
BIN
cpld/db/GR8RAM.lpc.rdb
Executable file
Binary file not shown.
8
cpld/db/GR8RAM.lpc.txt
Executable file
8
cpld/db/GR8RAM.lpc.txt
Executable file
@ -0,0 +1,8 @@
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; UFM_inst|UFM_altufm_none_0ep_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
BIN
cpld/db/GR8RAM.map.cdb
Executable file
BIN
cpld/db/GR8RAM.map.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.map.hdb
Executable file
BIN
cpld/db/GR8RAM.map.hdb
Executable file
Binary file not shown.
1
cpld/db/GR8RAM.map.logdb
Executable file
1
cpld/db/GR8RAM.map.logdb
Executable file
@ -0,0 +1 @@
|
||||
v1
|
||||
35
cpld/db/GR8RAM.map.qmsg
Executable file
35
cpld/db/GR8RAM.map.qmsg
Executable file
@ -0,0 +1,35 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136944860 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:44 2021 " "Processing started: Fri Mar 19 02:55:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136946282 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946532 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946548 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""}
|
||||
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946860 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136946860 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136946892 ""}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947142 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947204 ""}
|
||||
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 181 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616136948751 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616136948751 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RDdir VCC " "Pin \"RDdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RDdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RCKE VCC " "Pin \"RCKE\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 448 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RCKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616136949454 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSEL " "No output dependent on input pin \"nIOSEL\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSEL"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSTRB " "No output dependent on input pin \"nIOSTRB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSTRB"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1616136950063 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "417 " "Implemented 417 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_LCELLS" "343 " "Implemented 343 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616136950095 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616136950095 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136950376 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:50 2021 " "Processing ended: Fri Mar 19 02:55:50 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""}
|
||||
BIN
cpld/db/GR8RAM.map.rdb
Executable file
BIN
cpld/db/GR8RAM.map.rdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.pplq.rdb
Executable file
BIN
cpld/db/GR8RAM.pplq.rdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.pre_map.hdb
Executable file
BIN
cpld/db/GR8RAM.pre_map.hdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.pti_db_list.ddb
Executable file
BIN
cpld/db/GR8RAM.pti_db_list.ddb
Executable file
Binary file not shown.
0
cpld/db/GR8RAM.quiproj.3716.rdr.flock
Executable file
0
cpld/db/GR8RAM.quiproj.3716.rdr.flock
Executable file
BIN
cpld/db/GR8RAM.root_partition.map.reg_db.cdb
Executable file
BIN
cpld/db/GR8RAM.root_partition.map.reg_db.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.routing.rdb
Executable file
BIN
cpld/db/GR8RAM.routing.rdb
Executable file
Binary file not shown.
4
cpld/db/GR8RAM.rpp.qmsg
Executable file
4
cpld/db/GR8RAM.rpp.qmsg
Executable file
@ -0,0 +1,4 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136540772 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136540788 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:49:00 2021 " "Processing started: Fri Mar 19 02:49:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136540788 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136540788 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp GR8RAM -c GR8RAM --netlist_type=sgate " "Command: quartus_rpp GR8RAM -c GR8RAM --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136540788 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "202 " "Peak virtual memory: 202 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:49:01 2021 " "Processing ended: Fri Mar 19 02:49:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136541319 ""}
|
||||
BIN
cpld/db/GR8RAM.rtlv.hdb
Executable file
BIN
cpld/db/GR8RAM.rtlv.hdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.rtlv_sg.cdb
Executable file
BIN
cpld/db/GR8RAM.rtlv_sg.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.rtlv_sg_swap.cdb
Executable file
BIN
cpld/db/GR8RAM.rtlv_sg_swap.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.sgate.rvd
Executable file
BIN
cpld/db/GR8RAM.sgate.rvd
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.sgate_sm.rvd
Executable file
BIN
cpld/db/GR8RAM.sgate_sm.rvd
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.sgdiff.cdb
Executable file
BIN
cpld/db/GR8RAM.sgdiff.cdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.sgdiff.hdb
Executable file
BIN
cpld/db/GR8RAM.sgdiff.hdb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.sld_design_entry.sci
Executable file
BIN
cpld/db/GR8RAM.sld_design_entry.sci
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.sld_design_entry_dsc.sci
Executable file
BIN
cpld/db/GR8RAM.sld_design_entry_dsc.sci
Executable file
Binary file not shown.
1
cpld/db/GR8RAM.smart_action.txt
Executable file
1
cpld/db/GR8RAM.smart_action.txt
Executable file
@ -0,0 +1 @@
|
||||
FIT
|
||||
23
cpld/db/GR8RAM.sta.qmsg
Executable file
23
cpld/db/GR8RAM.sta.qmsg
Executable file
@ -0,0 +1,23 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056855068 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:54 2021 " "Processing started: Thu Mar 18 04:40:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616056855099 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616056855286 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616056856161 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616056856536 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616056856896 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616056857052 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616056857052 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616056857115 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616056857240 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.447 -415.877 C25M " " -8.447 -415.877 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.286 " "Worst-case hold slack is -16.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.286 -16.286 DRCLK " " -16.286 -16.286 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.579 -1.579 C25M " " -1.579 -1.579 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857333 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857365 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616056857677 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:58 2021 " "Processing ended: Thu Mar 18 04:40:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""}
|
||||
BIN
cpld/db/GR8RAM.sta.rdb
Executable file
BIN
cpld/db/GR8RAM.sta.rdb
Executable file
Binary file not shown.
0
cpld/db/GR8RAM.syn_hier_info
Executable file
0
cpld/db/GR8RAM.syn_hier_info
Executable file
BIN
cpld/db/GR8RAM.tis_db_list.ddb
Executable file
BIN
cpld/db/GR8RAM.tis_db_list.ddb
Executable file
Binary file not shown.
BIN
cpld/db/GR8RAM.vpr.ammdb
Executable file
BIN
cpld/db/GR8RAM.vpr.ammdb
Executable file
Binary file not shown.
0
cpld/db/logic_util_heursitic.dat
Executable file
0
cpld/db/logic_util_heursitic.dat
Executable file
33
cpld/db/prev_cmp_GR8RAM.qmsg
Executable file
33
cpld/db/prev_cmp_GR8RAM.qmsg
Executable file
@ -0,0 +1,33 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136912610 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:12 2021 " "Processing started: Fri Mar 19 02:55:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136914344 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914954 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136914985 ""}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
|
||||
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "FCK gr8ram.v(190) " "Can't resolve multiple constant drivers for net \"FCK\" at gr8ram.v(190)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 190 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""}
|
||||
{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "gr8ram.v(187) " "Constant driver at gr8ram.v(187)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 187 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""}
|
||||
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Quartus II" 0 -1 1616136915016 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136915188 ""}
|
||||
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 17 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 3 errors, 17 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:15 2021 " "Processing ended: Fri Mar 19 02:55:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""}
|
||||
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 17 s " "Quartus II Full Compilation was unsuccessful. 5 errors, 17 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136916625 ""}
|
||||
25
cpld/greybox_tmp/cbx_args.txt
Executable file
25
cpld/greybox_tmp/cbx_args.txt
Executable file
@ -0,0 +1,25 @@
|
||||
ERASE_TIME=500000000
|
||||
INTENDED_DEVICE_FAMILY="MAX II"
|
||||
LPM_FILE=UNUSED
|
||||
LPM_HINT=UNUSED
|
||||
LPM_TYPE=altufm_none
|
||||
OSC_FREQUENCY=180000
|
||||
PORT_ARCLKENA=PORT_UNUSED
|
||||
PORT_DRCLKENA=PORT_UNUSED
|
||||
PROGRAM_TIME=1600000
|
||||
WIDTH_UFM_ADDRESS=9
|
||||
DEVICE_FAMILY="MAX II"
|
||||
CBX_AUTO_BLACKBOX=ALL
|
||||
arclk
|
||||
ardin
|
||||
arshft
|
||||
busy
|
||||
drclk
|
||||
drdin
|
||||
drdout
|
||||
drshft
|
||||
erase
|
||||
osc
|
||||
oscena
|
||||
program
|
||||
rtpbusy
|
||||
11
cpld/incremental_db/README
Executable file
11
cpld/incremental_db/README
Executable file
@ -0,0 +1,11 @@
|
||||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||